FN8174.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9271

Single Supply/Low Power/256-Tap/SPI Bus

Single Digitally-Controlled (XDCPTM)

Potentiometer

FEATURES

· 256 Resistor Taps
· SPI Serial Interface for write, read, and transfer

operations of the potentiometer

· Wiper Resistance, 100

typical @ V

= 5V

· 16 Nonvolatile Data Registers
· Nonvolatile Storage of Multiple Wiper Positions
· Power-on Recall. Loads Saved Wiper Position on

Power-up.

· Standby Current < 3µA Max
· V

: 2.7V to 5.5V Operation

· 50k

, 100k

versions of End to End Resistance

· 100 yr. Data Retention
· Endurance: 100,000 Data Changes per Bit per

Register

· 14-Lead TSSOP
· Low Power CMOS

DESCRIPTION

The X9271 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.

The digital controlled potentiometer is implemented
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and a four
nonvolatile Data Registers that can be directly written to
and read by the user. The contents of the WCR controls
the position of the wiper on the resistor array though the
switches. Powerup recalls the contents of the default
data register (DR0) to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

FUNCTIONAL DIAGRAM

50k

and 100k

POT

SPI
Bus

Power-on Recall

Wiper Counter
Register (WCR)

Data Registers

16 Bytes

Interface

Bus

Interface

and Control

Address

Data

Status

Write
Read

Transfer

Inc/Dec

Control

256-taps

Data Sheet

March 31, 2005

FN8174.1

March 31, 2005

DETAILED FUNCTIONAL DIAGRAM

CIRCUIT LEVEL APPLICATIONS

· Vary the gain of a voltage amplifier

· Provide programmable dc reference voltages for

comparators and detectors

· Control the volume in audio circuits

· Trim out the offset voltage error in a voltage amplifier

circuit

· Set the output voltage of a voltage regulator

· Trim the resistance in Wheatstone bridge circuits

· Control the gain, characteristic frequency and

Q-factor in filter circuits

· Set the scale factor and zero point in sensor signal

conditioning circuits

· Vary the frequency and duty cycle of timer ICs

· Vary the dc biasing of a pin diode attenuator in RF

circuits

· Provide a control variable (I, V, or R) in feedback

circuits

SYSTEM LEVEL APPLICATIONS

· Adjust the contrast in LCD displays

· Control the power level of LED transmitters in

communication systems

· Set and regulate the DC biasing point in an RF

power amplifier in wireless systems

· Control the gain in audio and home entertainment

systems

· Provide the variable DC bias for tuners in RF

wireless systems

· Set the operating points in temperature control

systems

· Control the operating point for sensors in industrial

systems

· Trim offset and gain errors in artificial intelligent

systems

WIPER

COUNTER

(WCR)

DATA

INTERFACE

AND

CONTROL

CIRCUITRY

Bank 0

Bank 1

Bank 2

Bank 3

12 additional nonvolatile registers
3 Banks of 4 registers x 8-bits

SCK

HOLD

Control

256-taps

50k

and 100k

Power-on Recall

X9271

FN8174.1

March 31, 2005

PIN CONFIGURATION

PIN ASSIGNMENTS

SCK

TSSOP

X9271

HOLD

TSSOP

Symbol

Function

Serial Data Output.

Device Address.

No Connect.

Chip Select.

SCK

Serial Clock.

Serial Data Input.

System Ground.

Hardware Write Protect.

Device Address.

HOLD

Device select. Pause the serial bus.

Wiper Terminal of the Potentiometer.

High Terminal of the Potentiometer.

Low Terminal of the Potentiometer.

System Supply Voltage.

X9271

FN8174.1

March 31, 2005

PIN DESCRIPTIONS

Bus Interface Pins

ERIAL

UTPUT

(SO)

SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.

ERIAL

NPUT

SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.

ERIAL

LOCK

(SCK)

The SCK input is used to clock data into and out of the
X9271.

OLD

(HOLD)

HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause the
serial communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH at
all times. CMOS level input.

EVICE

DDRESS

(A1 - A0)

The address inputs are used to set the the 8-bit slave
address. A match in the slave address serial data
stream must be made with the address input in order
to initiate communication with the X9271.

HIP

ELECT

(CS)

When CS is HIGH, the X9271 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9271, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.

Potentiometer Pins

, R

The R

and R

pins are equivalent to the terminal

connections on a mechanical potentiometer.

The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.

Supply Pins

YSTEM

UPPLY

OLTAGE

)

AND

UPPLY

ROUND

)

The V

pin is the system supply voltage. The V

pin is the system ground.

Other Pins

ARDWARE

RITE

ROTECT

NPUT

(WP)

The WP pin when LOW prevents nonvolatile writes to
the Data Registers.

ONNECT

No connect pins should be left floating. This pins are
used for Intersil manufacturing and testing purposes.

X9271

FN8174.1

March 31, 2005

PRINCIPLES OF OPERATION

Device Description

ERIAL

NTERFACE

The X9271 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.

The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.

RRAY

ESCRIPTION

The X9271 is comprised of a resistor array (See
Figure 1). The array contains the equivalent of 255
discrete resistive segments that are connected in

series. The physical ends of each array are equivalent
to the fixed terminals of a mechanical potentiometer
(R

and R

inputs).

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R

) output. Within each individual array only one

switch may be turned on at a time.

These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).

OWER

AND

OWN

ECOMMENDATIONS

There are no restrictions on the power-up or power-
down conditions of V

and the voltages applied to

the potentiometer pins provided that V

is always

more positive than or equal to V

, V

, and V

, i.e.,

, V

. The V

ramp rate specification is

always in effect.

Figure 1. Detailed Potentiometer Block Diagram

SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

SERIAL
BUS
INPUT

PARALLEL
BUS
INPUT

COUNTER

REGISTER

INC/DEC

LOGIC

UP/DN

CLK

MODIFIED SCK

UP/DN

C
O
U
N
T
E
R

D
E
C
O
D
E

IF WCR = 00[H] THEN R

= R

IF WCR = FF[H] THEN R

= R

WIPER

(WCR)

BANK_0 Only

(DR0)

(DR1)

(DR2)

(DR3)

X9271

FN8174.1

March 31, 2005

DEVICE DESCRIPTION

Wiper Counter Register (WCR)

The X9271 contains a Wiper Counter Register for the
DCP potentiometer. The Wiper Counter Register can
be envisioned as a 8-bit parallel and serial load
counter with its outputs decoded to select one of 256
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written
directly by the host via the Write Wiper Counter
Register instruction (serial load); it may be written
indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register
instruction (parallel load); it can be modified one step
at a time by the Increment/ Decrement instruction.
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9271 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the R0 value into the WCR. The
DR0 value of Bank 0 is the default value.

Data Registers (DR3DR0)

The potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.

Bits [7:0] are used to store one of the 256 wiper
positions or data (0 ~255).

Status Register (SR)

This 1-bit Status Register is used to store the system
status.

WIP: Write In Progress status bit, read only.

When WIP=1, indicates that high-voltage write cycle

is in progress.

When WIP=0, indicates that no high-voltage write

cycle is in progress

Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).

Table 2. Data Register, DR (8-bit), DR[7:0]: Used to store wiper positions or data (Nonvolatile, NV).

Table 3. Status Register, SR (WIP is 1-bit)

WCR7

WCR6

WCR5

WCR4

WCR3

WCR2

WCR1

WCR0

(MSB)

(LSB)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MSB

LSB

WIP

(LSB)

X9271

FN8174.1

March 31, 2005

DEVICE DESCRIPTION

Instructions

DENTIFICATION

YTE

(ID

AND

The first byte sent to the X9271 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier. The ID[3:0]
bits is the device id for the X9271; this is fixed as
0101[B] (refer to Table 4).

The A1 - A0 bits in the ID byte is the internal slave
address. The physical device address is defined by the
state of the A1 - A0 input pins. The slave address is
externally specified by the user. The X9271 compares
the serial data stream with the address input state; a
successful compare of both address bits is required for
the X9271 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A1 - A0 inputs
can be actively driven by CMOS input signals or tied to
V

or V

NSTRUCTION

YTE

(I[3:0])

The next byte sent to the X9271 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (I[3:0]). The RB and RA bits point to one of the
four Data Registers. P0 is the POT selection; since the
X9271 is single POT, the P0=0. The format is shown in
Table 5.

EGISTER

ANK

ELECTION

(R1, R0, P1, P0)

There are 16 registers organized into four banks. Bank
0 is the default bank of registers. Only Bank 0 registers
can be used for data register to Wiper Counter
Register operations.

Banks 1, 2, and 3 are additional banks of registers (12
total) that can be used for SPI write and read
operations. The data registers in Banks 1, 2, and 3
cannot be used for direct read/write operations
between the Wiper Counter Register.

Register Selection (DR0 to DR3) Table

Register Bank Selection (Bank 0 to Bank 3) Table

Table 4. Identification Byte Format

Register

Selection

Operations

Data Register Read and Write;
Wiper Counter Register
Operations

Bank

Selection

Operations

Data Register Read and Write;
Wiper Counter Register
Operations

Data Register Read and Write
Only

ID3

ID2

ID1

ID0

(MSB)

(LSB)

Device Type

Identifier

Set to 0

for proper operation

Internal

Slave Address

X9271

FN8174.1

March 31, 2005

Table 5. Instruction Byte Format

DEVICE DESCRIPTION

Instructions

Five of the eight instructions are three bytes in length.
These instructions are:

Read Wiper Counter Register read the current

wiper position of the potentiometer;

Write Wiper Counter Register change current

wiper position of the potentiometer;

Read Data Register read the contents of the

selected Data Register;

Write Data Register write a new value to the

selected Data Register.

Read Status - This command returns the contents

of the WIP bit which indicates if the internal write
cycle is in progress.

The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t

WRL

. A transfer

from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t

to complete. The transfer can occur

between one of the four potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between all potentiometers and
one associated register. The Read Status Register
instruction is the only unique format (See Figure 4).

Two instructions require a two-byte sequence to
complete (Figure 2). These instructions transfer data
between the host and the X9271; either between the
host and one of the data registers or directly between
the host and the Wiper Counter Register. These
instructions are:

XFR Data Register to Wiper Counter Register

This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.

XFR Wiper Counter Register to Data Register

This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.

The final command is Increment/Decrement (Figure 5
and 6). It is different from the other commands,
because it's length is indeterminate. Once the
command is issued, the master can clock the selected
wiper up and/or down in one resistor segment steps;
thereby, providing a fine tuning capability to the host.
For each SCK clock pulse (t

HIGH

) while SI is HIGH,

the selected wiper will move one resistor segment
towards the R

terminal. Similarly, for each SCK clock

pulse while SI is LOW, the selected wiper will move
one resistor segment towards the R

terminal.

See Instruction format for more details.

Write in Process (WIP bit)

The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a Write In Process bit
(WIP). The WIP bit is read with a Read Status
command.

(MSB)

(LSB)

Instruction Opcode

Pot Selection (WCR Selection)
Set to P0=0 for potentiometer operations

P1 and P0 are used also for register Bank Selection
for SPI Register Write and Read operations

X9271

FN8174.1

March 31, 2005

Figure 2. Two-Byte Instruction Sequence

Figure 3. Three-Byte Instruction Sequence (Write)

Figure 4. Three-Byte Instruction Sequence (Read)

ID3 ID2 ID1 ID0

RB RA

SCK

Device ID

Internal

Instruction

Opcode

Address

Pot/Bank

Address

These commands only valid when P1 = P0 = 0

A1 A0

RB RA

SCL

D7 D6 D5 D4 D3 D2

D1 D0

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction
Opcode

Address

Pot/Bank
Address

WCR[7:0] valid only when P1 = P0 = 0;

Data Register Bit [7:0] for all values of P1 and P0

A1 A0

I1 I0

RB RA

SCL

D7 D6 D5 D4 D3 D2

D1 D0

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction
Opcode

Address

Pot/Bank

Address

WCR[7:0] valid only when P1 = P0 = 0;

Don't Care

Data Register Bit [7:0] for all values of P1 and P0

X9271

FN8174.1

March 31, 2005

Figure 5. Increment/Decrement Instruction Sequence

Figure 6. Increment/Decrement Timing Limits

Table 6. Instruction Set

Note:

1/0 = data is one or zero

A1 A0

RA RB

SCL

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction

Opcode

Address

Pot/Bank

Address

D
E

Instruction

Instruction Set

Operation

Read Wiper Counter
Register

1/0

Read the contents of the Wiper Counter
Register

Write Wiper Counter
Register

1/0

Write new value to the Wiper Counter
Register

Read Data Register

1/0

Read the contents of the Data Register
pointed to by P1 - P0 and RB - RA

Write Data Register

1/0

Write new value to the Data Register
pointed to by P1 - P0 and RB - RA

XFR Data Register to
Wiper Counter Register

1/0

Transfer the contents of the Data Register
pointed to by RB - RA (Bank 0 only) to the
Wiper Counter Register

XFR Wiper Counter
Register to Data Register

1/0

Transfer the contents of the Wiper Counter
Register to the Register pointed to by RB-RA
(Bank 0 only)

Increment/Decrement
Wiper Counter Register

Enable Increment/decrement of the Wiper
Counter Register

Read Status (WIP bit)

Read the status of the internal write cycle, by
checking the WIP bit.

SCK

INC/DEC CMD ISSUED

tWRID

VOLTAGE OUT

X9271

FN8174.1

March 31, 2005

INSTRUCTION FORMAT

Read Wiper Counter Register (WCR)

Write Wiper Counter Register (WCR)

Read Data Register (DR)

Write Data Register (DR)

Transfer Wiper Counter Register (WCR) to Data Register (DR)

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR/Bank

Addresses

Wiper Position

(Sent by X9271 on SO)

Rising

Edge

0 A1 A0 1

C
R

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR/Bank

Addresses

Data Byte

(Sent by Host on SI)

Rising

Edge

0 A1 A0 1

C
R

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR/Bank

Addresses

Data Byte

(Sent by X9271 on SO)

Rising

Edge

0 A1 A0 1

1 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR/Bank

Addresses

Data Byte

(Sent by Host on SI)

Rising

Edge

HIGH-VOLTAGE

ITE CYCLE

0 0 A1 A0 1 1 0 0 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR/Bank

Addresses

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 A1 A0

1 1

X9271

FN8174.1

March 31, 2005

Transfer Data Register (DR) to Wiper Counter Register (WCR)

Increment/Decrement Wiper Counter Register (WCR)

Read Status Register (SR)

Notes: (1) "A1 ~ A0": stands for the device addresses sent by the master.

(2) WCRx refers to wiper position data in the Wiper Counter Register
(2) "I": stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) "D": stands for the decrement operation, SI held LOW during active SCK phase (high).
(4) "X:": Don't Care.

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR/Bank

Addresses

Rising

Edge

0 0

1 1 0 1 RB

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR/Bank

Addresses

Increment/Decrement

(Sent by Master on SDA)

Rising

Edge

X X

0 I/D I/D

I/D

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR/Bank

Addresses

Data Byte

(Sent by X9271 on SO)

Rising

Edge

WIP

X9271

FN8174.1

March 31, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias..................... -65

C to +135

Storage temperature ......................... -65

C to +150

Voltage on SCK any address input

with respect to V

................................. -1V to +7V

V =

|(V

- V

)|..................................................... 5.5V

Lead temperature (soldering, 10 seconds) ........ 300

(10 seconds)..................................................±6mA

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.

ANALOG CHARACTERISTICS

(Over recommended industrial operating conditions unless otherwise stated.)

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

potentiometer. It is a measure of the error in step size.

(3) MI = RTOT / 255 or (R

- R

) / 255, single pot

(4) During power-up V

> V

, V

, and V

(5) n = 0, 1, 2, ...,255; m =0, 1, 2, ...., 254.

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Units

TOTAL

End to End Resistance

100

T version

TOTAL

End to End Resistance

U version

End to End Resistance
Tolerance

±20

Power Rating

C, each pot

Wiper Current

±3

Wiper Resistance

300

3mA @ V

= 3V

Wiper Resistance

150

3mA @ V

= 5V

TERM

Voltage on any R

or R

= 0V

Noise

-120

dBV

Ref: 1V

Resolution

0.4

Absolute Linearity

(1)

±1

(3)

w(n)(actual) -

w(n)(expected)

(5)

Relative Linearity

(2)

±0.2

(3)

w(n + 1)

- [R

w(n) + MI

]

(5)

Temperature Coefficient of
R

TOTAL

300

ppm/

Ratiometric Temp. Coefficient

ppm/°C

Potentiometer Capacitancies

10/10/25

See Macro model

RECOMMENDED OPERATING CONDITIONS

Temp

Min.

Max.

Commercial

+70

Industrial

-40

+85

Device

Supply Voltage (V

)

(4)

Limits

X9271

10%

X9271-2.7

2.7V to 5.5V

X9271

FN8174.1

March 31, 2005

D.C. OPERATING CHARACTERISTICS

(Over the recommended operating conditions unless otherwise specified.)

ENDURANCE AND DATA RETENTION

CAPACITANCE

POWER-UP TIMING

A.C. TEST CONDITIONS

Notes: (6) This parameter is not 100% tested

(7) t

PUR

and t

PUW

are the delays required from the time the (last) power supply (V

-) is stable until the specific instruction can be issued.

These parameters are periodically sampled and not 100% tested.

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Units

CC1

supply current

(active)

400

SCK

= 2.5 MHz, SO = Open, V

= 6V

Other Inputs = V

CC2

supply current

(nonvolatile write)

SCK

= 2.5MHz, SO = Open, V

= 6V

Other Inputs = V

current (standby)

SCK = SI = V

, Addr. = V

CS = V

= 6V

Input leakage current

= V

to V

Output leakage current

OUT

= V

to V

Input HIGH voltage

x 0.7

+ 1

Input LOW voltage

-1

x 0.3

Output LOW voltage

0.4

= 3mA

Output HIGH voltage

- 0.8

= -1mA, V

+3V

Output HIGH voltage

- 0.4

= -0.4mA, V

+3V

Parameter

Min.

Units

Minimum endurance

100,000

Data changes per bit per register

Data retention

100

years

Symbol

Test

Max.

Units

Test Conditions

IN/OUT

(6)

Input / Output capacitance (SI)

OUT

= 0V

OUT

(6)

Output capacitance (SO)

OUT

= 0V

(6)

Input capacitance (A0, CS, WP, HOLD, and
SCK)

= 0V

Symbol

Parameter

Min.

Max.

Units

(6)

Power-up rate

0.2

V/ms

PUR

(7)

Power-up to initiation of read operation

PUW

(7)

Power-up to initiation of write operation

Input Pulse Levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x 0.5

X9271

FN8174.1

March 31, 2005

EQUIVALENT A.C. LOAD CIRCUIT

AC TIMING

Symbol

Parameter

Min.

Max.

Units

SCK

SSI/SPI clock frequency

2.5

MHz

CYC

SSI/SPI clock cycle time

500

SSI/SPI clock high time

200

SSI/SPI clock low time

200

LEAD

Lead time

250

LAG

Lag time

250

SI, SCK, HOLD and CS input setup time

SI, SCK, HOLD and CS input hold time

SI, SCK, HOLD and CS input rise time

SI, SCK, HOLD and CS input fall time

DIS

SO output disable time

250

SO output valid time

200

SO output hold time

SO output rise time

100

SO output fall time

100

HOLD

HOLD time

400

HSU

HOLD setup time

100

HOLD hold time

100

HOLD low to output in high Z

100

HOLD high to output in low Z

100

Noise suppression time constant at SI, SCK, HOLD and CS inputs

CS deselect time

WPASU

WP, A0 setup time

WPAH

WP, A0 hold time

1462

100pF

SO pin

10pF

TOTAL

25pF

10pF

SPICE Macromodel

2714

1382

100pF

SO pin

1217

X9271

FN8174.1

March 31, 2005

HIGH-VOLTAGE WRITE CYCLE TIMING

XDCP TIMING

SYMBOL TABLE

Symbol

Parameter

Typ.

Max.

Units

High-voltage write cycle time (store instructions)

Symbol

Parameter

Min.

Max.

Units

WRPO

Wiper response time after the third (last) power supply is stable

WRL

Wiper response time after instruction issued (all load instructions)

WAVEFORM

INPUTS

OUTPUTS

Must be
steady

Will be
steady

May change
from Low to
High

Will change
from Low to
High

May change
from High to
Low

Will change
from High to
Low

Don't Care:
Changes
Allowed

Changing:
State Not
Known

N/A

Center Line
is High
Impedance

X9271

FN8174.1

March 31, 2005

APPLICATIONS INFORMATION

Basic Configurations of Electronic Potentiometers

Application Circuits

Three terminal Potentiometer;
Variable voltage divider

Two terminal Variable Resistor;
Variable current

Noninverting Amplifier

Voltage Regulator

Offset Voltage Adjustment

Comparator with Hysterisis

= (1+R

adj

(REG) = 1.25V (1+R

)+I

adj

(REG)

317

= {R

/(R

)} V

(max)

= {R

/(R

)} V

(min)

100k

10k

-12V

+12V

TL072

}

X9271

FN8174.1

March 31, 2005

Application Circuits (continued)

Attenuator

Filter

Inverting Amplifier

Equivalent L-R Circuit

= G V

-1/2

+1/2

= 1 + R

fc = 1/(2

RC)

= R

+ s R

+ R

) C

= R

+ s Leq

+ R

) >> R

Function Generator

= R

= 10k

}

= G V

G = - R

}

frequency

, R

, C

amplitude

, R

X9271

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8174.1

March 31, 2005

ORDERING INFORMATION

Device

Limits

Blank = 5V

10%

-2.7 = 2.7 to 5.5V

Temperature Range
Blank = Commercial = 0

C to +70

I = Industrial = -40

C to +85

Package
V = 14-Lead TSSOP

Potentiometer Organization

Pot

U =

50k

T =

100k

X9271

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9271Uv-2.7

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9271Uv-2.7