FN8175.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9279

Single Supply/Low Power/256-Tap/2-Wire Bus

Single Digitally-Controlled (XDCPTM)

Potentiometer

FEATURES

· 256 Resistor Taps
· 2-Wire Serial Interface for Write, Read, and

Transfer Operations of the Potentiometer

· Wiper Resistance, 100

Typical @ 5V

· 16 Nonvolatile Data Registers for Each

Potentiometer

· Nonvolatile Storage of Multiple Wiper Positions
· Power-on Recall. Loads Saved Wiper Position

on Power-up.

· Standby Current < 5µA Max
· V

: 2.7V to 5.5V Operation

· 50k

, 100k

Versions of End to End Resistance

· Endurance: 100,000 Data Changes per Bit per

Register

· 100 yr. Data Retention
· 14 Ld TSSOP
· Low Power CMOS
· Pb-Free Plus Anneal Available (RoHS Compliant)

DESCRIPTION

The X9279 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.

The digital controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-Wire bus interface. The potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and a four nonvolatile Data Registers that can
be directly written to and read by the user. The
contents of the WCR controls the position of the wiper
on the resistor array though the switches. Powerup
recalls the contents of the default data register (DR0)
to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

FUNCTIONAL DIAGRAM

256-taps

50k

and 100k

POT

2-Wire

Bus

wiper

Interface

Power-on Recall

Wiper Counter

Data Registers

16 Bytes

Bus

Interface

and Control

Address

Data

Status

Write

Read

Transfer

Inc/Dec

Control

Data Sheet

September 27, 2005

FN8175.2

September 27, 2005

DETAILED FUNCTIONAL DIAGRAM

Ordering Information

PART NUMBER

PART MARKING

LIMITS (V)

POTENTIOMETER

ORGANIZATION (k

) TEMP RANGE (°C)

PACKAGE

X9279TV14*

X9279TV

5 ±10%

100

0 to 70

14 Ld TSSOP (4.4mm)

X9279TV14I*

X9279TV I

-40 to 85

14 Ld TSSOP (4.4mm)

X9279UV14*

X9279UV

0 to 70

14 Ld TSSOP (4.4mm)

X9279UV14Z (Note)

X9279UV Z

0 to 70

14 Ld TSSOP (4.4mm) (Pb-free)

X9279UV14I*

X9279UV I

-40 to 85

14 Ld TSSOP (4.4mm)

X9279UV14IZ* (Note)

-40 to 85

14 Ld TSSOP (4.4mm) (Pb-free)

X9279TV14-2.7*

X9279TV F

2.7 to 5.5

100

0 to 70

14 Ld TSSOP (4.4mm)

X9279TV14I-2.7*

X9279TV G

-40 to 85

14 Ld TSSOP (4.4mm)

X9279UV14-2.7*

X9279UV F

0 to 70

14 Ld TSSOP (4.4mm)

X9279UV14Z-2.7 (Note)

0 to 70

14 Ld TSSOP (4.4mm) (Pb-free)

X9279UV14I-2.7*

X9279UV G

-40 to 85

14 Ld TSSOP (4.4mm)

X9279UV14IZ-2.7* (Note)

-40 to 85

14 Ld TSSOP (4.4mm) (Pb-free)

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

DR0 DR1

DR2 DR3

WIPER

COUNTER

(WCR)

DATA

INTERFACE

AND

CONTROL

CIRCUITRY

256-taps

50k

and 100k

Bank 0

Bank 1

Bank 2

Bank 3

12 additional nonvolatile registers

3 Banks of 4 registers x 8-bits

SCL

SDA

Control

Power-on Recall

DR0 DR1

DR2 DR3

DR0 DR1

DR2 DR3

DR0 DR1

DR2 DR3

X9279

FN8175.2

September 27, 2005

CIRCUIT LEVEL APPLICATIONS

· Vary the gain of a voltage amplifier
· Provide programmable dc reference voltages for

comparators and detectors

· Control the volume in audio circuits
· Trim out the offset voltage error in a voltage

amplifier circuit

· Set the output voltage of a voltage regulator
· Trim the resistance in Wheatstone bridge circuits
· Control the gain, characteristic frequency and

Q-factor in filter circuits

· Set the scale factor and zero point in sensor signal

conditioning circuits

· Vary the frequency and duty cycle of timer ICs
· Vary the dc biasing of a pin diode attenuator in RF

circuits

· Provide a control variable (I, V, or R) in feedback

circuits

SYSTEM LEVEL APPLICATIONS

· Adjust the contrast in LCD displays
· Control the power level of LED transmitters in

communication systems

· Set and regulate the DC biasing point in an RF

power amplifier in wireless systems

· Control the gain in audio and home entertainment

systems

· Provide the variable DC bias for tuners in RF

wireless systems

· Set the operating points in temperature control

systems

· Control the operating point for sensors in industrial

systems

· Trim offset and gain errors in artificial intelligent

systems

PIN CONFIGURATION

PIN ASSIGNMENTS

Pin

TSSOP

Symbol

Function

No Connect

Device Address for 2-Wire bus.

No Connect

Device Address for 2-Wire bus.

SCL

Serial Clock for 2-Wire bus.

SDA

Serial Data Input/Output for 2-Wire bus.

System Ground.

Hardware Write Protect

Device Address for 2-Wire bus.

Device Address for 2 wire-bus.

Wiper Terminal of the Potentiometer.

High Terminal of the Potentiometer.

Low Terminal of the Potentiometer.

System Supply Voltage.

1
2
3
4
5
6
7

14
13
12
11
10

SCL

TSSOP

X9279

SDA

X9279

FN8175.2

September 27, 2005

PIN DESCRIPTIONS

Bus Interface Pins

ERIAL

ATA

NPUT

UTPUT

(SDA)

The SDA is a bidirectional serial data input/output pin
for a 2-Wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-Wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of
the serial clock SCL.

It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the
guidelines for calculating typical values on the bus
pull-up resistors graph.

ERIAL

LOCK

(SCL)

This input is used by 2-Wire master to supply 2-Wire
serial clock to the X9279.

EVICE

DDRESS

(A2 - A0)

The Address inputs are used to set the least
significant 3 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the Address input in order to initiate
communication with the X9279. A maximum of 8
devices may occupy the 2-Wire serial bus.

Potentiometer Pins

, R

The R

and R

pins are equivalent to the terminal

connections on a mechanical potentiometer.

The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.

Bias Supply Pins

YSTEM

UPPLY

OLTAGE

)

AND

UPPLY

ROUND

)

The V

pin is the system supply voltage. The V

pin is the system ground.

Other Pins

ONNECT

No connect pins should be left open. This pins are used
for Intersil manufacturing and testing purposes.

ARDWARE

RITE

ROTECT

NPUT

(WP)

The WP pin when LOW prevents nonvolatile writes to
the Data Registers.

X9279

FN8175.2

September 27, 2005

PRINCIPLES OF OPERATION

The X9279 is a integrated microcircuit incorporating a
resistor array and associated registers and counter
and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometers. This section provides detail
description of the following:

Resistor Array Description.
Serial Interface Description.
Instruction and Register Description.

Array Description
The X9279 is comprised of a resistor array (See Figure
1). The array contains, in effect, 255 discrete resistive
segments that are connected in series. The physical
ends of each array are equivalent to the fixed terminals
of a mechanical potentiometer (R

and R

inputs).

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R

) output. Within each individual array only one

switch may be turned on at a time.

These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).

The WCR may be written directly. These Data
Registers can the WCR can be read and written by the
host system.

Power-up and Down Recommendations.
There are no restrictions on the power-up or power-
down conditions of V

and the voltages applied to

the potentiometer pins provided that V

is always

more positive than or equal to V

, V

, and V

, i.e.,

, V

. The V

ramp rate specification is

always in effect.

Figure 1. Detailed Potentiometer Block Diagram

SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

SERIAL

BUS

INPUT

PARALLEL

BUS

INPUT

COUNTER

REGISTER

INC/DEC

LOGIC

UP/DN

CLK

MODIFIED SCK

UP/DN

C
O

U
N

T
E

D
E

C
O

D
E

IF WCR = 00[H] THEN R

= R

WCR = FF[H]

THEN

WIPER

(WCR)

BANK_0 Only

(DR0)

(DR1)

(DR2)

(DR3)

X9279

FN8175.2

September 27, 2005

SERIAL INTERFACE DESCRIPTION

Serial Interface
The X9279 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9279 will be considered a
slave device in all applications.

Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 2.

Start Condition
All commands to the X9279 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9279 continuously monitors

the SDA and SCL lines for the start condition and will
not respond to any command until this condition is
met. See Figure 2.

Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 2.

Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.

The X9279 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9279 will respond with a final acknowledge.
See Figure 2.

Figure 2. Acknowledge Response from Receiver

SCL FROM

MASTER

DATA

OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

X9279

FN8175.2

September 27, 2005

Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9279
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9279 is still busy with the write operation no ACK
will be returned. If the X9279 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.

FLOW 1: ACK Polling Sequence

INSTRUCTION AND REGISTER DESCRIPTION

Device Addressing: Identification Byte ( ID and A)
The first byte sent to the X9279 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier. The ID[3:0]
bits is the device ID for the X9279; this is fixed as
0101[B] (refer to Table 1).

The A[2:0] bits in the ID byte is the internal slave
address. The physical device address is defined by
the state of the A2 - A0 input pins. The slave address
is externally specified by the user. The X9279
compares the serial data stream with the address
input state; a successful compare of both address bits
is required for the X9279 to successfully continue the
command sequence. Only the device which slave
address matches the incoming device address sent by
the master executes the instruction. The A2 - A0
inputs can be actively driven by CMOS input signals or
tied to V

or V

Instruction Byte (I)
The next byte sent to the X9279 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode I [2:0]. The RB and RA bits point to one of the
four Data Registers. P0 is the POT selection; since the
X9279 is single POT, the P0 = 0. The format is shown
in Table 2.

Register Bank Selection (RB, RA, P1, P0)
There are 16 registers organized into four banks. Bank
0 is the default bank of registers. Only Bank 0 registers
can be used for Data Register to Wiper Counter
Register operations.

Banks 1, 2, and 3 are additional banks of registers (12
total) that can be used for 2-Wire write and read
operations. The Data Registers in Banks 1, 2, and 3
cannot be used for direct read/write operations
between the Wiper Counter Register.

Nonvolatile Write

Command Completed

EnterACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

Further

Operation?

Issue

Instruction

Issue STOP

Yes

Proceed

Issue STOP

Proceed

X9279

FN8175.2

September 27, 2005

Register Selection (R0 to R3) Table

Register Bank Selection (Bank 0 to Bank 3) Table

Table 1. Identification Byte Format

Table 2. Instruction Byte Format

RB RA

Register

Selection

Operations

Data Register Read and Write;

Wiper Counter Register

Operations

Data Register Read and Write;

Wiper Counter Register

Operations

Data Register Read and Write;

Wiper Counter Register

Operations

Data Register Read and Write;

Wiper Counter Register

Operations

Bank

Selection

Operations

Data Register Read and Write;

Wiper Counter Register

Operations

Data Register Read and

Write Only

Data Register Read and

Write Only

Data Register Read and

Write Only

ID3

ID2

ID1

ID0

(MSB)

(LSB)

Device Type

Identifier

Set to 0

for proper operation

Internal Slave

Address

(MSB)

(LSB)

Instruction Opcode

Pot Selection (Bank Selection)

Set to P0 = 0 for potentiometer operations

Selection

P1 and P0 are used also for register Bank Selection

for 2-Wire Register Write and Read operations

Register Selection

DR0

DR1

DR2

DR3

X9279

FN8175.2

September 27, 2005

Table 3. Instruction Set

Note:

1/0 = data is one or zero

DEVICE DESCRIPTION

Wiper Counter Register (WCR)
The X9279 contains contains a Wiper Counter
Register, for the DCP potentiometer. The Wiper
Counter Register can be envisioned as a 8-bit parallel
and serial load counter with its outputs decoded to
select one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (See Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9279 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR. The
DR0 value of Bank 0 is the default value.

Data Registers (DR)
The potentiometer has four 8-bit nonvolatile Data
Registers (DR3-DR0). These can be read or written
directly by the host. Data can also be transferred
between any of the four Data Registers and the
associated Wiper Counter Register. All operations
changing data in one of the Data Registers is a
nonvolatile operation and will take a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.

Bit [7:0] are used to store one of the 256 wiper
positions (0~255).

Instruction

Instruction Set

Operation

I0 RB RA P

Read Wiper Counter

Read the contents of the Wiper Counter

Write Wiper Counter

Write new value to the Wiper Counter

Read Data Register

1/0 1/0

1/0

1/0 Read the contents of the Data Register pointed to

by P1 - P0 and RB - RA

Write Data Register

1/0 1/0

1/0

1/0 Write new value to the Data Register

pointed to by P1 - P0 and RB - RA

XFR Data Register to

Wiper Counter Register

1/0 1/0

Transfer the contents of the Data Register

pointed to by RB - RA (Bank 0 only) to the Wiper

Counter Register

XFR Wiper Counter

1/0 1/0

Transfer the contents of the Wiper Counter Register

to the Register pointed to by RB-RA (Bank 0 only)

Increment/Decrement

Wiper Counter Register

Enable Increment/decrement of the Wiper Counter

X9279

FN8175.2

September 27, 2005

Table 4. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).

Table 5. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).

Instructions
Four of the seven instructions are three bytes in
length. These instructions are:

Read Wiper Counter Register read the current

wiper position of the potentiometer,

Write Wiper Counter Register change current

wiper position of the potentiometer,

Read Data Register read the contents of the

selected Data Register;

Write Data Register write a new value to the

selected Data Register.

The basic sequence of the three byte instructions is
illustrated in Figure 4. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t

WRL

. A transfer

from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t

to complete. The transfer can occur

between the potentiometer and one of its four
associated registers (Bank 0).

Two instructions require a two-byte sequence to
complete. These instructions transfer data between the
host and the X9279; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:

XFR Data Register to Wiper Counter Register

This transfers the contents of one specified Data
Register to the Wiper Counter Register.

XFR Wiper Counter Register to Data Register

This transfers the contents of the Wiper Counter
Register to the specified Data Register.

The final command is Increment/Decrement (Figure 5
and 6). The Increment/Decrement command is
different from the other commands. Once the
command is issued and the X9279 has responded
with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps;
thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (t

HIGH

) while SDA is HIGH,

the selected wiper will move one resistor segment
towards the R

terminal. Similarly, for each SCL clock

pulse while SDA is LOW, the selected wiper will move
one resistor segment towards the R

terminal.

See Instruction format for more details.

Figure 3. Two-Byte Instruction Sequence

WCR7

WCR6

WCR5

WCR4

WCR3

WCR2

WCR1

WCR0

(MSB)

(LSB)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MSB

LSB

These commands only valid when P1 = P0 = 0

0 A2

I2 I1 I0

RB RA P1

SCL

SDA

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction

Opcode

Address

Pot/Bank
Address

X9279

FN8175.2

September 27, 2005

Figure 4. Three-Byte Instruction Sequence

Figure 5. Increment/Decrement Instruction Squence

Figure 6. Increment/Decrement Timing Limits

I3 I2

I1 I0 RB RA

ID3 ID2 ID1 ID0

Device ID

External

Instruction

Opcode

Address

Pot/Bank

Address

WCR[7:0] valid only when P1=P0=0;

Data Register D[7:0] for all values of P1 and P0

A2 A1 A0

P1 P0 A

SCL

SDA

D7 D6 D5 D4 D3 D2 D1 D0

I1 I0

ID3 ID2 ID1 ID0

Device ID

External

Instruction

Opcode

Address

Pot/Bank

Address

A1 A0

RA P1 P0 A

SCL

SDA

SCL

SDA

INC/DEC

CMD

Issued

Voltage Out

WRID

X9279

FN8175.2

September 27, 2005

INSTRUCTION FORMAT

Read Wiper Counter Register (WCR)

Write Wiper Counter Register (WCR)

Read Data Register (DR)

Write Data Register (DR)

Transfer Wiper Counter Register (WCR) to Data Register (DR)

A
R

Device Type

Identifier

Device

Addresses

S
A
C
K

Instruction

Opcode

DR/Bank

Addresses S

A
C
K

Wiper Position

(Sent by X9279 on SDA) M

1 0 A 2 A 1 A 0

1 0 0 1 0 0 0 0

A
R

Device Type

Identifier

Device

Addresses

S
A
C
K

Instruction

Opcode

DR/Bank

Addresses S

A
C
K

Wiper Position

(Sent by Master on SDA) S

1 0 A 2 A 1 A 0

1 0 1 0 0 0 0 0

A
R

Device Type

Identifier

Device

Addresses

S
A
C
K

Instruction

Opcode

DR/Bank

Addresses

S
A

Wiper Position

(Sent by X9279 on SDA) M

S
T

1 0 A 2 A 1 A 0

1 0 1 1 RB RA P1 P0

A
R

Device Type

Identifier

Device

Addresses

S
A
C
K

Instruction

Opcode

DR/Bank

Addresses

S
A

Wiper Position

(Sent by Master on SDA) S

A
C
K

S
T

HIGH-VOLTAGE

ITE CYC

L
E

1 0 A 2 A 1 A 0

1 1 0 0 RB RA P1 P0

S
T
A
R
T

Device Type

Identifier

Device

Addresses

S
A
C
K

Instruction

Opcode

DR/Bank

Addresses

S
A
C
K

S
T

HIGH-VOLTAGE

WRITE CYCLE

1 0 A 2 A 1 A 0

1 1 1 0 RB RA 0 0

X9279

FN8175.2

September 27, 2005

Transfer Data Register (DR) to Wiper Counter Register (WCR)

Increment/Decrement Wiper Counter Register (WCR)

Notes: (1) "MACK"/"SACK": stands for the acknowledge sent by the master/slave.

(2) "A3 ~ A0": stands for the device addresses sent by the master.
(3) "X": indicates that it is a "0" for testing purpose but physically it is a "don't care" condition.
(4) "I": stands for the increment operation, SDA held high during active SCL phase (high).
(5) "D": stands for the decrement operation, SDA held low during active SCL phase (high).

A
R

Device Type

Identifier

Device

Addresses

S
A
C
K

Instruction

Opcode

DR/Bank

Addresses

S
A
C
K

0 1 0 1 0 A 2 A 1 A 0

1 1 0 1 RB RA 0 0

S
T
A

Device Type

Identifier

Device

Addresses

S
A

Instruction

Opcode

DR/Bank

Addresses

S
A
C
K

Increment/Decrement

(Sent by Master on SDA)

S
T

0 1 0 1 0 A 2 A 1 A 0

0 0 1 0 0 0 0 0

I/D I/D .

. I/D I/D

X9279

FN8175.2

September 27, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65

C to +135

Storage temperature ......................... -65

C to +150

Voltage on SCL, SDA any address input

with respect to V

................................. -1V to +7V

V = | (V

- V

) |................................................... 5.5V

Lead temperature (soldering, 10s) .................... 300

(10s) ..............................................................±6mA

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.

ANALOG CHARACTERISTICS

(Over recommended industrial (2.7V) operating conditions unless otherwise stated.)

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

potentiometer. It is a measure of the error in step size.

(3) MI = RTOT / 255 or (R

- R

) / 255, single pot

(4) During power-up V

> V

, V

, and V

(5) n = 0, 1, 2, ....,255; m =0, 1, 2, ...., 254.

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Units

TOTAL

End to End Resistance

100

T version

TOTAL

End to End Resistance

U version

End to End Resistance Tolerance

±20

Power Rating

C, each pot

Wiper Current

±3

Wiper Resistance

300

3mA @ V

= 3V

Wiper Resistance

150

3mA @ V

= 5V

TERM

Voltage on any R

or R

= 0V

Noise

-120

dBV

Hz Ref: 1V

Resolution

0.4

Absolute Linearity

(1)

±1

(3)

w(n)(actual)

- R

w(n)(expected)

(5)

Relative Linearity

(2)

±0.2

(3)

w(n + 1)

- [R

w(n) + MI

]

(5)

Temperature Coefficient of

TOTAL

300

ppm/

Ratiometric Temp. Coefficient

ppm/°C

Potentiometer Capacitances

10/10/25

See Macro model

RECOMMENDED OPERATING CONDITIONS

Temp

Min.

Max.

Commercial

+70

Industrial

-40

+85

Device

Supply Voltage (V

)

(4)

Limits

X9279

10%

X9279-2.7

2.7V to 5.5V

X9279

FN8175.2

September 27, 2005

D.C. OPERATING CHARACTERISTICS

(Over the recommended operating conditions unless otherwise specified.)

ENDURANCE AND DATA RETENTION

CAPACITANCE

POWER-UP TIMING

A.C. TEST CONDITIONS

Notes: (6) This parameter is not 100% tested

(7) t

PUR

and t

PUW

are the delays required from the time the (last) power supply (V

-) is stable until the specific instruction can be issued.

These parameters are periodically sampled and not 100% tested.

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Units

CC1

supply current

(active)

SCL

= 400kHz; V

= +6V;

SDA = Open; (for 2-Wire, Active, Read

and Volatile Write States only)

CC2

supply current

(nonvolatile write)

SCL

= 400kHz; V

= +6V;

SDA = Open; (for 2-Wire, Active,

Nonvolatile Write State only)

current (standby)

= +6V; V

= V

or V

;

SDA = V

; (for 2-Wire, Standby

State only)

Input leakage current

= V

to V

Output leakage current

OUT

= V

to V

Input HIGH voltage

x 0.7

+ 1

Input LOW voltage

-1

x 0.3

Output LOW voltage

0.4

= 3mA

Output HIGH voltage

Parameter

Min.

Units

Minimum endurance

100,000

Data changes per bit per register

Data retention

100

years

Symbol

Test

Max.

Units

Test Conditions

IN/OUT

(6)

Input / Output capacitance (SDA)

OUT

= 0V

(6)

Input capacitance (

SCL, WP, A2, A1 and A0

)

= 0V

Symbol

Parameter

Min.

Max.

Units

(6)

Power-up rate

0.2

V/ms

PUR

(7)

Power-up to initiation of read operation

PUW

(7)

Power-up to initiation of write operation

Input Pulse Levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x 0.5

X9279

FN8175.2

September 27, 2005

EQUIVALENT A.C. LOAD CIRCUIT

AC TIMING

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol

Parameter

Min.

Max.

Units

SCL

Clock Frequency

400

kHz

CYC

Clock Cycle Time

2500

HIGH

Clock High Time

600

LOW

Clock Low Time

1300

SU:STA

Start Setup Time

600

HD:STA

Start Hold Time

600

SU:STO

Stop Setup Time

600

SU:DAT

SDA Data Input Setup Time

100

HD:DAT

SDA Data Input Hold Time

SCL and SDA Rise Time

300

SCL and SDA Fall Time

300

SCL Low to SDA Data Output Valid Time

0.9

SDA Data Output Hold Time

Noise Suppression Time Constant at SCL and SDA inputs

BUF

Bus Free Time (Prior to Any Transmission)

1200

SU:WPA

A0, A1 Setup Time

HD:WPA

A0, A1 Hold Time

Symbol

Parameter

Typ.

Max.

Units

High-voltage write cycle time (store instructions)

1533

100pF

SDA pin

10pF

TOTAL

25pF

10pF

SPICE Macromodel

867

100pF

SDA pin

X9279

FN8175.2

September 27, 2005

XDCP TIMING

SYMBOL TABLE

Symbol

Parameter

Min.

Max.

Units

WRPO

Wiper response time after the third (last) power supply is stable

WRL

Wiper response time after instruction issued (all load instructions)

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from Low to

High

Will change

from Low to

High

May change

from High to

Low

Will change

from High to

Low

Don't Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

X9279

FN8175.2

September 27, 2005

APPLICATIONS INFORMATION

Basic Configurations of Electronic Potentiometers

Application Circuits

Three terminal Potentiometer;

Variable voltage divider

Two terminal Variable Resistor;

Variable current

Noninverting Amplifier

Voltage Regulator

Offset Voltage Adjustment

Comparator with Hysterisis

= (1+R

adj

(REG) = 1.25V (1+R

)+I

adj

(REG)

317

= {R

/(R

)} V

(max)

= {R

/(R

)} V

(min)

100k

10k

-12V

+12V

TL072

}

X9279

FN8175.2

September 27, 2005

Application Circuits (continued)

Attenuator

Filter

Inverting Amplifier

Equivalent L-R Circuit

= G V

-1/2

+1/2

= 1 + R

fc = 1/(2

RC)

= R

+ s R

+ R

) C

= R

+ s Leq

+ R

) >> R

Function Generator

= R

= 10k

}

= G V

G = - R

}

frequency

, R

, C

amplitude

, R

X9279

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8175.2

September 27, 2005

PACKAGING INFORMATION

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V

See Detail "A"

.031 (.80)

.041 (1.05)

.169 (4.3)
.177 (4.5).252 (6.4) BSC

.025 (.65) BSC

.193 (4.9)
.200 (5.1)

.002 (.05)

.006 (.15)

.047 (1.20)

.0075 (.19)

.0118 (.30)

- 8

.010 (.25)

.019 (.50)
.029 (.75)

Gage Plane

Seating Plane

DetailA (20X)

X9279

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9279TV14I