ChipFind - документация

Электронный компонент: X9317TV8IZ

Скачать:  PDF   ZIP
1
FN8183.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas, Inc. Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9317
Low Noise, Low Power, 100 Taps
Digitally Controlled Potentiometer
(XDCPTM)
The Intersil X9317 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a 3-wire interface.
The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS, U/D, and INC inputs.
The position of the wiper can be stored in nonvolatile
memory and then be recalled upon a subsequent power-up
operation.
The device can be used as a three-terminal potentiometer
for voltage control or as a two-terminal variable resistor for
current control in a wide variety of applications.
Features
Solid-State Potentiometer
3-Wire Serial Up/Down Interface
100 Wiper Tap Points
- Wiper position stored in nonvolatile memory and
recalled on power-up
99 Resistive Elements
- Temperature compensated
- End to end resistance range 20%
Low Power CMOS
- V
CC
= 2.7V to 5.5V, and 5V 10%
- Standby current < 1A
High Reliability
- Endurance, 100,000 data changes per bit
- Register data retention, 100 years
R
TOTAL
Values = 1k
, 10k, 50k, 100k
Packages
- 8 Ld SOIC, DIP, TSSOP, and MSOP
Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
LCD Bias Control
DC Bias Adjustment
Gain and Offset Trim
Laser Diode Bias Control
Voltage Regulator Output Control
Pinouts
X9317
(8 LD TSSOP)
TOP VIEW
X9317
(8 LD DIP, 8 LD SOIC, 8 LD MSOP)
TOP VIEW
INC
R
L
/V
L
CS
V
CC
1
2
3
4
8
7
6
5
X9317
U/D
R
W
/V
W
V
SS
R
H
/V
H
R
H
V
CC
INC
U/D
1
2
3
4
8
7
6
5
X9317
V
SS
CS
R
L
R
W
Data Sheet
September 9, 2005
2
FN8183.1
September 9, 2005
Ordering Information
PART NUMBER
PART MARKING
V
CC
LIMITS (V)
R
TOTAL
(k
)
TEMPERATURE
RANGE (C)
PACKAGE
X9317ZM8*
5 10%
1
0 to 70
8 Ld MSOP
X9317ZM8Z* (Note)
DDA
0 to 70
8 Ld MSOP (Pb-free)
X9317ZM8I*
AFI
-40 to 85
8 Ld MSOP
X9317ZM8IZ* (Note)
DCY
-40 to 85
8 Ld MSOP (Pb-free)
X9317ZP
X9317ZP
0 to 70
8 Ld PDIP
X9317ZS8*
X9317Z
0 to 70
8 Ld SOIC
X9317ZS8Z* (Note)
X9317Z Z
0 to 70
8 Ld SOIC (Pb-free)
X9317ZS8I*
X9317Z I
-40 to 85
8 Ld SOIC
X9317ZS8IZ* (Note)
X9317Z Z I
-40 to 85
8 Ld SOIC (Pb-free)
X9317ZV8*
9317Z
0 to 70
8 Ld TSSOP
X9317ZV8Z* (Note)
9317Z Z
0 to 70
8 Ld TSSOP (Pb-free)
X9317ZV8I*
317ZI
-40 to 85
8 Ld TSSOP
X9317ZV8IZ* (Note)
9317ZI Z
-40 to 85
8 Ld TSSOP (Pb-free)
X9317WM8*
ABF
10
0 to 70
8 Ld MSOP
X9317WM8Z* (Note)
DCW
0 to 70
8 Ld MSOP (Pb-free)
X9317WM8I*
ADS
-40 to 85
8 Ld MSOP
X9317WM8IZ* (Note)
DCT
-40 to 85
8 Ld MSOP (Pb-free)
X9317WP
X9317WP
0 to 70
8 Ld PDIP
X9317WPI
X9317WP I
-40 to 85
8 Ld PDIP
X9317WS8*
X9317W
0 to 70
8 Ld SOIC
X9317WS8Z* (Note)
X9317W Z
0 to 70
8 Ld SOIC (Pb-free)
X9317WS8I*
X9317W I
-40 to 85
8 Ld SOIC
X9317WS8IZ* (Note)
X9317W Z I
-40 to 85
8 Ld SOIC (Pb-free)
X9317WV8*
9317W
0 to 70
8 Ld TSSOP
X9317WV8Z* (Note)
9317W Z
0 to 70
8 Ld TSSOP (Pb-free)
X9317WV8I*
317WI
-40 to 85
8 Ld TSSOP
X9317WV8IZ* (Note)
9317WI Z
-40 to 85
8 Ld TSSOP (Pb-free)
X9317UM8*
AEC
50
0 to 70
8 Ld MSOP
X9317UM8Z* (Note)
DCS
0 to 70
8 Ld MSOP (Pb-free)
X9317UM8I*
AFE
-40 to 85
8 Ld MSOP
X9317UM8IZ* (Note)
DCR
-40 to 85
8 Ld MSOP (Pb-free)
X9317UP
X9317UP
0 to 70
8 Ld PDIP
X9317UPI
X9317UP I
-40 to 85
8 Ld PDIP
X9317US
0 to 70
8 Ld SOIC
X9317US8*
X9317U
0 to 70
8 Ld SOIC
X9317US8Z* (Note)
X9317U Z
0 to 70
8 Ld SOIC (Pb-free)
X9317US8I*
X9317U I
-40 to 85
8 Ld SOIC
X9317US8IZ* (Note)
X9317U Z I
-40 to 85
8 Ld SOIC (Pb-free)
X9317UV8*
9317U
0 to 70
8 Ld TSSOP
X9317UV8Z* (Note)
9317U Z
0 to 70
8 Ld TSSOP (Pb-free)
X9317UV8I*
317UI
-40 to 85
8 Ld TSSOP
X9317UV8IZ* (Note)
9317UI Z
-40 to 85
8 Ld TSSOP (Pb-free)
X9317
3
FN8183.1
September 9, 2005
X9317TM8*
AGD
100
0 to 70
8 Ld MSOP
X9317TM8Z* (Note)
DCN
0 to 70
8 Ld MSOP (Pb-free)
X9317TM8I*
AGF
-40 to 85
8 Ld MSOP
X9317TM8IZ* (Note)
DCL
-40 to 85
8 Ld MSOP (Pb-free)
X9317TP
0 to 70
8 Ld PDIP
X9317TPI
X9317TP I
-40 to 85
8 Ld PDIP
X9317TS8
X9317T
0 to 70
8 Ld SOIC
X9317TS8Z (Note)
X9317T Z
0 to 70
8 Ld SOIC (Pb-free)
X9317TS8I
X9317T I
-40 to 85
8 Ld SOIC
X9317TS8IZ (Note)
X9317T Z I
-40 to 85
8 Ld SOIC (Pb-free)
X9317TV8*
0 to 70
8 Ld TSSOP
X9317TV8Z* (Note)
9317T Z
0 to 70
8 Ld TSSOP (Pb-free)
X9317TV8I*
-40 to 85
8 Ld TSSOP
X9317TV8IZ* (Note)
9317TI Z
-40 to 85
8 Ld TSSOP (Pb-free)
X9317ZM8-2.7*
AFH
2.7-5.5
1
0 to 70
8 Ld MSOP
X9317ZM8Z-2.7* (Note)
AOA
0 to 70
8 Ld MSOP (Pb-free)
X9317ZM8I-2.7*
AFJ
-40 to 85
8 Ld MSOP
X9317ZM8IZ-2.7* (Note)
DCZ
-40 to 85
8 Ld MSOP (Pb-free)
X9317ZS8-2.7*
X9317Z F
0 to 70
8 Ld SOIC
X9317ZS8Z-2.7* (Note)
X9317Z Z F
0 to 70
8 Ld SOIC (Pb-free)
X9317ZS8I-2.7*
X9317Z G
-40 to 85
8 Ld SOIC
X9317ZS8IZ-2.7* (Note)
X9317Z Z G
-40 to 85
8 Ld SOIC (Pb-free)
X9317ZV8-2.7*
317ZF
0 to 70
8 Ld TSSOP
X9317ZV8Z-2.7* (Note)
9317ZF Z
0 to 70
8 Ld TSSOP (Pb-free)
X9317ZV8I-2.7*
317ZG
-40 to 85
8 Ld TSSOP
X9317ZV8IZ-2.7* (Note)
317ZG Z
-40 to 85
8 Ld TSSOP (Pb-free)
X9317WM8-2.7*
ACZ
10
0 to 70
8 Ld MSOP
X9317WM8Z-2.7* (Note)
DCX
0 to 70
8 Ld MSOP (Pb-free)
X9317WM8I-2.7*
ADT
-40 to 85
8 Ld MSOP
X9317WP-2.7
X9317WP F
0 to 70
8 Ld PDIP
X9317WPI-2.7
X9317WP G
-40 to 85
8 Ld PDIP
X9317WS8-2.7*
X9317W F
0 to 70
8 Ld SOIC
X9317WS8Z-2.7* (Note)
X9317W Z F
0 to 70
8 Ld SOIC (Pb-free)
X9317WS8I-2.7*
X9317W G
-40 to 85
8 Ld SOIC
X9317WS8IZ-2.7*
(Note)
X9317W Z G
-40 to 85
8 Ld SOIC (Pb-free)
X9317WV8-2.7*
317WF
0 to 70
8 Ld TSSOP
X9317WV8Z-2.7* (Note)
9317WF Z
0 to 70
8 Ld TSSOP (Pb-free)
X9317WV8I-2.7*
317WG
-40 to 85
8 Ld TSSOP
X9317WV8IZ-2.7* (Note)
AKZ
-40 to 85
8 Ld TSSOP (Pb-free)
Ordering Information
(Continued)
PART NUMBER
PART MARKING
V
CC
LIMITS (V)
R
TOTAL
(k
)
TEMPERATURE
RANGE (C)
PACKAGE
X9317
4
FN8183.1
September 9, 2005
X9317UM8-2.7*
AED
50
0 to 70
8 Ld MSOP
X9317UM8Z-2.7* (Note)
AOB
0 to 70
8 Ld MSOP (Pb-free)
X9317UM8I-2.7*
AFF
-40 to 85
8 Ld MSOP
X9317UM8IZ-2.7* (Note)
AOH
-40 to 85
8 Ld MSOP (Pb-free)
X9317UP-2.7
X9317UP F
0 to 70
8 Ld PDIP
X9317UPI-2.7
X9317UP G
-40 to 85
8 Ld PDIP
X9317US8-2.7*
X9317U F
0 to 70
8 Ld SOIC
X9317US8Z-2.7* (Note)
X9317U Z F
0 to 70
8 Ld SOIC (Pb-free)
X9317US8I-2.7*
X9317U G
-40 to 85
8 Ld SOIC
X9317US8IZ-2.7* (Note)
X9317U Z G
-40 to 85
8 Ld SOIC (Pb-free)
X9317UV8-2.7*
9317UF
0 to 70
8 Ld TSSOP
X9317UV8Z-2.7* (Note)
9317UF Z
0 to 70
8 Ld TSSOP (Pb-free)
X9317UV8I-2.7*
9317UG
-40 to 85
8 Ld TSSOP
X9317UV8IZ-2.7* (Note)
9317UG Z
-40 to 85
8 Ld TSSOP (Pb-free)
X9317TM8-2.7*
AGE
100
0 to 70
8 Ld MSOP
X9317TM8Z-2.7* (Note)
DCP
0 to 70
8 Ld MSOP (Pb-free)
X9317TM8I-2.7*
AGG
-40 to 85
8 Ld MSOP
X9317TM8IZ-2.7* (Note)
DCM
-40 to 85
8 Ld MSOP (Pb-free)
X9317TP-2.7
0 to 70
8 Ld PDIP
X9317TPI-2.7
X9317TP G
-40 to 85
8 Ld PDIP
X9317TS8-2.7*
0 to 70
8 Ld SOIC
X9317TS8Z-2.7* (Note)
X9317T Z F
0 to 70
8 Ld SOIC (Pb-free)
X9317TS8I-2.7*
X9317T G
-40 to 85
8 Ld SOIC
X9317TS8IZ-2.7* (Note)
X9317T Z G
-40 to 85
8 Ld SOIC (Pb-free)
X9317TV8-2.7*
0 to 70
8 Ld TSSOP
X9317TV8Z-2.7* (Note)
9317TF Z
0 to 70
8 Ld TSSOP (Pb-free)
X9317TV8I-2.7*
317TG
-40 to 85
8 Ld TSSOP
X9317TV8IZ-2.7* (Note)
9317TG Z
-40 to 85
8 Ld TSSOP (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add "T1" suffix for tape and reel.
Ordering Information
(Continued)
PART NUMBER
PART MARKING
V
CC
LIMITS (V)
R
TOTAL
(k
)
TEMPERATURE
RANGE (C)
PACKAGE
X9317
5
FN8183.1
September 9, 2005
Block Diagram
Up/Down
Counter
7-Bit
Nonvolatile
Memory
Store and
Recall
Control
Circuitry
One
of
One
Decoder
Resistor
Array
R
H
U/D
INC
CS
Wiper
Switches
Hundred
V
CC
V
SS
R
L
R
W
Control
and
Memory
Up/Down
(U/D)
Increment
(INC)
Device Select
(CS)
V
CC
(Supply Voltage)
V
SS
(Ground)
R
H
R
W
R
L
General
Detailed
0
1
2
96
97
98
99
Pin Descriptions
DIP/SOIC
SYMBOL
BRIEF DESCRIPTION
1
INC
Increment. Toggling INC while CS is low moves the wiper either up or down.
2
U/D
Up/Down. The U/D input controls the direction of the wiper movement.
3
R
H
The high terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.
4
V
SS
Ground.
5
R
W
The wiper terminal is equivalent to the movable terminal of a mechanical potentiometer.
6
R
L
The low terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.
7
CS
Chip Select. The device is selected when the CS input is LOW, and de-selected when CS is high.
8
V
CC
Supply Voltage.
X9317