X9401

Low Noise/Low Power/SPI Bus

Quad, 64 Tap, Digitally Controlled

Potentiometer (XDCPTM)

FEATURES

· Quad4 separate pots, 64 taps/pot
· Nonvolatile storage of wiper position
· Four Nonvolatile Data Registers for Each Pot
· 16-bytes of EEPROM memory
· SPI serial interface
· R

Total

= 10k

· Wiper resistance = 150

typical

· Standby current < 1µA (total package)
· Operating current < 400µA max.
· V

= 2.7V to 5V

· Packages24 Ld TSSOP and SOIC
· 100 year data retention
· Pb-free plus anneal available (RoHS compliant)

DESCRIPTION

The X9401 integrates 4 digitally controlled potentiome-
ters (XDCP) on a monolithic CMOS integrated
microcircuit.

The digitally controlled potentiometer is implemented
using 64 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. Each potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4 nonvola-
tile Data Registers (DR0:DR3) that can be directly writ-
ten to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
through the switches. Power-up recalls the contents of
DR0 to the WCR.

The XDCP can be used as a three-terminal potentiom-
eter or as a two-terminal variable resistor in a wide
variety of applications including control, parameter
adjustments, and signal processing.

BLOCK DIAGRAM

Interface

and

Control

Circuitry

SCK

A0
A1

R0 R1

R2 R3

Wiper

Counter

(WCR)

Resistor

Array
Pot 1

R0 R1

R2 R3

Wiper

Counter

(WCR)

Data

R0 R1

R2 R3

Resistor

Array

R0 R1

R2 R3

Resistor

Array

Wiper

Counter

(WCR)

Wiper

Counter

(WCR)

Pot 3

Pot 2

HOLD

Pot 0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

PRELIMINARY

Data Sheet

FN8190.2

September 23, 2005

FN8190.2

September 23, 2005

Ordering Information

PART NUMBER

PART

MARKING

LIMITS (V)

POTENTIOMETER

ORGANIZATION (k

) TEMP RANGE (°C)

PACKAGE

X9401WS24*

X9401WS

5 ±10%

0 to 70

24 Ld SOIC (300 mil)

X9401WS24Z* (Note)

X9401WS Z

0 to 70

24 Ld SOIC (300 mil) (Pb-free)

X9401WS24I*

X9401WS I

-40 to 85

24 Ld SOIC (300 mil)

X9401WS24IZ* (Note)

X9401WS Z I

-40 to 85

24 Ld SOIC (300 mil) (Pb-free)

X9401WV24*

X9401WV

0 to 70

24 Ld TSSOP (4.4mm)

X9401WV24Z* (Note)

X9401WV Z

0 to 70

24 Ld TSSOP (4.4mm) (Pb-free)

X9401WV24I*

X9401WV I

-40 to 85

24 Ld TSSOP (4.4mm)

X9401WV24IZ* (Note)

X9401WV Z I

-40 to 85

24 Ld TSSOP (4.4mm) (Pb-free)

X9401WS24-2.7*

X9401WS F

2.7 to 5.5

0 to 70

24 Ld SOIC (300 mil)

X9401WS24Z-2.7* (Note)

X9401WS Z F

0 to 70

24 Ld SOIC (300 mil) (Pb-free)

X9401WS24I-2.7*

X9401WS G

-40 to 85

24 Ld SOIC (300 mil)

X9401WS24IZ-2.7* (Note)

X9401WS Z G

-40 to 85

24 Ld SOIC (300 mil) (Pb-free)

X9401WV24-2.7*

X9401WV F

0 to 70

24 Ld TSSOP (4.4mm)

X9401WV24Z-2.7* (Note)

X9401WV Z F

0 to 70

24 Ld TSSOP (4.4mm) (Pb-free)

X9401WV24I-2.7*

X9401WV G

-40 to 85

24 Ld TSSOP (4.4mm)

X9401WV24IZ-2.7* (Note)

X9401WV Z G

-40 to 85

24 Ld TSSOP (4.4mm) (Pb-free)

X9401YS24I-2.7

X9401YS G

2.5

-40 to 85

24 Ld SOIC (300 mil)

X9401YV24I-2.7

X9401YV G

-40 to 85

24 Ld TSSOP (4.4mm)

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

X9401

FN8190.2

September 23, 2005

PIN DESCRIPTIONS

Host Interface Pins

Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.

Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.

Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9401.

Chip Select (CS)
When CS is HIGH, the X9401 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9401, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.

Hold (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence
is underway, HOLD may be used to pause the serial
communication with the controller without resetting the
serial sequence. To pause, HOLD must be brought LOW
while SCK is LOW. To resume communication, HOLD is
brought HIGH, again while SCK is LOW. If the pause
feature is not used, HOLD should be held HIGH at all
times.

Device Address (A

- A

)

The address inputs are used to set the least significant 2
bits of the 8-bit slave address. A match in the slave address
serial data stream must be made with the address
input in order to initiate communication with the
X9401. A maximum of 4 devices may occupy the SPI
serial bus.

Potentiometer Pins

- V

), V

- V

), R

- R

)

The V

and V

inputs are equivalent to the

terminal connections on either end of a mechanical poten-

tiometer.

- V

), R

- R

)

The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.

Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Wiper Counter Registers.

PIN CONFIGURATION

2
3

4
5

6
7

8
9

23
22

21
20

19
18

17
16

HOLD
SCK

SOIC

X9401

2
3

4
5

6
7

8
9

23
22

21
20

19
18

17
16

CS
V

NC
V

TSSOP

X9401

HOLD

SCK

X9401

FN8190.2

September 23, 2005

PIN NAMES

DEVICE DESCRIPTION

The X9401 is a highly integrated microcircuit incorpo-
rating four resistor arrays and their associated regis-
ters and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.

Serial Interface
The X9401 supports the SPI interface hardware con-
ventions. The device is accessed via the SI input with
data clocked in on the rising SCK. CS must be LOW
and the HOLD and WP pins must be HIGH during the
entire operation.

The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.

Array Description
The X9401 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V

and V

inputs).

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V

) output. Within each individual array only one

switch may be turned on at a time.

These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded
to select, and enable, one of sixty-four switches.

Wiper Counter Register (WCR)
The X9401 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The WCR is equiv-
alent to a serial-in, parallel-out register/counter with its
outputs decoded to select one of sixty-four switches
along its resistor array. The contents of the WCR can
be altered in four ways: it may be written directly by
the host via the Write Wiper Counter Register instruc-
tion (serial load); it may be written indirectly by trans-
ferring the contents of one of four associated data
registers via the XFR Data Register or Global XFR
Data Register instructions (parallel load); it can be
modified one step at a time by the Increment/Decre-
ment instruction. Finally, it is loaded with the contents
of its data register zero (R0) upon power-up.

The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9401 is powered-
down. Although the register is automatically loaded
with the value in R

upon power-up, this may be differ-

ent from the value present at power-down. The wiper
position must be stored in R

to insure restoring the

wiper position after power-up.

Data Registers
Each potentiometer has four 6-bit nonvolatile data reg-
isters. These can be read or written directly by the
host. Data can also be transferred between any of the
four data registers and the associated Wiper Counter
Register. All operations changing data in one of the
data registers is a nonvolatile operation and will take a
maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the data registers can
be used as memory locations for system parameters
or user preference data.

Data Register Detail

Symbol

Description

SCK

Serial Clock

SI, SO

Serial Data

- A

Device Address

- V

Potentiometers (terminal

equivalent)

- V

Potentiometers (wiper

equivalent)

Hardware Write Protection

System Supply Voltage

System Ground

No Connection

(MSB)

(LSB)

X9401

FN8190.2

September 23, 2005

Detailed Potentiometer Block Diagram

Write in Process
The contents of the Data Registers are saved to non-
volatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write opera-
tion can be monitored by a Write In Process bit (WIP).
The WIP bit is read with a Read Status command.

INSTRUCTIONS

Identification (ID) Byte
The first byte sent to the X9401 from the host, follow-
ing a CS going HIGH to LOW, is called the Identifica-
tion byte. The most significant four bits of the slave
address are a device type identifier, for the X9401 this
is fixed as 0101[B] (refer to Figure 1).

The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A

- A

input

pins. The X9401 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9401 to successfully
continue the command sequence. The A

- A

inputs

can be actively driven by CMOS input signals or tied to
V

or V

The remaining two bits in the slave byte must be set to 0.

Figure 1. Identification Byte Format

Instruction Byte
The next byte sent to the X9401 contains the instruc-
tion and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the four pots and, when applicable,
they point to one of four associated registers. The for-
mat is shown below in Figure 2.

Serial Data Path

From Interface

Circuitry

Serial

Bus
Input

Parallel

Bus
Input

Wiper

Counter

INC/DEC

Logic

UP/DN

CLK

Modified SCL

UP/DN

If WCR = 00[H] then V

= V

If WCR = 3F[H] then V

= V

u
n

c
o

d
e

(WCR)

(One of Four Arrays)

Device Type

Identifier

Device Address

X9401

FN8190.2

September 23, 2005

Figure 2. Instruction Byte Format

The four high order bits of the instruction byte specify
the operation. The next two bits (R

and R

) select

one of the four registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits (P1 and P

) selects which one of the four potenti-

ometers is to be affected by the instruction.

Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
These instructions are:

XFR Data Register to Wiper Counter Register--This

transfers the contents of one specified Data Register
to the associated Wiper Counter Register.

XFR Wiper Counter Register to Data Register--This

transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.

Global XFR Data Register to Wiper Counter Register

--This transfers the contents of all specified Data
Registers to the associated Wiper Counter Regis-
ters.

Global XFR Wiper Counter Register to Data

The basic sequence of the two byte instructions is illus-
trated in Figure 3. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a data register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper
to this action will be delayed by t

WRL

. A transfer from

the WCR (current wiper position), to a data register is a
write to nonvolatile memory and takes a minimum of
t

to complete. The transfer can occur between one

of the four potentiometers and one of its associated reg-
isters; or it may occur globally, where the transfer
occurs between all potentiometers and one associated
register.

Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9401; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are:

Read Wiper Counter Register-- read the current

wiper position of the selected pot,

Write Wiper Counter Register--change current

wiper position of the selected pot,

Read Data Register--read the contents of the

selected data register;

Write Data Register--write a new value to the

selected data register.

Read Status--This command returns the contents

of the WIP bit which indicates if the internal write
cycle is in progress.

The sequence of these operations is shown in Figure 4
and Figure 5.

The final command is Increment/Decrement. It is dif-
ferent from the other commands, because it's length is
indeterminate. Once the command is issued, the mas-
ter can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tun-
ing capability to the host. For each SCK clock pulse
(t

HIGH

) while SI is HIGH, the selected wiper will move

one resistor segment towards the V

terminal.

Similarly, for each SCK clock pulse while SI is LOW,
the selected wiper will move one resistor segment
towards the V

terminal. A detailed illustration of the

sequence and timing for this operation are shown in
Figure 6 and Figure 7.

Pot Select

Select

Instructions

X9401

FN8190.2

September 23, 2005

Figure 7. Increment/Decrement Timing Limits

Table 1. Instruction Set

Instruction

Instruction Set

Operation

Read Wiper Counter Register 1

Read the contents of the Wiper Counter Register

pointed to by P

- P

Write Wiper Counter Register 1

Write new value to the Wiper Counter Register

pointed to by P

- P

Read Data Register

Read the contents of the Data Register pointed to by

- P

and R

- R

Write Data Register

Write new value to the Data Register pointed to by

- P

and R

- R

XFR Data Register to Wiper

Counter Register

Transfer the contents of the Data Register pointed to

by R

- R

to the Wiper Counter Register pointed to by

- P

XFR Wiper Counter Register

to Data Register

Transfer the contents of the Wiper Counter Register

pointed to by P

- P

to the Register pointed to by

- R

Global XFR Data Register to

Wiper Counter Register

Transfer the contents of the Data Registers pointed to

by R

- R

of all four pots to their respective Wiper

Counter Register

Global XFR Wiper Counter

Transfer the contents of all Wiper Counter Registers

to their respective data Registers pointed to by

- R

of all four pots

Increment/Decrement Wiper

Counter Register

Enable Increment/decrement of the Wiper Counter

- P

Read Status (WIP bit)

Read the status of the internal write cycle, by

checking the WIP bit.

SCK

INC/DEC CMD Issued

WRID

Voltage Out

X9401

FN8190.2

September 23, 2005

Instruction Format

Notes: (1) "A1 ~ A0": stands for the device addresses sent by the master.

(2) WPx refers to wiper position data in the Counter Register
(3) "I": stands for the increment operation, SI held HIGH during active SCK phase (high).
(4) "D": stands for the decrement operation, SI held LOW during active SCK phase (high).

Read Wiper Counter Register (WCR)

Write Wiper Counter Register (WCR)

Read Data Register (DR)

Write Data Register (DR)

Transfer Data Register (DR) to Wiper Counter Register (WCR)

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

wiper position

(sent by X9401 on SO)

Rising

Edge

0 1 0 1 0 0 A

0 1 0 0 1 0 0

0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

Data Byte

(sent by Host on SI)

Rising

Edge

0 1 0 1 0 0 A

0 1 0 1 0 0 0

0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

DR and WCR

addresses

Data Byte

(sent by X9401 on SO)

Rising

Edge

0 1 0 1 0 0 A

0 1 0 1 1

0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

DR and WCR

addresses

Data Byte

(sent by host on SI)

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 0 0 A

0 1 1 0 0

0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

DR and WCR

addresses

Rising

Edge

0 1 0 1 0 0 A

0 1 1 0 1

X9401

FN8190.2

September 23, 2005

Transfer Wiper Counter Register (WCR) to Data Register (DR)

Increment/Decrement Wiper Counter Register (WCR)

Global Transfer Data Register (DR) to Wiper Counter Register (WCR)

Global Transfer Wiper Counter Register (WCR) to Data Register (DR)

Read Status

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

DR and WCR

addresses

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 0 0 A

0 1 1 1 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

increment/decrement

(sent by master on SDA)

Rising

Edge

0 1 0 1 0 0 A

0 0 0 1 0 X X

D .

. I/

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

addresses

Rising

Edge

0 1 0 1 0 0 A

0 0 0 0 1

0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

addresses

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 0 0 A

0 1 0 0 0

0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

wiper

addresses

Data Byte

(sent by X9401 on SO)

Rising

Edge

0 1 0 1 0 0 A

0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0

X9401

FN8190.2

September 23, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65

C to +135

Storage temperature ......................... -65

C to +150

Voltage on SCK, SCL or any address

input with respect to V

......................... -1V to +7V

V = |(V

)|...................................................... 5.5V

Lead temperature (soldering, 10s) .................... 300

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this specifi-
cation) is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

POWER-UP AND DOWN REQUIREMENTS
The are no restrictions on the power-up or power-down conditions of V

and the voltages applied to the poten-

tiometer pins provided that V

is always more positive than or equal to V

, V

, and V

, i.e., V

, V

The V

power-up spec is always in effect.

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-

eter. It is a measure of the error in step size.

(3) MI = RTOT/63 or (V

- V

)/63, single pot

Symbol

Parameter

Limits

Test Condition

Min.

Typ.

Max.

Unit

TOTAL

End to end resistance

+20

Power rating

C, each pot

Wiper current

Wiper resistance

150

500

Wiper Current =

3mA

TERM

Voltage on any V

or V

= 0V

Noise

-120

dBV

Ref: 1kHz

Resolution

1.6

Absolute linearity

(1)

-1

(3)

w(n)(actual)

- V

w(n)(expected)

Relative linearity

(2)

-0.2

+0.2

(3)

w(n + 1)

- [V

w(n) + MI

]

Temperature coefficient of R

TOTAL

300

ppm/

Ratiometric temp. coefficient

±20

ppm/°C

Potentiometer capacitances

10/10/25

See Macro model

, R

leakage current

0.1

µA

= V

to V

. Device is in

stand-by mode.

RECOMMENDED OPERATING CONDITIONS

Temp

Min.

Max.

Commercial

+70

Industrial

-40

+85

Device

Supply Voltage (V

) Limits

X9401

10%

X9401-2.7

2.7V to 5.5V

X9401

FN8190.2

September 23, 2005

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

ENDURANCE AND DATA RETENTION

CAPACITANCE

POWER-UP TIMING

A.C. TEST CONDITIONS

Notes: (4) This parameter is periodically sampled and not 100%

tested

(5) t

PUR

and t

PUW

are the delays required from the time

the (last) power supply (V

-) is stable until the specific

instruction can be issued. These parameters are period-
ically sampled and not 100% tested.

(6) This is not a tested or guaranteed parameter and should

be used only as a guideline.

EQUIVALENT A.C. LOAD CIRCUIT

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Unit

CC1

supply current (active)

400

µA

SCK

= 2MHz, SO = Open,

Other Inputs = V

CC2

supply current (nonvola-

tile write)

SCK

= 2MHz, SO = Open,

Other Inputs = V

current (standby)

µA

SCK = SI = V

, Addr. = V

CS = V

Input leakage current

µA

= V

to V

Output leakage current

µA

OUT

= V

to V

Input HIGH voltage

x 0.7

+ 0.5

Input LOW voltage

-0.5

x 0.1

Output LOW voltage

0.4

= 3mA

Parameter

Min.

Unit

Minimum endurance

100,000

Data changes per bit per register

Data retention

100

years

Symbol

Test

Max.

Unit

Test Condition

OUT

(4)

Output capacitance (SO)

OUT

= 0V

(4)

Input capacitance (A0, A1, SI, and SCK)

= 0V

Symbol

Parameter Min.

Max.

Unit

(6)

Power-up rate

0.2

V/ms

PUR

(5)

Power-up to initiation of read operation

PUW

(5)

Power-up to initiation of write operation

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x 0.5

1533

100pF

SDA

Output

10pF

TOTAL

25pF

10pF

SPICE Macro Model

X9401

FN8190.2

September 23, 2005

AC TIMING

HIGH-VOLTAGE WRITE CYCLE TIMING

XDCP TIMING

Symbol

Parameter

Min.

Max.

Unit

SCK

SSI/SPI clock frequency

2.0

MHz

CYC

SSI/SPI clock cycle rime

500

SSI/SPI clock high rime

200

SSI/SPI clock low time

200

LEAD

Lead time

250

LAG

Lag time

250

SI, SCK, HOLD and CS input setup time

SI, SCK, HOLD and CS input hold time

SI, SCK, HOLD and CS input rise time

µs

SI, SCK, HOLD and CS input fall time

µs

DIS

SO output disable time

500

SO output valid time

100

SO output hold time

SO output rise time

SO output fall time

HOLD

HOLD time

400

HSU

HOLD setup time

100

HOLD hold time

100

HOLD low to output in high Z

100

HOLD high to output in low Z

100

Noise suppression time constant at SI, SCK, HOLD and CS inputs

CS deselect time

µs

WPASU

WP, A0 and A1 setup time

WPAH

WP, A0 and A1 hold time

Symbol

Parameter

Typ.

Max.

Unit

High-voltage write cycle time (store instructions)

Symbol

Parameter

Min. Max.

Unit

WRPO

Wiper response time after the third (last) power supply is stable

µs

WRL

Wiper response time after instruction issued (all load instructions)

µs

WRID

Wiper response time from an active SCL/SCK edge (increment/decrement instruction)

450

X9401

FN8190.2

September 23, 2005

Application Circuits

Noninverting Amplifier

Voltage Regulator

Offset Voltage Adjustment

Comparator with Hysteresis

= (1+R

adj

(REG) = 1.25V (1+R

)+I

adj

(REG)

317

= {R

/(R

)} V

(max)

= {R

/(R

)} V

(min)

100k

10k

+5V

TL072

}

Attenuator

Filter

= G V

-1/2

+1/2

= 1 + R

fc = 1/(2

RC)

All R

= 10k

X9401

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8190.2

September 23, 2005

PACKAGING INFORMATION

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

24-Lead Plastic, TSSOP Package Type V

.169 (4.3)
.177 (4.5)

.252 (6.4) BSC

.026 (.65) BSC

.303 (7.70)
.311 (7.90)

.002 (.06)
.005 (.15)

.047 (1.20)

.0075 (.19)

.0118 (.30)

See Detail "A"

.031 (.80)

.041 (1.05)

.010 (.25)

.020 (.50)
.030 (.75)

Gage Plane

Seating Plane

Detail A (20X)

(4.16) (7.72)

(1.78)

(0.42)

(0.65)

ALL MEASUREMENTS ARE TYPICAL

0° - 8°

X9401

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9401

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9401