X9420

Low Noise/Low Power/SPI Bus

Single Digitally Controlled (XDCPTM)

Potentiometer

FEATURES

· Solid-State Potentiometer
· SPI serial interface
· Register oriented format

--Direct read/write/transfer wiper positions
--Store as many as four positions per

potentiometer

· Power supplies

--V

= 2.7V to 5.5V

--V+ = 2.7V to 5.5V
--V = -2.7V to -5.5V

· Low power CMOS

--Standby current < 1µA

· High reliability

--Endurance100,000 data changes per bit per

register

--Register data retention100 years

· 8-bytes of nonvolatile EEPROM memory
· 10k

or 2.5k

resistor arrays

· Resolution: 64 taps each pot
· 14-lead TSSOP, 16-lead SOIC, and 16-pin plastic

DIP packages

DESCRIPTION

The X9420 integrates a single digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.

The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power-up recalls
the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

BLOCK DIAGRAM

R0 R1

R2 R3

Wiper

Counter

(WCR)

Interface

and

Control

Circuitry

HOLD

Data

SCK

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Data Sheet

FN8195.0

March 7, 2005

FN8195.0

March 7, 2005

PIN DESCRIPTIONS

Host Interface Pins

Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.

Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the potentiometer
and pot register are input on this pin. Data is latched
by the rising edge of the serial clock.

Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9420.

Chip Select (CS)
When CS is HIGH, the X9420 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9420, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.

Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.

Device Address (A

)

The address inputs is used to set the least significant
bit of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9420. A maximum of 2 devices may occupy the
SPI serial bus.

Potentiometer Pins
V

, V

The V

and V

input are equivalent to the

terminal connections on either end of a mechanical
potentiometer.

The wiper output is equivalent to the wiper output of a
mechanical potentiometer.

Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers. Writing to the Wiper Counter
Register is not restricted.

Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.

System/Digital Supply (V

)

is the supply voltage for the system/digital

section. V

is the system ground.

PIN CONFIGURATION

2
3

4
5

6
7

15
14

13
12

11
10

V+

NC
A0

HOLD
SCK

NC
V-

DIP/SOIC

X9420

TSSOP

2
3

4
5

6
7

13
12

11
10

9
8

V+

HOLD
SCK
V-

X9420

FN8195.0

March 7, 2005

PIN NAMES

PRINCIPLES OF OPERATION

The X9420 is a highly integrated microcircuit
incorporating a resistor array and associated registers
and counter and the serial interface logic providing
direct communication between the host and the XDCP
potentiometer.

Serial Interface
The X9420 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.

The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.

Array Description
The X9420 is comprised of one resistor array
containing 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V

and V

inputs).

At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(V

) output. Within the individual array only one

switch may be turned on at a time.

These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded to
select, and enable, one of sixty-four switches. The block
diagram of the potentiometer is shown in Figure 1.

Wiper Counter Register (WCR)
The X9420 contains a Wiper Counter Register. The
WCR can be envisioned as a 6-bit parallel and serial
load counter with its outputs decoded to select one of
sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/ Decrement
instruction. Finally, it is loaded with the contents of its
data register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9420 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.

Data Registers
The potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the WCR. It should be noted all
operations changing data in one of the Data Registers is
a nonvolatile operation and will take a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.

Register Descriptions

Table 1. Data Registers, (6-bit), Nonvolatile

There are four 6-bit Data Registers associated with the
potentiometer.

{D5~D0}: These bits are for general purpose Non-

volatile data storage or for storage of up to four dif-
ferent wiper values.

Table 2. Wiper Counter Register, (6-bit), Volatile

{WP5~WP0}: These bits specify the wiper position

of the potentiometer.

Symbol

Description

SCK

Serial Clock

SI, SO

Serial Data

Device Address

Potentiometer Pins (terminal equivalent)

Potentiometer Pins (wiper equivalent)

Hardware Write Protection

HOLD

Serial Communication Pause

V+,V-

Analog Supplies

System Supply Voltage

System Ground

No Connection

(MSB)

(LSB)

WP5 WP4 WP3 WP2 WP1 WP0

(MSB)

(LSB)

X9420

FN8195.0

March 7, 2005

Figure 1. Detailed Potentiometer Block Diagram

Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write operation
can be monitored by a Write In Process bit (WIP). The
WIP bit is read with a Read Status command.

INSTRUCTIONS

Address/Identification (ID) Byte
The first byte sent to the X9420 from the host,
following a CS going HIGH to LOW, is called the
Address or Identification byte. The most significant
four bits of the slave address are a device type
identifier, for the X9420 this is fixed as 0101[B] (refer
to Figure 2).

The least significant bit in the ID byte selects one of
two devices on the bus. The physical device address
is defined by the state of the A

input pin. The X9420

compares the serial data stream with the address
input state; a successful compare of the address bit is
required for the X9420 to successfully continue the
command sequence. The A

input can be actively

driven by a CMOS input signal or tied to V

or V

The remaining three bits in the ID byte must be set to 110.

Figure 2. Address/Identification Byte Format

Instruction Byte
The next byte sent to the X9420 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next two
bits point to one of four data registers. The format is
shown below in Figure 3.

Figure 3. Instruction Byte Format

Serial Data Path

From Interface

Circuitry

Serial

Bus
Input

Parallel

Bus
Input

Counter

INC/DEC

Logic

UP/DN

CLK

Modified SCK

UP/DN

C
O

U
N

T
E

D
E

C
O

D
E

IF WCR = 00[H] THEN V

= V

IF WCR = 3F[H] THEN V

= V

Wiper

(WCR)

Device Type

Identifier

Device Address

Select

Instructions

X9420

FN8195.0

March 7, 2005

The four high order bits of the instruction byte specify
the operation. The next two bits (R

and R

) select

one of the four registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits are defined as 0.

Two of the eight instructions are two bytes in length
and end with the transmission of the instruction byte.
These instructions are:

XFR Data Register to Wiper Counter Register --

This instruction transfers the contents of one speci-
fied Data Register to the Wiper Counter Register.

XFR Wiper Counter Register to Data Register--This

instruction transfers the contents of the Wiper
Counter Register to the specified associated Data
Register.

The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper
to this action will be delayed by t

WRL

. A transfer from

the WCR (current wiper position), to a Data Register is
a write to nonvolatile memory and takes a minimum of
t

to complete. The transfer can occur between the

potentiometer and one of its associated registers.

Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9420; either between the host and
one of the Data Registers or directly between the host
and the WCR. These instructions are:

Read Wiper Counter Register--read the current

wiper position of the pot,

Write Wiper Counter Register--change current

wiper position of the pot,

Read Data Register--read the contents of the

selected data register;

Write Data Register--write a new value to the

selected data register.

Read Status--This command returns the contents

of the WIP bit which indicates if the internal write
cycle is in progress.

The sequence of these operations is shown in Figure
5 and Figure 6.

The final command is Increment/Decrement. It is
different from the other commands, because it's length
is indeterminate. Once the command is issued, the
master can clock the wiper up and/or down in one
resistor segment steps; thereby, providing a fine
tuning capability to the host. For each SCK clock pulse
(t

HIGH

) while SI is HIGH, the selected wiper will move

one resistor segment towards the V

terminal.

Similarly, for each SCK clock pulse while SI is LOW,
the selected wiper will move one resistor segment
towards the V

terminal. A detailed illustration of

the sequence and timing for this operation are shown
in Figure 7 and Figure 8.

Figure 4. Two-Byte Instruction Sequence

R1 R0

SCK

X9420

FN8195.0

March 7, 2005

Table 3. Instruction Set

Instruction

Instruction Set

Operation

Read Wiper Counter

Read the contents of the Wiper Counter Register

Write Wiper Counter

Write new value to the Wiper Counter Register

Read Data Register

Read the contents of the Data Register pointed to by

- R

Write Data Register

Write new value to the Data Register pointed to by

- R

XFR Data Register to

Wiper Counter

Transfer the contents of the Data Register pointed to

by R

- R

to the Wiper Counter Register

XFR Wiper Counter

Transfer the contents of the Wiper Counter

- R

Increment/Decrement

Wiper Counter

Enable Increment/decrement of the Wiper Counter

Read Status (WIP bit)

Read the status of the internal write cycle, by check-

ing the WIP bit.

X9420

FN8195.0

March 7, 2005

Instruction Format

Notes: (1) "A1 ~ A0": stands for the device addresses sent by the master.

(2) WPx refers to wiper position data in the Wiper Counter Register

"I": stands for the increment operation, SI held HIGH during active SCK phase (high).

(3) "D": stands for the decrement operation, SI held LOW during active SCK phase (high).

Read Wiper Counter Register (WCR)

Write Wiper Counter Register (WCR)

Read Data Register (DR)
Read the contents of the Register pointed to by R1 - R0.

Write Data Register (DR)
Write a new value to the Register pointed to by R1 - R0.

Transfer Data Register (DR) to Wiper Counter Register (WCR)
Transfer the contents of the Register pointed to by R1 - R0 to the WCR.

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

wiper position

(sent by X9420 on SO)

Rising

Edge

0 1 0 1 1 1 0 A

0 1 0 0 1 0 0 0 0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

Data Byte

(sent by Host on SI)

Rising

Edge

0 1 0 1 1 1 0 A

0 1 0 1 0 0 0 0 0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

addresses

Data Byte

(sent by X9420 on SO)

Rising

Edge

0 1 0 1 1 1 0 A

0 1 0 1 1

0 0 0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

addresses

Data Byte

(sent by host on SI)

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 1 1 0 A

0 1 1 0 0

0 0 0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

addresses

Rising

Edge

0 1 0 1 1 1 0 A

0 1 1 0 1

0 0 0

X9420

FN8195.0

March 7, 2005

Transfer Wiper Counter Register (WCR) to Data Register (DR)

Increment/Decrement Wiper Counter Register (WCR)

Read Status

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

addresses

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 1 1 0 A

0 1 1 1 0

0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

increment/decrement

(sent by master on SDA)

Rising

Edge

0 1 0 1 1 1 0 A

0 0 0 1 0 0 0 0 0 I/D I/D .

. I/D I/D

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

Data Byte

(sent by X9420 on SO)

Rising

Edge

0 1 0 1 1 1 0 A

0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0

X9420

FN8195.0

March 7, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SCK, SCL or any

address input with respect to V

........... -1V to +7V

Voltage on V+ (referenced to V

)........................ 10V

Voltage on V- (referenced to V

)........................-10V

(V+) - (V-) .............................................................. 12V
Any V

, V

........................... V- to V+

Lead temperature (soldering, 10 seconds)........ 300°C
I

(10 seconds)..................................................±6mA

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as

a potentiometer.

(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-

ometer. It is a measure of the error in step size.

(3) MI = RTOT/63 or (V

- V

)/63, single pot.

(4) Typical = Individual array resolution.

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Units

TOTAL

End to End Resistance

±20

Power Rating

25°C, each pot

Wiper Current

±3

Wiper Resistance

150

250

Wiper Current =

1mA,

V+/V- = ±3V

100

Wiper Current =

1mA,

V+/V- = ±5V

Vv+

Voltage on V+ Pin

X9420

+4.5

+5.5

X9420-2.7

+2.7

+5.5

Vv-

Voltage on V- Pin

X9420

-5.5

-4.5

X9420-2.7

-5.5

-2.7

TERM

Voltage on any V

, V

V-

V+

Noise

-140

dBV

Ref: 1kHz

Resolution

(4)

1.6

See Note 5

Absolute Linearity

(1)

±1

(3)

w(n)(actual)

- V

w(n)(expected)

Relative Linearity

(2)

±0.2

(3)

w(n + 1)

- [V

w(n) + MI

]

Temperature Coefficient of R

TOTAL

300

ppm/°C See Note 5

Ratiometric Temperature Coefficient

ppm/°C See Note 5

Potentiometer Capacitances

10/10/25

See Circuit #3

Rh, RI, Rw leakage current

0.1

µA

Vin = V- to V+. Device is in

stand-by mode.

RECOMMENDED OPERATING CONDITIONS

Temp

Min.

Max.

Commercial

+70

Industrial

-40

+85

Device

Supply Voltage (V

) Limits

X9420

10%

X9420-2.7

2.7V to 5.5V

X9420

FN8195.0

March 7, 2005

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

ENDURANCE AND DATA RETENTION

CAPACITANCE

POWER-UP TIMING

POWER-UP REQUIREMENTS (Power-up sequencing can affect correct recall of the wiper registers)

The preferred power-on sequence is as follows: First V

, then V+ and V-, and then the potentiometer pins, R

, R

and R

. Voltage should not be applied to the potentiometer pins before V+ or V- is applied. The V

ramp rate

specification should be met, and any glitches or slope changes in the V

line should be held to <100mV if possible.

If V

powers down, it should be held below 0.1V for more than 1 second before powering up again in order for

proper wiper register recall. Also, V

should not reverse polarity by more than 0.5V. Recall of wiper position will not

be complete until V

, V+ and V- reach their final value.

Notes: (5) This parameter is periodically sampled and not 100% tested.

(6) t

PUR

and t

PUW

are the delays required from the time the third (last) power supply (V

, V+ or V-) is stable until the specific instruction

can be issued. These parameters are periodically sampled and not 100% tested.

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Units

CC1

Supply Current (Active)

400

µA

SCK

= 2MHz, SO = Open,

Other Inputs = V

CC2

Supply Current

(Non-volatile Write)

SCK

= 2MHz, SO = Open,

Other Inputs = V

Current (Standby)

SCK = SI = V

, Addr. = V

Input Leakage Current

= V

to V

Output Leakage Current

OUT

= V

to V

Input HIGH Voltage

x 0.7

+ 0.5

Input LOW Voltage

-0.5

x 0.1

Output LOW Voltage

0.4

= 3mA

Parameter

Min.

Units

Minimum Endurance

100,000

Data Changes per Bit per Register

Data Retention

100

Years

Symbol

Test

Max.

Units

Test Conditions

OUT

(5)

Output Capacitance (SO)

OUT

= 0V

(5)

Input Capacitance (A0, SI, and SCK)

= 0V

Symbol

Parameter Max.

Max.

Units

PUR

(6)

Power-up to Initiation of Read Operation

PUW

(6)

Power-up to Initiation of Write Operation

Power-up Ramp

0.2

V/msec

X9420

FN8195.0

March 7, 2005

A.C. TEST CONDITIONS

EQUIVALENT A.C. LOAD CIRCUIT

AC TIMING

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x 0.5

1533

100pF

SDA Output

Symbol

Parameter

Min.

Max.

Units

SCK

SSI/SPI Clock Frequency

2.0

MHz

CYC

SSI/SPI Clock Cycle Time

500

SSI/SPI Clock High Time

200

SSI/SPI Clock Low Time

200

LEAD

Lead Time

250

LAG

Lag Time

250

SI, SCK, HOLD and CS Input Setup Time

SI, SCK, HOLD and CS Input Hold Time

SI, SCK, HOLD and CS Input Rise Time

µs

SI, SCK, HOLD and CS Input Fall Time

µs

DIS

SO Output Disable Time

500

SO Output Valid Time

100

SO Output Hold Time

SO Output Rise Time

SO Output Fall Time

HOLD

HOLD Time

400

HSU

HOLD Setup Time

100

HOLD Hold Time

100

HOLD Low to Output in High Z

100

HOLD High to Output in Low Z

100

Noise Suppression Time Constant at SI, SCK, HOLD and CS inputs

CS Deselect Time

µs

WPASU

WP, A0 and A1 Setup Time

WPAH

WP, A0 and A1 Hold Time

X9420

FN8195.0

March 7, 2005

HIGH-VOLTAGE WRITE CYCLE TIMING

XDCP TIMING

SYMBOL TABLE

Symbol

Parameter

Typ.

Max.

Units

High-voltage Write Cycle Time (Store Instructions)

Symbol

Parameter

Min.

Max. Units

WRPO

Wiper Response Time After The Third (Last) Power Supply Is Stable

µs

WRL

Wiper Response Time After Instruction Issued (All Load Instructions)

µs

WRID

Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement

Instruction)

450

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from Low to

High

Will change

from Low to

High

May change

from High to

Low

Will change

from High to

Low

Don't Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

X9420

FN8195.0

March 7, 2005

APPLICATIONS INFORMATION

Electronic potentiometers provide three powerful application advantages: (1) the variability and reliability of a solid-
state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory
used for the storage of multiple potentiometer settings or data.

Basic Configurations of Electronic Potentiometers

Basic Circuits

Three terminal Potentiometer;

Variable voltage divider

Two terminal Variable Resistor;

Variable current

Noninverting Amplifier

Voltage Regulator

Offset Voltage Adjustment

Comparator with Hysterisis

= (1+R

adj

(REG) = 1.25V (1+R

)+I

adj

(REG)

317

= {R

/CR

} V

(max)

= {R

/CR

} V

(min)

100k

10k

-12V

+12V

TL072

}

+5V

-5V

LM308A

Cascading Techniques

Buffered Reference Voltage

+5V

-5V

OUT

= V

OP-07

(a)

(b)

X9420

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8195.0

March 7, 2005

Ordering Information

Device

Limits

Blank = 5V

10%

-2.7 = 2.7 to 5.5V

Temperature Range
Blank = Commercial = 0

C to +70

I = Industrial = -40

C to +85

M = Military = 55

C to +125

Package
P = 16-Lead Plastic DIP
S = 16-Lead SOIC
V = 14-Lead TSSOP

Potentiometer Organization
W = 10K
Y = 2.5K

X9420

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