FN8197.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9428

Low Noise/Low Power/2-Wire Bus

Single Digitally Controlled Potentiometer

(XDCPTM)

FEATURES

· Solid state potentiometer
· 2-wire serial interface
· Register oriented format

--Direct Read/Write/Transfer Wiper Position
--Store as many as Four Positions per

Potentiometer

· Power supplies

--V

= 2.7V to 5.5V

--V+ = 2.7V to 5.5V
--V = -2.7V to -5.5V

· Low power CMOS

--Standby current < 1µA
--Ideal for Battery Operated Applications

· High reliability

--Endurance100,000 Data Changes per Bit per

Register

--Register Data Retention100 years

· 4-bytes of nonvolatile memory
· 10k

resistor array

· Resolution: 64 taps each potentiometer
· SOIC and TSSOP packages

DESCRIPTION

The X9428 integrates a digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.

The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power-up recalls
the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

BLOCK DIAGRAM

R0 R1

R2 R3

Wiper

Counter

(WCR)

Interface

and

Control

Circuitry

SCL
SDA

A0
A2
A3

Data

V+
V

Data Sheet

March 8, 2005

FN8197.0

March 8, 2005

PIN DESCRIPTIONS

Host Interface Pins

Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9428.

Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.

Device Address (A

, A

)

The Address inputs are used to set the least
significant 3 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the Address input in order to initiate
communication with the X9428. A maximum of 8
devices may occupy the 2-wire serial bus.

Potentiometer Pins

, R

The R

and R

inputs are equivalent to the

terminal connections on either end of a mechanical
potentiometer.

The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.

Hardware Write Protect Input WP
The WP pin when low prevents nonvolatile writes to
the Data Registers.

Analog Supply V+, V-
The Analog Supply V+, V- are the supply voltages for
the XDCP analog section.

PIN CONFIGURATION

PIN NAMES

Symbol

Description

SCL

Serial clock

SDA

Serial data

A0, A2, A3

Device address

, V

Potentiometer Pins

(terminal equivalent)

Potentiometer Pin (wiper equivalent)

Hardware write protection

V+,V-

Analog and voltage follower

System supply voltage

System ground

No connection

SDA

2
3

4
5

6
7

15
14

13
12

11
10

V+

NC
A0

A3
SCL

NC
V-

DIP/SOIC

X9428

2
3

4
5

6
7

13
12

11
10

9
8

TSSOP

X9428

A2
R

SDA

V+
A0
NC
A3
SCL

V-

X9428

FN8197.0

March 8, 2005

PRINCIPLES OF OPERATION

The X9428 is a highly integrated microcircuit
incorporating a resistor array and its associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.

Serial Interface
The X9428 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9428 will be considered a
slave device in all applications.

Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (tLOW). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.

Start Condition
All commands to the X9428 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t

HIGH

). The X9428 continuously

monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.

Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.

Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.

The X9428 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9428 will respond with a final acknowledge.

Array Description
The X9428 is comprised of a resistor array. The array
contains 63 discrete resistive segments that are
connected in series. The physical ends of the array
are equivalent to the fixed terminals of a mechanical
potentiometer (V

and V

inputs).

At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(V

) output. Within each individual array only one

switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.

The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers and
the WCR can be read and written by the host system.

Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9428
this is fixed as 0101[B].

Figure 1. Slave Address

The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A

, A

inputs. The X9428

compares the serial data stream with the address
input state; a successful compare of all four address
bits is required for the X9428 to respond with an
acknowledge. The A

, A

inputs can be actively

driven by CMOS input signals or tied to V

or V

Device Type

Identifier

Device Address

X9428

FN8197.0

March 8, 2005

Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9428
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9428 is still busy with the write operation no ACK will
be returned. If the X9428 has completed the write
operation an ACK will be returned, and the master can
then proceed with the next operation.

Flow 1. ACK Polling Sequence

Instruction Structure
The next byte sent to the X9428 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of four associated registers. The format is
shown below in Figure 2.

Figure 2. Instruction Byte Format

The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four registers that
is to be acted upon when a register oriented instruction
is issued. Bits 0 and 1 are defined to be 0.

Four of the seven instructions end with the transmission
of the instruction byte. The basic sequence is illustrated
in Figure 3. These two-byte instructions exchange data
between the Wiper Counter Register and one of the
Data Registers. A transfer from a Data Register to a
Wiper Counter Register is essentially a write to a static
RAM. The response of the wiper to this action will be
delayed t

WRL

. A transfer from the Wiper Counter

to complete.

Four instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9428; either between the host and one of
the Data Registers or directly between the host and the
Wiper Counter Register. These instructions are: Read
Wiper Counter Register (read the current wiper position
of the selected pot), write Wiper Counter Register
(change current wiper position of the selected pot), read
Data Register (read the contents of the selected
nonvolatile register) and write Data Register (write a
new value to the selected Data Register). The
sequence of operations is shown in Figure 4.

Nonvolatile Write

Command Completed

Enter ACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

Further

Operation?

Issue

Instruction

Issue STOP

YES

Proceed

Issue STOP

Proceed

Select

Instructions

X9428

FN8197.0

March 8, 2005

Figure 3. Two-Byte Instruction Sequence

The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9428 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(t

HIGH

) while SDA is HIGH, the selected wiper will

move one resistor segment towards the V

terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the V

terminal. A detailed

illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.

Table 1. Instruction Set

Note:

(7) 1/0 = data is one or zero

A3 A2

R1 R0 0

SCL

SDA

Instruction

Instruction Set

Operation

Read Wiper Counter

Read the contents of the Wiper Counter Register

Write Wiper Counter

Write new value to the Wiper Counter Register

Read Data Register

1/0 1/0

Read the contents of the Data Register pointed to by

- R

Write Data Register

1/0 1/0

Write new value to the Data Register pointed to by

- R

XFR Data Register to

Wiper Counter Register

1/0 1/0

Transfer the contents of the Data Register pointed to

by R

- R

to its Wiper Counter Register

XFR Wiper Counter

1/0 1/0

Transfer the contents of the Wiper Counter Register

to the Data Register pointed to by R

- R

Increment/Decrement

Wiper Counter Register

1/0 Enable Increment/decrement of the Wiper Counter

X9428

FN8197.0

March 8, 2005

DETAILED OPERATION

The potentiometer has a Wiper Counter Register and
four Data Registers. A detailed discussion of the
register organization and array operation follows.

Wiper Counter Register
The X9428 contains a Wiper Counter Register. The
Wiper Counter Register can be envisioned as a 6-bit
parallel and serial load counter with its outputs
decoded to select one of sixty-four switches along its
resistor array. The contents of the WCR can be altered
in four ways: it may be written directly by the host via
the write Wiper Counter Register instruction (serial
load); it may be written indirectly by transferring the
contents of one of four associated Data Registers via
the XFR Data Register instruction (parallel load); it can
be modified one step at a time by the
Increment/Decrement instruction. Finally, it is loaded
with the contents of its Data Register zero (DR0) upon
power-up.

The WCR is a volatile register; that is, its contents are
lost when the X9428 is powered-down. Although the
register is automatically loaded with the value in DR0
upon power-up, it should be noted this may be
different from the value present at power-down.

Data Registers
The potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the Wiper Counter Register. It
should be noted all operations changing data in one of
these registers is a nonvolatile operation and will take
a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.

Register Descriptions

Data Registers, (6-Bit), Nonvolatile

Four 6-bit Data Registers for each XDCP. (eight 6-bit
registers in total).

{D5~D0}: These bits are for general purpose not

volatile data storage or for storage of up to four
different wiper values. The contents of Data Register
0 are automatically moved to the Wiper Counter
Register on power-up.

Wiper Counter Register, (6-Bit), Volatile

One 6-bit wiper counter register for each XDCP. (Four
6-bit registers in total.)

{D5~D0}: These bits specify the wiper position of the

respective XDCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register 0.
The contents of the WCR can be loaded from any of
the other Data Register or directly. The contents of
the WCR can be saved in a DR.

(MSB)

(LSB)

WP5

WP4

WP3

WP2

WP1

WP0

(MSB)

(LSB)

X9428

FN8197.0

March 8, 2005

Instruction Format

Notes: (1) "MACK"/"SACK": stands for the acknowledge sent by the master/slave.

(2) "A3 ~ A0": stands for the device addresses sent by the master.
(3) "X": indicates that it is a "0" for testing purpose but physically it is a "don't care" condition.
(4) "I": stands for the increment operation, SDA held high during active SCL phase (high).
(5) "D": stands for the decrement operation, SDA held low during active SCL phase (high).

Read Wiper Counter Register (WCR)

Write Wiper Counter Register (WCR)

Read Data Register (DR)

Write Data Register (DR)

XFR Data Register (DR) to Wiper Counter Register (WCR)

A
R

device type

identifier

device

addresses

S
A

instruction

opcode

S
A
C
K

wiper position

(sent by slave on SDA)

A
C
K

S
T

0 1 0 1 A

2 0

1 0 0 1 0 0 0 0

0 0

A
R

device type

identifier

device

addresses

S
A

instruction

opcode

S
A
C
K

wiper position

(sent by master on SDA)

S
A
C
K

S
T

0 1 0 1 A

2 0

1 0 1 0 0 0 0 0

0 0

A
R

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

addresses

S
A
C
K

wiper position/data

(sent by slave on SDA)

A
C
K

S
T

0 1 0 1 A

2 0

1 0 1 1 R

0 0 0

0 0

A
R

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

addresses

S
A
C
K

wiper position/data

(sent by master on SDA)

S
A

S
T

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 A

2 0

1 1 0 0 R

0 0 0

0 0

A
R

device type

identifier

device

addresses

S
A

instruction

opcode

addresses

S
A
C
K

S
T

0 1 0 1 A

2 0

1 1 0 1 R

0 0 0

X9428

FN8197.0

March 8, 2005

XFR Wiper Counter Register (WCR) to Data Register (DR)

Increment/Decrement Wiper Counter Register (WCR)

SYMBOL TABLE

Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors

S
T
A
R
T

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

addresses

S
A

S
T

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 A

2 0

1 1 1 0 R

0 0 0

S
T
A

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

S
A
C
K

increment/decrement

(sent by master on SDA)

0 1 0 1 A

2 0

0 0 1 0 0 0 0 0

D .

. I/

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from Low to

High

Will change

from Low to

High

May change

from High to

Low

Will change

from High to

Low

Don't Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

120

100

20 40 60 80 100 120

Resist

ance

(K)

Bus Capacitance (pF)

Min.

Resistance

Max.

Resistance

MAX

BUS

MIN

OL MIN

CC MAX

=1.8k

X9428

FN8197.0

March 8, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65

C to +135

Storage temperature ......................... -65

C to +150

Voltage on SDA, SCL or any address

input with respect to V

......................... -1V to +7V

Voltage on V+ (referenced to V

)........................ 10V

Voltage on V- (referenced to V

)........................-10V

(V+) - (V-) .............................................................. 12V
Any V

..............................................................V+

Any V

.................................................................V-

Lead temperature (soldering, 10 seconds)........ 300

(10 seconds)................................................±12mA

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Unit

End to end resistance tolerance

±20

Power rating

25°C, each pot

Wiper current

±6

Wiper resistance

150

250

Wiper current =

1mA, V

= 3V

100

Wiper current =

1mA, V

= 5V

V+

Voltage on V+ pin

X9428

+4.5

+5.5

X9428-2.7

+2.7

+5.5

V-

Voltage on V- pin

X9428

-5.5

-4.5

X9428-2.7

-5.5

-2.7

TERM

Voltage on any V

or V

V-

V+

Noise

-140

dBV

Ref: 1kHz

Resolution

(4)

1.6

Absolute linearity

(1)

±1

(3)

w(n)(actual)

- V

w(n)(expected)

Relative linearity

(2)

±0.2

(3)

w(n + 1 )

- [V

w(n) + MI

]

Temperature Coefficient of R

TOTAL

300

ppm/

Ratiometric Temperature Coefficient

±20

ppm/°C

Potentiometer Capacitances

10/10/25

See Circuit #3,

Spice Macromodel

RECOMMENDED OPERATING CONDITIONS

Temp

Min.

Max.

Commercial

+70

Industrial

-40

+85

Device

Supply Voltage (V

) Limits

X9428

10%

X9428-2.7

2.7V to 5.5V

X9428

FN8197.0

March 8, 2005

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-

eter. It is a measure of the error in step size.

(3) MI = RTOT/63 or (R

- R

)/63, single pot

(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.

ENDURANCE AND DATA RETENTION

CAPACITANCE

POWER-UP TIMING

POWER-UP AND POWER-DOWN

There are no restrictions on the power-up or power-down sequencing of the bias supplies V

, V+, and V- provided

that all three supplies reach their final values within 1msec of each other. However, at all times, the voltages on the
potentiometer pins must be less than V+ and more than V-. The recall of the wiper position from nonvolatile memory
is not in effect until all supplies reach their final value.

Notes: (5) This parameter is periodically sampled and not 100% tested

(6) t

PUR

and t

PUW

are the delays required from the time the third (last) power supply (V

, V+ or V-) is stable until the specific

instruction can be issued. These parameters are periodically sampled and not 100% tested.

(7) Sample tested only.

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Unit

CC1

supply current

(nonvolatile write)

SCL

= 400kHz, SDA = Open,

Other Inputs = V

CC2

supply current

(move wiper, write, read)

100

µA

SCL

= 400kHz, SDA = Open,

Other Inputs = V

current (standby)

µA

SCL = SDA = V

, Addr. = V

Input leakage current

µA

= V

to V

Output leakage current

µA

OUT

= V

to V

Input HIGH voltage

x 0.7

x 0.5

Input LOW voltage

-0.5

x 0.1

Output LOW voltage

0.4

= 3mA

Parameter

Min.

Unit

Minimum endurance

100,000

Data changes per bit per register

Data retention

100

Years

Symbol

Test

Max.

Unit

Test Conditions

I/O

(5)

Input/output capacitance (SDA)

I/O

= 0V

(5)

Input capacitance (A0, A1, A2, A3, and SCL)

= 0V

Symbol

Parameter Min.

Typ.

Max.

Unit

PUR

(6)

Power-up to initiation of read operation

PUW

(6)

Power-up to initiation of write operation

(7)

Power-up ramp rate

0.2

V/msec

X9428

FN8197.0

March 8, 2005

A.C. TEST CONDITIONS

EQUIVALENT A.C. LOAD CIRCUIT

Circuit #3 SPICE Macro Model

AC TIMING (over recommended operating conditions)

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x 0.5

1533

100pF

SDA Output

2.7V

100pF

10pF

TOTAL

25pF

10pF

Symbol

Parameter

Min.

Max.

Unit

SCL

Clock frequency

100

400

kHz

CYC

Clock cycle time

2500

HIGH

Clock high time

600

LOW

Clock low time

1300

SU:STA

Start setup time

600

HD:STA

Start hold time

600

SU:STO

Stop setup time

600

SU:DAT

SDA data input setup time

100

HD:DAT

SDA data input hold time

SCL and SDA rise time

300

SCL and SDA fall time

300

SCL low to SDA data output valid time

900

SDA data output hold time

Noise suppression time constant at SCL and SDA inputs

BUF

Bus free time (prior to any transmission)

1300

SU:WPA

WP, A0, A1, A2 and A3 setup time

HD:WPA

WP, A0, A1, A2 and A3 hold time

X9428

FN8197.0

March 8, 2005

HIGH-VOLTAGE WRITE CYCLE TIMING

XDCP TIMING

Note:

(8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling

edge of SCL.

TIMING DIAGRAMS

START and STOP Timing

Input Timing

Output Timing

Symbol

Parameter

Typ.

Max.

Unit

High-voltage write cycle time (store instructions)

Symbol

Parameter

Min.

Max.

Unit

WRPO

Wiper response time after the third (last) power supply is stable

µs

WRL

Wiper response time after instruction issued (all load instructions)

µs

WRID

Wiper response time from an active SCL/SCK edge (increment/decrement instruction)

µs

SU:STA

HD:STA

SU:STO

SCL

SDA

(START)

(STOP)

SCL

SDA

HIGH

LOW

CYC

HD:DAT

SU:DAT

BUF

SCL

SDA

X9428

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8197.0

March 8, 2005

Ordering Information

Device

Limits

Blank = 5V ±10%
-2.7 = 2.7 to 5.5V

Temperature Range
Blank = Commercial = 0

C to +70

I = Industrial = -40

C to +85

Package
P = 16-Lead Plastic DIP*
S = 16-Lead SOIC
V = 14-Lead TSSOP

Potentiometer Organization
Y =

W =

10k

X9428

*Note: P package only available as X9428WP16I-2.7 for prototyping. Other resistor values not available in package.

X9428

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9428YVI-2.7

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9428YVI-2.7