FN8198.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

PRELIMINARY

X9430

Programmable Analog

Dual Digitally Controlled Potentiometer

(XDCPTM) with Operational Amplifier

FEATURES

· Two CMOS voltage operational amplifiers
· Two digitally controlled potentiometers
· Can be combined or used separately
· Amplifiers

--Low voltage operation
--V+/V- = ±2.7V to ±5.5V
--Rail-to-rail CMOS performance
--1MHz gain bandwidth product

· Digitally controlled potentiometer

--Dual 64 tap potentiometers
--R

total

= 10k

--SPI serial interface
--V

= 2.7V to 5.5V

DESCRIPTION

The X9430 is a monolithic CMOS IC that incorporates
two operational amplifiers and two nonvolatile digitally
controlled potentiometers. The amplifiers are CMOS
differential input voltage operational amplifiers with
near rail-to-rail outputs. All pins for the two amplifiers
are brought out of the package to allow combining
them with the potentiometers or using them as com-
plete stand-alone amplifiers.

The digitally controlled potentiometers consist of a
series string of 63 polycrystalline resistors that behave
as standard integrated circuit resistors. The SPI serial
port, common to both pots, allows the user to program
the connection of the wiper output to any of the resis-
tor nodes in the series string. The wiper position is
saved in the on board E2 memory to allow for nonvola-
tile restoration of the wiper position.

A wide variety of applications can be implemented
using the potentiometers and the amplifiers. A typical
application is to implement the amplifier as a wiper
buffer in circuits that use the potentiometer as a voltage
reference. The potentiometer can also be combined
with the amplifier yielding a digitally programmable gain
amplifier or programmable current source.

BLOCK DIAGRAM

OUT1

Control and

SCK

Memory

NI0

V+

V-

OUT0

NI1

INV1

INV0

WCR1

WCR0

HOLD

Data Sheet

March 11, 2005

NOT RE

COMME

NDED FO

R NEW D

ESIGNS

NO REC

OMMEN

DED RE

PLACEM

ENT

contact

our Tec

hnical S

upport C

enter at

1-888-IN

TERSIL

or www.

intersil.c

om/tsc

FN8198.0

March 11, 2005

PIN DESCRIPTIONS

Host Interface Pins

Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.

Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the device are
input on this pin. Data is latched by the rising edge of
the serial clock.

Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9430.

Chip Select (CS)
When CS is HIGH, the X9430 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9430, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.

Hardware Write Protect Input WP
The WP pin when low prevents nonvolatile writes to
the wiper counter register.

Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume com-
munication, HOLD is brought HIGH, again while SCK
is LOW. If the pause feature is not used, HOLD should
be held HIGH at all times.

Device Address (A

- A

)

The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9430. A maximum of 4 devices may occupy the
SPI serial bus.

Potentiometer Pins

- R

), R

- R

)

The R

and R

inputs are equivalent to the terminal con-

nections on either end of a mechanical potentiometer.

- R

)

The wiper output is equivalent to the wiper output of a
mechanical potentiometer.

Amplifier and Device Pins

Amplifier Input Voltage V

(0,1) and V

INV

(0,1)

and V

INV

are inputs to the noninverting (+) and

inverting (-) inputs of the operational amplifiers.

Amplifier Output Voltage V

OUT

(0,1)

OUT

is the voltage output pin of the operational

amplifier.

Analog Supplies V+, V-
The Analog Supplies V+, V- are the supply voltages
for the XDCP analog section and the operational
amplifiers.

System Supply V

and Ground V

The system supply V

and its reference V

is used

to bias the interface and control circuits.

Alternate designations for R

, R

are V

, V

X9430

FN8198.0

March 11, 2005

PIN CONFIGURATION

PIN NAMES

PRINCIPLES OF OPERATION

The X9430 is an integrated microcircuit incorporating two
digitally controlled potentiometers, two operational
amplifiers and their associated registers and counters;
and the serial interface logic providing direct communica-
tion between the host and the digitally controlled
potentiometers.

Serial Interface
The X9430 supports the SPI interface hardware con-
ventions. The device is accessed via the SI input with
data clocked in on the rising edge of SCK. CS must be
LOW and the HOLD and WP pins must be HIGH dur-
ing the entire operation.

1
2
3
4
5
6
7
8
9
10

24
23
22
21
20
19
18
17
16
15

V+
V

OUT0

NI0

INV0

A0
S0
HOLD
SCK
V

INV1

NI1

SOIC

X9430

OUT1

V-

INV0

NI0

HOLD

SCK

1
2
3
4
5
6
7
8
9
10

24
23
22
21
20
19
18
17
16

TSSOP

X9430

V+

OUT0

OUT1

NI1

INV1

14
13

Symbol

Description

SCK

Serial Clock

Serial Input

Serial Output

A0 - A1

Device Address

Chip Select

HOLD

Hold

- R

, R

- R

Potentiometers (terminal

equivalent)

- R

Potentiometers (wiper

equivalent)

NI(0,1)

, V

INV(0,1)

Amplifier Input Voltages

OUT0,

OUT1

Amplifier Outputs

Hardware Write Protection

V+,V-

Analog and Voltage Amplifier

Supplies

System/Digital Supply Voltage

System Ground

X9430

FN8198.0

March 11, 2005

Potentiometer/Array Description
The X9430 is comprised of two resistor arrays and two
operational amplifiers. Each array contains 63 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R

and R

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R

) output. Within each individual array only one

switch may be turned on at a time. These switches are
controlled by a volatile wiper counter register (WCR).
The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches.

The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.

Operational Amplifier
The voltage operational amplifiers are CMOS rail-to-
rail output general purpose amplifiers. They are
designed to operate from dual (±) power supplies. The
amplifiers may be configured like any standard ampli-
fier. All pins are externally available to allow connec-
tion with the potentiometers or as stand alone
amplifiers.

Write in Process
The contents of the data registers are saved to nonvol-
atile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write opera-
tion can be monitored by a write in process bit (WIP).
The WIP bit is read with a read status command.

INSTRUCTIONS AND PROGRAMMING

Identification (ID) Byte
The first byte sent to the X9430 from the host, follow-
ing a CS going HIGH to LOW, is called the identifica-
tion byte. The most significant four bits of the slave
address are a device type identifier, for the X9430 this
is fixed as 0101[B] (refer to Figure 1).

Detailed Block Diagram

OUT (0,1)

(DR0 - DR3)

0,1

Control and

SCK

A1
A0

H (0,1)

L (0,1)

W (0,1)

N (0,1)

WCR

0,1

(DR0 - DR3)

0,1

INV (0,1)

HOLD

Memory

WCR0

WCR1

(One of 2 Circuits)

X9430

FN8198.0

March 11, 2005

The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A

- A

input

pins. The X9430 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9430 to successfully
continue the command sequence. The A

- A

inputs

can be actively driven by CMOS input signals or tied to
V

or V

The remaining two bits in the slave byte must be set to 0.

Figure 1. Identification Byte Format

Instruction Byte
The next byte sent to the X9430 contains the instruc-
tion and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the WCRs of the two pots, and when
applicable, they point to one of four associated data
registers. The format is shown below in Figure 2.

Figure 2. Instruction Byte Format

The four high order bits of the instruction byte specify
the operation. The next two bits (R

and R

) select one

of the four registers that is to be acted upon when a
register oriented instruction is issued. The last bit (P

)

selects which one of the two potentiometers is to be
affected by the instruction.

Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.

The basic sequence of the two byte instructions is
illustrated in Figure 3. These two-byte instructions
exchange data between a wiper counter register and
one of the four data registers associated with each. A
transfer from a data register to a wiper counter register
is essentially a write to a static RAM. The response of
the wiper to this action will be delayed t

WRL

. A transfer

from the wiper counter register (current wiper position)
to a data register is a write to nonvolatile memory and
takes a minimum of t

to complete. The transfer can

occur between one of the two potentiometers and one
of its associated registers; or it may occur globally,
wherein the transfer occurs between both of the poten-
tiometers and one of their associated registers.

Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9430; either between the host and
one of the data registers or directly between the host
and the Wiper Counter and Registers. These instruc-
tions are: 1) Read Wiper Counter Register, read the
current wiper position of the selected pot 2) Write
Wiper Counter Register, i.e. change current wiper
position of the selected pot; 3) Read Data Register,
read the contents of the selected nonvolatile register; 4)
Write Data Register, write a new value to the selected
data register; 5)Read Status, returns the contents of the
WIP bit which indicates if an internal write cycle is in
progress.

The sequence of these operations is shown in Figure
4 and Figure 5.

The final command is Increment/Decrement. It is differ-
ent from the other commands, because it's length is
indeterminate. Once the command is issued, the master
can clock the selected wiper up and/or down in one resis-
tor segment steps; thereby, providing a fine tuning capa-
bility to the host. For each SCK clock pulse (t

HIGH

) while

SI is HIGH, the selected wiper will move one resistor
segment towards the V

terminal. Similarly, for each

SCK clock pulse while SI is LOW, the selected wiper will
move one resistor segment towards the V

terminal. A

detailed illustration of the sequence and timing for this
operation are shown in Figure 6 and Figure 7.

Device Type

Identifier

Device Address

WCR Select

Select

Instructions

X9430

FN8198.0

March 11, 2005

Figure 7. Increment/Decrement Timing

REGISTER OPERATION

Both digitally controlled potentiometers share the serial
interface and share a common architecture. Each poten-
tiometer is associated with a wiper counter register
(WCR), and four data registers. Figure 8 illustrates the
control, registers, and system features of the device.

Figure 8. System Block Diagram

Wiper Counter (WCR) and Analog Control
Registers (ACR)
The X9430 contains two wiper counter registers, one
for each XDCP. The wiper counter register is equiva-
lent to a serial-in, parallel-out counter with its outputs
decoded to select one of sixty-four switches along its
resistor array. The contents of the wiper counter register
can be altered in four ways: it may be written directly
by the host via the write WCR instruction (serial load);
it may be written indirectly by transferring the contents
of one of four associated data registers (DR) via the
XFR data register instruction (parallel load); it can be
modified one step at a time by the increment/decre-
ment instruction (WCR only). Finally, it may be loaded
with the contents of its associated data register zero
(R0) upon power-up.

The wiper counter register is a volatile register; that is, its
contents are lost when the X9430 is powered-down.
Although the registers are automatically loaded with the
value in R0 upon power-up, it should be noted this may
be different from the value present at power-down.

Data Registers (DR)
Each potentiometer has four nonvolatile data registers
(DR). These can be read or written directly by the host
and data can be transferred between any of the four data
registers and the WCR. It should be noted all operations
changing data in one of these registers is a nonvolatile
operation and will take a maximum of 10ms.

If the application does not require storage of multiple set-
tings for the potentiometer, these registers can be used
as regular memory locations that could store system
parameters or user preference data.

SCK

INC/DEC CMD Issued

WRID

OUT

OUT (0,1)

(DR0-DR3)

0,1

Control and

SCK

H (0,1)

L (0,1)

W (0,1)

N (0,1)

WCR

0,1

INV (0,1)

HOLD

Memory

WCR0

WCR1

Detailed Block Diagram

X9430

FN8198.0

March 11, 2005

REGISTER DESCRIPTIONS AND MEMORY MAP

Memory Map

Wiper Counter Register (WCR)

WP0 - WP5 identify wiper position.

Data Registers (DR, R0 - R3)

Instruction Format

Notes: (1) "A1 ~ A0": stands for the device addresses sent by the master.

(2) WPx refers to wiper position data in the Wiper Counter Register
(3) "I": stands for the increment operation, SI held HIGH during active SCK phase (high).
(4) "D": stands for the decrement operation, SI held LOW during active SCK phase (high).

Read Wiper Counter Register (WCR)

Read the contents of the Wiper Counter Register pointed to by P

- P

Write Wiper Counter Register (WCR)

Write new value to the Wiper Counter Register pointed to by P

- P

Read Data Register (DR)

Read the contents of the Register pointed to by P

- P

and R

- R

Write Data Register (DR)

Write new value to the Register pointed to by P

- P

and R

- R

WCRO

WCR1

DR0

DR1

DR2

DR3

WP5 WP4 WP3 WP2 WP1

WP0

(volatile)

(LSB)

Wiper Position or User Data
(Nonvolatile)

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

wiper position

(sent by X9430 on SO)

Rising

Edge

0 1 0 1 0 0 A

0 1 0 0 1 0 0 0

0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

Data Byte

(sent by Host on SI)

Rising

Edge

0 1 0 1 0 0 A

0 1 0 1 0 0 0 0

0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

DR/WCR

addresses

Data Byte

(sent by X9430 on SO)

Rising

Edge

0 1 0 1 0 0 A

0 1 0 1 1

0 0

0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

DR/WCR

addresses

Data Byte

(sent by host on SI)

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 0 0 A

0 1 1 0 0

0 0 0

X9430

FN8198.0

March 11, 2005

Transfer Data Register (DR) to Wiper Counter Register (WCR)

Transfer the contents of the Register pointed to by R

- R

to the WCR

Transfer Wiper Counter Register (WCR) to Data Register (DR)

Transfer the contents of the WCR to the Register pointed to by R

- R

Increment/Decrement Wiper Counter Register (WCR)

Enable Increment/decrement of the WCR pointed to by P

- P

Global Transfer Data Register (DR) to Wiper Counter Register (WCR)

Transfer the contents of all four Data Registers pointed to by R

- R

to their respective WCR

Global Transfer Wiper Counter Register (WCR) to Data Register (DR)

Transfer the contents of all WCRs to their respective data Registers pointed to by R

- R

Read Status

Returns the contents of the WIP bit which indicates if an internal write cycle is in progress

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

DR/WCR

addresses

Rising

Edge

0 1 0 1 0 0 A

0 1 1 0 1

0 P

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

DR/WCR

addresses

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 0 0 A

0 1 1 1 0

0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

increment/decrement

(sent by master on SDA)

Rising

Edge

0 1 0 1 0 0 A

0 0 0 1 0 X X 0

D .

. I/

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

addresses

Rising

Edge

0 1 0 1 0 0 A

0 0 0 0 1

0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

addresses

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 0 0 A

0 1 0 0 0

0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

wiper

addresses

Data Byte

(sent by X9430 on SO)

Rising

Edge

0 1 0 1 0 0 A

0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0

X9430

: 0-WCR0, 1-WCR1

FN8198.0

March 11, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65

C to +135

Storage temperature ......................... -65

C to +150

Voltage on SCK, SCL or any

address input with respect to V

........... -1V to +7V

Voltage on V+ (referenced to V

) ........................+7V

Voltage on V- (referenced to V

) ..........................-7V

(V+) - (V-) .............................................................. 10V
Any V

.....................................................................V+

Any V

......................................................................V-

Lead temperature (soldering, 10 seconds)........ 300

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.

POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

potentiometer. It is a measure of the error in step size.

(3) MI = RTOT/63 or (R

- R

)/63, single pot (=LSB)

(4) Individual array resolutions

Symbol

Parameter

Limits

Test Conditions

Min. Typ. Max.

Unit

TOTAL

End to end resistance

-20

+20

Power rating

C, each pot

Wiper current

-3

Wiper resistance

100

V+ = 5V, V- = -5V, I

= 3mA

100

250

V+ = 2.7V, V- = -2.7V, I

= 1mA

Vv+

Voltage on V+ pin

X9430

+4.5

+5.5

X9430-2.7

+2.7

+5.5

Vv-

Voltage on V- pin

X9430

-5.5

-4.5

X9430-2.7

-5.5

-2.7

TERM

Voltage on any R

or R

V-

V+

Noise

-100

dBv

Ref: 1V

Resolution

(4)

1.6

Absolute linearity

(1)

-1

(3)

w(n)(actual)

- V

w(n)(expected)

Relative linearity

(2)

-0.2

+0.2

(3)

w(n + 1)

- [V

w(n) + MI

]

Temperature coefficient of R

TOTAL

300

ppm/°C

Ratiometric temperature coefficient

±20

ppm/°C

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Commercial

+70

Industrial

-40

+85

Device

Supply Voltage (V

) Limits

X9430

10%

X9430-2.7

2.7V to 5.5V

X9430

FN8198.0

March 11, 2005

AMPLIFIER ELECTRICAL CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)

V+ and V- (±5V to ±3V) are the amplifier power supplies. The amplifiers are specified with dual power supplies. V

and V

are the logic supplies. All ratings are over the temperature range for the Industrial (-40 to + 85°C) and

Commercial (0 to 70°C) versions of the part unless specified differently.

Symbol

Parameter

Condition

Industrial

Commercial

Unit

Min.

Typ. Max. Min. Typ. Max.

Input Offset Voltage

V+/V-

3V to

VOS

Input Offset Voltage Temp.

Coefficient

V+/V-

3V to

-10

µV/°C

Input bias current

V+/V-

3V to

Input offset current

V+/V-

3V to

CMRR

Common mode
rejection ratio

= -1V to +1V

PSRR

Power supply
rejection ratio

V+/V-

3V to

Input common mode

voltage range

= 25°C

V-

V+

V-

V+

Large signal voltage gain

= -1V to + 1V

V/mV

Output voltage swing

V-
V+

+0.1

-.15

+0.1

-.15

V
V

Output current

V+/V- =

5.5V

V+/V- =

3.3V

50
30

mA
mA

Supply current

V+/V- =

5.0V

V+/V- =

3.0V

1.5

Gain-bandwidth prod

= 100k, C

= 50pf

1.0

MHz

Slew rate

= 100k, C

= 50pf

1.5

V/µsec

Phase margin

= 100k,

= 50pf

Deg.

X9430

FN8198.0

March 11, 2005

POTENTIOMETER D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)

ENDURANCE AND DATA RETENTION

CAPACITANCE

POWER-UP TIMING

A.C. TEST CONDITIONS

Notes: (5) This parameter is periodically sampled and not 100%

tested.

(6) t

PUR

and t

PUW

are the delays required from the time the

third (last) power supply (V

, V+ or V-) is stable until

the specific instruction can be issued. These parameters
are periodically sampled and not 100% tested.

(7) The power-up order of power supplies are V

, V+

and V-.

SPICE Macro Model

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Unit

CC1

supply current (active)

400

µA

SCK

= 2MHz, SO = Open,

Other Inputs = V

CC2

supply current (nonvolatile

write)

SCK

= 2MHz, SO = Open,

Other Inputs = V

current (standby)

µA

SCK = SI = V

, Addr. = V

Input leakage current

µA

= V

to V

Output leakage current

µA

OUT

= V

to V

Input HIGH voltage

x 0.7

+ 0.5

Input LOW voltage

-0.5

x 0.1

Output LOW voltage

0.4

= 3mA

Parameter

Min.

Unit

Minimum endurance

100,000

Data changes per register

Data retention

100

years

Symbol

Test

Typ.

Max.

Unit

Test Conditions

OUT

(5)

Output capacitance (SO)

OUT

= 0V

(5)

Input capacitance (A0, A1, SI, WP, HOLD and SCK)

= 0V

| C

Potentiometer capacitance

10/10/2

Symbol

Parameter Max.

Unit

PUR

(6)

Power-up to initiation of read operation

PUW

(6)

Power-up to initiation of write operation

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x 0.5

TOTAL

X9430

FN8198.0

March 11, 2005

AC TIMING

HIGH-VOLTAGE WRITE CYCLE TIMING

RAMP (sample tested)

Symbol

Parameter

Min.

Max.

Unit

SCK

SSI/SPI clock frequency

2.0

MHz

CYC

SSI/SPI clock cycle time

500

SSI/SPI clock high time

200

SSI/SPI clock low time

200

LEAD

Lead time

250

LAG

Lag time

250

SI, SCK, HOLD and CS input setup time

SI, SCK, HOLD and CS input hold time

SI, SCK, HOLD and CS input rise time

µs

SI, SCK, HOLD and CS input fall time

µs

DIS

SO output disable time

500

SO output valid time

200

SO output hold time

SO output rise time

SO output fall time

HOLD

HOLD time

400

HSU

HOLD setup time

100

HOLD hold time

100

HOLD low to output in high Z

100

HOLD high to output in low Z

100

Noise suppression time constant at SI, SCK, HOLD and CS inputs

CS deselect time

µs

WPASU

WP, A0 and A1 setup time

WPAH

WP, A0 and A1 hold time

Symbol

Parameter

Typ.

Max.

Unit

High-voltage write cycle time (store instructions)

Symbol

Parameter

Typ.

Max.

Unit

trV

power-up rate

V/ms

X9430

FN8198.0

March 11, 2005

DCP Timing

SYMBOL TABLE

TIMING DIAGRAMS

Input Timing

Symbol

Parameter

Min. Max. Unit

WRPO

Wiper response time after the third (last) power supply is stable

µs

WRL

Wiper response time after instruction issued (all load instructions)

µs

WRID

Wiper response time from an active SCL/SCK edge (increment/decrement instruction)

µs

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from Low to

High

Will change

from Low to

High

May change

from High to

Low

Will change

from High to

Low

Don't Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

...

SCK

MSB

LSB

High Impedance

LEAD

LAG

CYC

...

X9430

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8198.0

March 11, 2005

Ordering Information

Device

Limits

Blank = 5V ±10%
-2.7 = 2.7 to 5.5V

Temperature Range
Blank = Commercial = 0 to +70°C
I = Industrial = -40 to +85°C

Package
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP

Potentiometer Organization

Pot 0

Pot 1

W =

10k

X9430

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