FN8199.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

PRELIMINARY

X9438

Programmable Analog

Dual Digitally Controlled Potentiometer

(XDCPTM) with Operational Amplifier

FEATURES

· Two CMOS voltage operational amplifiers
· Two digitally controlled potentiometers
· Can be combined or used separately
· Amplifiers:

--Low voltage operation
--V+/V- = ±2.7V to ±5.5V
--Rail-to-rail CMOS performance
--1MHz gain bandwidth product

· Digitally controlled potentiometers

--Dual 64 tap potentiometers
--R

total

= 10k

--2-wire serial interface
--V

= 2.7V to 5.5V

DESCRIPTION

The X9438 is a monolithic CMOS IC that incorporates
two operational amplifiers and two nonvolatile digitally
controlled potentiometers. The amplifiers are CMOS
differential input voltage operational amplifiers with
near rail-to-rail outputs. All pins for the two amplifiers
are brought out of the package to allow combining
them with the potentiometers, or using them as com-
plete stand-alone amplifiers.

The digitally controlled potentiometers consist of a
series string of 63 polycrystalline resistors that behave
as standard integrated circuit resistors. The two-wire
serial port, common to both pots, allows the user to
program the connection of the wiper output to any of
the resistor nodes in the series string. The wiper posi-
tion is saved in the on board E2 memory to allow for
nonvolatile restoration of the wiper position.

A wide variety of applications can be implemented
using the potentiometers and the amplifiers. A typical
application is to implement the amplifier as a wiper
buffer in circuits that use the potentiometer as a voltage
reference. The potentiometer can also be combined
with the amplifier yielding a digitally programmable gain
amplifier or programmable current source.

BLOCK DIAGRAM

OUT1

Control and

SCL

SDA

A3
A2

Memory

NI0

V+

V-

OUT0

NI1

INV1

INV0

WCR1

WCR0

Data Sheet

March 11, 2005

NOT RE

COMME

NDED FO

R NEW D

ESIGNS

NO REC

OMMEN

DED RE

PLACEM

ENT

contact

our Tec

hnical S

upport C

enter at

1-888-IN

TERSIL

or www.

intersil.c

om/tsc

FN8199.0

March 11, 2005

PIN DESCRIPTIONS

Host Interface Pins

Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9438.

Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor.

Device Address (A

- A

)

The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9438. A maximum of 16 devices may share the
same 2-wire serial bus.

Potentiometer Pins

(1)

- R

), R

- R

)

The R

and R

inputs are equivalent to the terminal con-

nections on either end of a mechanical potentiometer.

- R

)

The wiper output is equivalent to the wiper output of a
mechanical potentiometer.

Amplifier and Device Pins

Amplifier Input Voltage V

(0,1) and V

INV

(0,1)

and V

INV

are inputs to the noninverting (+) and

inverting (-) inputs of the operational amplifiers.

Amplifier Output Voltage V

OUT

(0,1)

OUT

is the voltage output pin of the operational

amplifier.

Hardware Write Protect Input WP
The WP pin, when low, prevents non-volatile writes to
the wiper counter registers.

Note:

(1) Alternate designations for R

, R

are V

, V

Analog Supplies V+, V-
The analog supplies V+, V- are the supply voltages for
the XDCP analog section and the operational amplifiers.

System Supply V

and Ground V

The system supply V

and its reference V

is used

to bias the interface and control circuits.

PIN CONFIGURATION

PIN NAMES

Symbol

Description

SCL

Serial Clock

SDA

Serial Data

A0 - A3

Device Address

- R

Potentiometers (terminal equivalent)

- R

Potentiometers (wiper equivalent)

NI(0,1)

INV(0,1)

Amplifier Input Voltages

OUT0,

OUT1

Amplifier Outputs

Hardware Write Protection

V+,V-

Analog and Voltage Amplifier Supplies

System/Digital Supply Voltage

System Ground

No Connection

SDA

1
2
3
4
5
6
7
8
9
10

24
23
22
21
20
19
18
17
16
15

V+
V

OUT0

NI0

INV0

A0
NC
A

SCL
V

INV1

NI1

SOIC

X9438

OUT1

V-

INV0

NI0

SCL

1
2
3
4
5
6
7
8
9
10

24
23
22
21
20
19
18
17
16
15

TSSOP

X9438

V+

OUT0

OUT1

NI1

INV1

SDA

X9438

FN8199.0

March 11, 2005

PRINCIPLES OF OPERATION

The X9438 is an integrated microcircuit incorporating
two resistor arrays, two operational amplifiers and
their associated registers and counters; and the serial
interface logic providing direct communication
between the host and the digitally controlled potenti-
ometers and operational amplifiers.

Serial Interface
The X9438 supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers and pro-
vide the clock for both transmit and receive operations.
Therefore, the X9438 will be considered a slave
device in all applications.

Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (t

LOW

). SDA state changes during

SCL HIGH are reserved for indicating start and stop
conditions.

Start Condition
All commands to the X9438 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t

HIGH

). The X9438 continuously

monitors the SDA and SCL lines for the start condition
and will not respond to any command until this condi-
tion is met.

Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA while
SCL is HIGH.

Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and dur-
ing this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits
of data.

The X9438 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the com-
mand byte. If the command is followed by a data byte
the X9438 will respond with a final acknowledge.

Operational Amplifier
The voltage operational amplifiers are CMOS rail-to-
rail output general purpose amplifiers. They are
designed to operate from dual (±) power supplies. The
amplifiers may be configured like any standard ampli-
fier. All pins are externally available to allow connec-
tions with the potentiometers or as stand alone
amplifiers.

Potentiometer/Array Description
The X9438 is comprised of two resistor arrays and two
operational amplifiers. Each array contains 63 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RH and RL
inputs).

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R

) output. Within each individual array only one

switch may be turned on at a time. These switches are
controlled by a volatile wiper counter register (WCR).
The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches.

The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.

INSTRUCTIONS AND PROGRAMMING

Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most signifi-
cant four bits of the slave address are the device type
identifier (refer to Figure 1). For the X9438 this is fixed
as 0101[B].

Figure 1. Address/Identification Byte Format

Device Type

Identifier

Device Address

X9438

FN8199.0

March 11, 2005

The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A

- A

inputs. The X9438 compares

the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9438 to respond with an acknowledge. The
A

- A

inputs can be actively driven by CMOS input

signals or tied to V

or V

Acknowledge Polling
The disabling of the inputs, during the internal non-vol-
atile write operation, can be used to take advantage of
the typical 5ms EEPROM write cycle time. Once the
stop condition is issued to indicate the end of the non-
volatile write command the X9438 initiates the internal
write cycle. ACK polling (Flow 1) can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9438 is
still busy with the write operation no ACK will be
returned. If the X9438 has completed the write opera-
tion an ACK will be returned and the master can then
proceed with the next operation.

Flow 1. ACK Polling Sequence

Instruction Structure
The byte following the address contains the instruction
and register pointer information. The four most signifi-
cant bits are the instruction. The next four bits point to
one of the two pots and when applicable they point to
one of the four WCRs associated data registers. The
format is shown below in Figure 2.

Figure 2. Instruction Byte Format

The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the two regis-
ters that is to be acted upon when a register oriented
instruction is issued. The last bit (P0) selects which
one of the two potentiometers is to be affected by the
instruction.

Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is illus-
trated in Figure 3. These two-byte instructions
exchange data between the wiper counter register and
one of the data registers. A transfer from a data regis-
ter to a wiper counter register is essentially a write to a
static RAM. The response of the wiper to this action
will be delayed t

WRL

. A transfer from the wiper counter

to complete. The transfer can occur between one

of the two potentiometers and one of its associated
registers; or it may occur globally, wherein the transfer
occurs between all of the potentiometers and one of
their associated registers.

Four instructions require a three-byte sequence to
complete. The basic sequence is illustrated in Figure
4. These instructions transfer data between the host
and the X9438; either between the host and one of the
data registers or directly between the host and the
wiper counter and analog control registers. These
instructions are: 1) Read Wiper Counter Register or
read the current wiper position of the selected pot, 2)
Write Wiper Counter Register, i.e. change current
wiper position of the selected pot; 3) Read Data Regis-
ter, read the contents of the selected non-volatile regis-
ter; 4) Write Data Register, write a new value to the
selected data register. The bit structures of the instruc-
tions are shown in Figure 6.

Nonvolatile Write

Command Completed

Enter Ack Polling

Issue

START

Issue Slave

Address

ACK

Returned?

Further

Operation?

Issue

Instruction

Issue STOP

Yes

Prooceed

Issue STOP

Prooceed

WCR Select

Select

Instructions

X9438

FN8199.0

March 11, 2005

Figure 3. Two-Byte Command Sequence

Figure 4. Three-Byte Command Sequence

The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9438 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse

HIGH

) while SDA is HIGH, the selected wiper will

move one resistor segment towards the V

terminal.

Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the V

terminal. A detailed illustration of the

sequence for this operation is shown in Figure 5.

Figure 5. Increment/Decrement Command Sequence

A3 A2 A1 A0

R1 R0 0

SCL

SDA

A3 A2 A1 A0 A

I1 I0

P0 R1 R0 A

SCL

SDA

D5 D4 D3 D2 D1 D0

A3 A2 A1 A0

P1 P0 R1 R0 A

SCL

SDA

X9438

FN8199.0

March 11, 2005

Figure 6. Instruction Set

Read Wiper Counter Register (WCR)
Read the contents of the Wiper Counter Register P

P0: 0 - WCR0, 1 - WCR1

Write Wiper Counter Register (WCR)
Write new value to the Wiper Counter Register P

P0: 0 - WCR0, 1 - WCR1

Read Data Register (DR)
Read the contents of the Register pointed to by P

and R

- R

R1 R0:

00 - R0,

10 - R1

01 - R2,

11 - R3

Write Data Register (DR)
Write new value to the Register pointed to by P

and R

- R

Definitions:
SACK - Slave acknowledge, MACK - Master acknowledge, I/D - Increment/Decrement (1/0), R - Register,
P - Potentiometer

S
T
A

device type

identifier

device

addresses

S
A

instruction

opcode

WCR

addresses

S
A
C
K

(sent by slave on SDA)

A
C
K

S
T

0 1 0 1 A

1 0 0 1 0 0 0 P

0 0 D

S
T
A

device type

identifier

device

addresses

S
A

instruction

opcode

WCR

addresses

S
A
C
K

(sent by master on SDA)

S
A
C
K

S
T

0 1 0 1 A

1 0 1 0 0 0 0 P

0 0 D

A
R

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

WCR/DR

addresses

S
A
C
K

(sent by master on SDA)

S
T

0 1 0 1 A

1 0 1 1 R

0 0

0 0 D

A
R

device type

identifier

device

addresses

S
A

instruction

opcode

WCR/DR

addresses

S
A

(sent by master on SDA)

S
A

S
T

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 A

1 1 0 0 R

0 0 D

X9438

FN8199.0

March 11, 2005

Figure 6. Instruction Set (continued)

Transfer Data Register to Wiper Counter Register
Transfer the contents of the Register pointed to by R

- R

to the WCR pointed to by P

Transfer Wiper Counter Register to Data Register
Transfer the contents of the WCR pointed to by P

to the Register pointed to by R

- R

Global Transfer Data Register to Wiper Counter Register
Transfer the contents of all four Data Registers pointed to by R

- R

to their respective WCR.

Global Transfer Wiper Counter Register to Data Register
Transfer the contents of all WCRs to their respective data Registers pointed to by R

- R

Increment/Decrement Wiper Counter Register
Enable Increment/decrement of the WCR pointed to by P

P0: 0 or 1 only.

S
T
A
R
T

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

WCR/DR

addresses

S
A
C
K

0 1 0 1 A

1 1 0 1 R

0 0

S
T
A

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

WCR/DR

addresses

S
A
C
K

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 A

1 1 1 0 R

0 0

S
T
A
R
T

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

addresses

S
A
C
K

0 1 0 1 A

0 0 0 1 R

0 0 0

S
T
A
R
T

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

addresses

S
A
C
K

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 A

1 0 0 0 R

0 0 0

S
T
A

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

WCR

addresses

S
A
C
K

increment/decrement

(sent by master on SDA)

0 1 0 1 A

0 0 1 0 0 0 0 P

D .

. I/

X9438

FN8199.0

March 11, 2005

REGISTER OPERATION

Both digitally controlled potentiometers share the
serial interface and share a common architecture.
Each potentiometer is associated with a Wiper
Counter Register (WCR), and four Data Registers.
Figure 7 illustrates the control, registers, and system
features of the device.

Figure 7. System Block Diagram

Wiper Counter (WCR) and Analog Control Registers
(ACR)
The X9438 contains two wiper counter registers, one
for each XDCP. The wiper counter register is equiva-
lent to a serial-in, parallel-out counter, with its outputs
decoded to select one of sixty-four switches along its
resistor array. The contents of the wiper counter regis-
ter can be altered in four ways: it may be written
directly by the host via the write WCR Instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated data registers
(DR) via the XFR data register instruction (parallel
load); it can be modified one step at a time by the
increment/decrement instruction (WCR only). Finally,
it is loaded with the contents of its data register zero
(R0) upon power-up.

The wiper counter register is a volatile register; that is,
its contents are lost when the X9438 is powered-down.
Although the registers are automatically loaded with the
value in R0 upon power-up, it should be noted this may
be different from the value present at power-down.

Data Registers (DR)
Each potentiometer has four non-volatile data registers
(DR). These can be read or written directly by the host
and data can be transferred between any of the four
data registers and the WCR. It should be noted all oper-
ations changing data in one of these registers is a non-
volatile operation and will take a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could store sys-
tem parameters or user preference data.

REGISTER DESCRIPTIONS AND MEMORY MAP

Memory Map

Wiper Counter Register (WCR)

WP0-WP5 identify wiper position.

Data Registers (DR, R0 - R3)

OUT (0,1)

(DR0-DR3)

0,1

Interface

and

Control

Circuitry

SCL

SDA

H (0,1)

L (0,1)

W (0,1)

NI (0,1)

WCR

0,1

INV (0,1)

WCRO

WCR1

DR0

DR1

DR2

DR3

WP5 WP4 WP3 WP2 WP1 WP0

(volatile)

(LSB)

Wiper Position or User Data

(Nonvolatile)

X9438

FN8199.0

March 11, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SDA, SCL or any address

input with respect to V

......................... -1V to +7V

Voltage on any V+ (referenced to V

) ................

Voltage on any V- (referenced to V

) .................. -7V

(V+) - (V-) ............................................................. 10V
Any R

....................................................................V+

Any R

......................................................................V-

Lead temperature (soldering, 10 seconds)........ 300°C

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-

eter. It is a measure of the error in step size.

(3) MI = RTOT/63 or (R

- R

)/63, single pot ( = LSB)

(4) Individual array resolutions

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Unit

TOTAL

End to end resistance

-20

+20

Power rating

C, each pot

Wiper current

-3

Wiper resistance

100

= 5V, Wiper Current = 3mA

100

250

= 2.7, Wiper Current = 1mA

Vv+

Voltage on V+ pin

X9438

+4.5

+5.5

X9438-2.7

+2.7

+5.5

Vv-

Voltage on V- pin

X9438

-5.5

-4.5

X9438-2.7

-5.5

-2.7

TERM

Voltage on any R

or R

V-

V+

Noise

-100

dBv

Ref: 1V

Resolution

(4)

1.6

Absolute linearity

(1)

-1

(3)

w(n)(actual)

- V

w(n)(expected)

Relative linearity

(2)

-0.2

+0.2

(3)

w(n + 1)

- [V

w(n) + MI

]

Temperature coefficient of R

TOTAL

300

ppm/

°C

Ratiometric temperature coefficient

±20

ppm/°C

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Commercial

°C

+70

°C

Industrial

-40

°C

+85

°C

Device

Supply Voltage (V

) Limits

X9438

10%

X9438-2.7

2.7V to 5.5V

X9438

FN8199.0

March 11, 2005

AMPLIFIER ELECTRICAL CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)

V+ and V- (

5V to

3V) are the amplifier power supplies. The amplifiers are specified with dual power supplies. V

and V

is the logic supply. All ratings are over the temperature range for the Industrial (-40 to + 85°C) and Commercial (0 to 70°C)
versions of the part unless specified differently.

SYSTEM/DIGITAL D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)

Symbol

Parameter

Condition

Industrial

Commercial

Unit

Min. Typ. Max. Min. Typ. Max.

Input offset voltage

V+/V-

3V to

VOS

Input offset voltage temp.

coefficient

V+/V-

3V to

-10

µV/°C

Input bias current

V+/V-

3V to

Input offset current

V+/V-

3V to

CMRR

Common mode
rejection ratio

= -1V to +1V

PSRR

Power supply
rejection ratio

V+/V-

3V to

Input common mode voltage

range

= 25°C

V-

V+

V-

V+

Large signal voltage gain

= -1V to + 1V

V/mV

Output voltage swing

V-
V+

+0.1

-.15

+0.1

-.15

V
V

Output current

V+/V- =

5.5V

V+/V- =

3.3V

50
30

mA
mA

Supply current

V+/V- =

5.0V

V+/V- =

3.0V

1.5

Gain-bandwidth prod

= 100k, C

= 50pf

1.0

MHz

Slew rate

= 100k, C

= 50pf

1.5

V/µsec

Phase margin

= 100k, C

= 50pf

Deg.

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Unit

supply current (active)

400

µA

SCL

= 400kHz, SDA = Open,

Other Inputs = V

current (standby)

µA

SCL = SDA = V

, Addr. = V

Input leakage current

µA

= V

to V

Output leakage current

µA

OUT

= V

to V

Input HIGH voltage

x 0.7

+ 0.5

Input LOW voltage

-0.5

x 0.1

Output LOW voltage

0.4

= 3mA

X9438

FN8199.0

March 11, 2005

ENDURANCE AND DATA RETENTION

CAPACITANCE

POWER-UP TIMING AND SEQUENCE

A.C. TEST CONDITIONS

Note:

(1) Applicable to recall and power consumption applications

EQUIVALENT A.C. LOAD CIRCUIT

SPICE Macro Model

Parameter

Min.

Unit

Minimum endurance

100,000

Data changes per bit per register

Data retention

100

Years

Symbol

Test

Typical

Unit

Test Conditions

I/O

Input/output capacitance (SDA)

I/O

= 0V

Input capacitance (A0, A1, A2, A3, and SCL)

= 0V

| C

Potentiometer capacitance

10/10/25

See SPICE Model

Power-up sequence

(1)

: (1) V

(2) V+ and V-

Power-down sequence: no limitation

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x 0.5

1533

100pF

SDA Output

2.7V

100pF

TOTAL

X9438

FN8199.0

March 11, 2005

AC TIMING

Note:

(4) V

= 5V/2.7V

HIGH-VOLTAGE WRITE CYCLE TIMING

DCP TIMING

RAMP (sample tester)

Symbol

Parameter

Min.

Max.

Unit

SCL

Clock frequency

400

kHz

CYC

Clock cycle time

2500

HIGH

Clock high time

600

LOW

Clock low time

1300

SU:STA

Start setup time

600

HD:STA

Start hold time

600

SU:STO

Stop setup time

600

SU:DAT

SDA data input setup time

100

HD:DAT

(4)

SDA data input hold time

0/30

SCL and SDA rise time

300

SCL and SDA fall time

300

SCL low to SDA data output valid time

100

900

SDA data output hold time

Noise suppression time constant at SCL and SDA inputs

BUF

Bus free time (Prior to Any Transmission)

1300

SU:WPA

WP, A0, A1, A2 and A3 setup time

HD:WPA

WP, A0, A1, A2 and A3 hold time

Symbol

Parameter

Typ.

Max.

Unit

High-voltage write cycle time (store instructions)

Symbol

Parameter

Min.

Max.

Unit

WRL

Wiper response time after instruction issued (All load instructions)

µs

Symbol

Parameter

Typ.

Max.

Unit

trV

Power-up rate

V/ms

X9438

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8199.0

March 11, 2005

Ordering Information

Device

Limits

Blank = 5V ±10%
-2.7 = 2.7 to 5.5V

Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C

Package
P24 = 24-Lead Plastic DIP
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP

Potentiometer Organization

Pot 0

Pot 1

W =

10k

Y =

2.5k

X9438

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