FN8200.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9440

Mixed Signal with SPI Interface

Dual Digitally Controlled Potentiometer

(XDCPTM) & Voltage Comparator

FEATURES

· Two digitally controlled potentiometers and two

voltage comparators in one package

· SPI serial interface
· Register oriented format

--Direct read/write wiper position
--Store as many as four positions per pot

· Fast response comparator
· Enable, latch, or shutdown comparator outputs

through the ACR

· Auto-recall of WCR and ACR data from R0
· Hardware write protection, WP
· Separate analog and digital/system supplies
· Direct write cell

--Endurance100,000 data changes per bit per

register

--Register data retention100 years

· 16-bytes of EEPROM memory
· Power saving feature and low noise
· Two 10k

or two 2.5k

potentiometers

· Resolution: 64 taps each pot
· 24-lead TSSOP and 24-Lead SOIC packages

DESCRIPTION

The X9440 integrates two non volatile digitally con-
trolled potentiometers (XDCP) and two voltage com-
parators on a CMOS monolithic microcircuit.

The X9440 contains two resistor arrays, each com-
posed of 63 resistive elements. Between each ele-
ment and at either end are tap points accessible to the
wiper elements. The position of the wiper element on
the array is controlled by the user through the SPI
serial bus interface.

Each potentiometer has an associated voltage com-
parator. The comparator compares the external input
voltage V

with the wiper voltage V

and sets the out-

put voltage level to a logic high or low.

Each resistor array and comparator has associated
with it a wiper counter register (WCR), analog control
register (ACR), and eight 6 bit data registers that can
be directly written and read by the user. The contents
of the wiper counter register controls the position of
the wiper on the resistor array. The contents of the
analog control register controls the comparator and its
output. The potentiometer is programmed with a SPI
serial interface.

BLOCK DIAGRAM

OUT (0,1)

-R

)

0,1

Interface

and

Control

Circuitry

SCK

HOLD

H (0,1)

L (0,1)

W (0,1)

NI (0,1)

WCR

0,1

-R

)

0,1

ACR

0,1

Data Sheet

March 28, 2005

FN8200.0

March 28, 2005

PIN DESCRIPTIONS

Host Interface Pins

Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.

Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.

Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9440.

Chip Select (CS)
When CS is HIGH, the X9440 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9440, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.

Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume com-
munication, HOLD is brought HIGH, again while SCK
is LOW. If the pause feature is not used, HOLD should
be held HIGH at all times.

Device Address (A

-A

)

The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9440. A maximum of 4 devices may share the
same SPI serial bus.

Potentiometer Pins
V

-V

), V

-V

)

The V

and V

inputs are equivalent to the terminal con-

nections on either end of a mechanical potentiometer.

-V

)

The wiper output V

is equivalent to the wiper output

of a mechanical potentiometer and is connected to the
inverting input of the voltage comparator.

Comparator and Device Pins

Voltage Input V

NI0

, V

NI1

NI0

and V

NI1

are the input voltages to the plus (non-

inverting) inputs of the two comparators.

Buffered Voltage Outputs V

OUT0

, V

OUT1

OUT0

and V

OUT1

are the buffered voltage comparator

outputs controlled by bits in the volatile analog control
register.

Hardware Write Protect Input WP
The WP pin when low prevents non volatile writes to
the wiper counter and analog control registers.

Analog Supplies V+, V-
The Analog Supplies V+, V- are the supply voltages for
the XDCP analog section and the voltage comparators.

System Supply V

and Ground V

The system supply, V

and its reference V

is used

to bias the interface and control circuits.

X9440

FN8200.0

March 28, 2005

PIN CONFIGURATION

PIN NAMES

PRINCIPLES OF OPERATION

The X9440 is a highly integrated microcircuit incorpo-
rating two resistor arrays, two voltage comparators
and their associated registers and counters; and the
serial interface logic providing direct communication
between the host and the digitally-controlled potenti-
ometers and voltage comparators.

Serial Interface
The X9440 supports the SPI interface hardware con-
ventions. The device is accessed via the SI input with
data clocked in on the rising SCK. CS must be LOW
and the HOLD and WP pins must be HIGH during the
entire operation.

The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.

Array Description
The X9440 is comprised of two resistor arrays and two
voltage comparators. Each array contains 63 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (V

and V

inputs).

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V

) output. Within each individual array only one

switch may be turned on at a time. These switches are
controlled by a volatile wiper counter register (WCR).
The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches.

The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.

Voltage Comparator
The comparator compares the wiper voltage V

with

the external input voltage V

. The comparator and its

logic level output are controlled by the shutdown,
latch, and enable bits of the analog control register
(ACR). Enable connects the comparator output to the
V

OUT

pin, Latch memorizes the output logic state, and

shutdown removes the analog section supply voltages
to save power. The analog control register (ACR) is
programmed using the SPI serial interface.

The ACR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the ACR. These data registers and
the ACR may be read and written by the host system.

Symbol

Description

SCK

Serial Clock

S1, SO

Serial Data

A0-A1

Device Address

-V

Potentiometers (terminal equivalent)

Potentiometers (wiper equivalent)

NI0

, V

NI1

Comparator Input Voltages

OUT0,

OUT1

Buffered Comparator Outputs

Hardware Write Protection

V+,V-

Analog and Voltage Comparator

Supplies

System Supply Voltage

System Ground

No Connection

1
2
3
4
5
6
7
8
9
10

24
23
22
21
20
19
18
17
16
15

V+
V

OUT0

NI0

NC
A0
SO
HOLD
SCK
NC
V

NI1

SOIC

X9440

14
13

11
12

OUT1

V-

1
2
3
4
5
6
7
8
9

24
23
22
21
20
19
18
17
16
15

TSSOP

X9440

14
13

11
12

V-

V+

OUT1

OUT0

SCK

HOLD

NI1

NI0

X9440

FN8200.0

March 28, 2005

REGISTERS

Both digitally-controlled potentiometers and voltage com-
parators share the serial interface and share a common
architecture. Each potentiometer and voltage comparator
is associated with wiper counter and analog control reg-
isters and eight data registers. A detailed discussion of
the register organization and array operation follows.

Wiper Counter (WCR) and Analog Control
Registers (ACR)
The X9440 contains two wiper counter registers: one
for each XDCP potentiometer and two Analog Control
Registers, and one for each of the two voltage com-
parators. The wiper counter register is equivalent to a
serial-in, parallel-out counter with its outputs decoded
to select one of sixty-four switches along its resistor
array. The contents of the wiper counter register and
analog control register can be altered in four ways: it
may be written directly by the host via the Write WCR
instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated
data registers (DR) via the XFR data register instruc-
tion (parallel load); it can be modified one step at a
time by the increment/ decrement instruction (WCR
only). Finally, it is loaded with the contents of its data
register zero (R0) upon power-up.

The wiper counter and analog control register are vol-
atile registers; that is, their contents are lost when the
X9440 is powered-down. Although the registers are
automatically loaded with the value in R0 upon power-
up, it should be noted this may be different from the
value present at power-down.

Programming the ACR is similar to the WCR. How-
ever, the 6 bits in the WCR positions the wiper in the
resistor array while 3 bits in the ACR control the com-
parator and its output.

Data Registers (DR)
Each potentiometer and each voltage comparator has
four non volatile data registers (DR). These can be
read or written directly by the host and data can be
transferred between any of the four data registers and
the WCR or ACR. It should be noted all operations
changing data in one of these registers is a non vola-
tile operation and will take a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer or comparator, these reg-
isters can be used as regular memory locations that
could store system parameters or user preference data.

Figure 1. Detailed Potentiometer Block Diagram

Serial Data Path
From Interface

Circuitry

Serial

Bus

Input

Parallel

Bus

Input

Counter

Inc/Dec

Logic

UP/DN

CLK

Modified SCK

UP/DN

If WC = 00[H] V

= V

If WC = 3F[H] V

= V

Wiper

(One of Two Arrays)

(WCR)

X9440

FN8200.0

March 28, 2005

REGISTER BIT DESCRIPTIONS

Wiper Counter Register (WCR)

WP0-WP5 identify wiper position.

Analog Control Register (ACR)

Shutdown
"1"

indicates power is connected to the voltage
comparator.

"0"

indicates power is not connected to the voltage
comparator.

Enable
"1"

indicates the output buffer of the voltage
comparator is enabled.

"0"

indicates the output buffer of the voltage
comparator is disabled.

Latch
"1"

indicates the output of the voltage comparator is
memorized or latched.

"0"

indicates the output of the voltage comparator is
not latched.

Userbits--available for user applications

Data Registers (DR, R

-R

)

{Refer to Memory Map, Figure 9}

INSTRUCTIONS AND PROGRAMMING

Identification (ID) Byte
The first byte sent to the X9440 from the host, follow-
ing a CS going HIGH to LOW, is called the Identifica-
tion byte. The most significant four bits of the slave
address are a device type identifier, for the X9440 this
is fixed as 0101[B] (refer to Figure 2).

The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A

-A

input pins.

The X9440 compares the serial data stream with the
address input state; a successful compare of both
address bits is required for the X9440 to successfully
continue the command sequence. The A

-A

inputs

can be actively driven by CMOS input signals or tied to
V

or V

The remaining two bits in the slave byte must be set to 0.

Figure 2. Identification Byte Format

Instruction Byte
The byte following the address contains the instruction
and register pointer information. The four most signifi-
cant bits are the instruction. The next four bits point to
one of the two pots or two voltage comparators and
when applicable they point to one of four associated
registers. The format is shown below in Figure 3.

Figure 3. Instruction Byte Format

The four high order bits of the instruction byte specify
the operation. The next two bits (R

and R

) select one

of the four data registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits (P

and P

) selects which one of the four potenti-

ometers is to be affected by the instruction.

The four high order bits define the instruction. The next
two bits (R

and R

) select one of the four data registers

that is to be acted upon when a register oriented instruc-
tion is issued. The last two bits (P

and P

) select which

one of the two potentiometers or which one of the two
voltage comparators is to be affected by the instruction.

WP5 WP4 WP3 WP2 WP1 WP0

(volatile)

(LSB)

0 0

User-

bit5

User-

bit4

User-

bit3

Latch Enable

Shut-

down

(volatile)

(LSB)

Wiper Position or Analog Control Data or User Data

(Nonvolatile)

Device Type

Identifier

Device Address

Pot Select

Select

Instructions

X9440

FN8200.0

March 28, 2005

Four of the ten instructions end with the transmission
of the instruction byte. The basic sequence is illus-
trated in Figure 4. These two-byte instructions
exchange data between the wiper counter register or
analog control register and one of the data registers. A
transfer from a data register to a wiper counter register
or analog control register is essentially a write to a
static RAM. The response of the wiper to this action
will be delayed t

WRL

. A transfer from the wiper counter

to complete. The transfer can occur between one

of the two potentiometers or one of the two voltage
comparators and one of its associated registers; or it
may occur globally, wherein the transfer occurs
between both of the potentiometers and voltage com-
parators and one of their associated registers.

Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9440; either between the host and
one of the data registers or directly between the host
and the wiper counter and analog control registers.
These instructions are: Read Wiper Counter Register
or Analog Control Register, read the current wiper
position of the selected pot or the comparator control
bits, Write Wiper Counter Register or Analog Control
Register, i.e. change current wiper position of the
selected pot or control the voltage comparator; Read
Data Register, read the contents of the selected non
volatile register; Write Data Register, write a new value
to the selected data register. The bit structures of the
instructions are shown in Figure 9.

The sequences of the three byte operations are shown
in Figure 5 and Figure 6.

The bit structures of the instructions and the descrip-
tion of the instructions are shown in Figure 10.

Figure 4. Two-Byte Command Sequence

Figure 5. Three-Byte Command Sequence (Write)

A1 A0

R1 R0 P1 P0

SCK

A1 A0

I1 I0

R1 R0 P1 P0

SCL

D5 D4 D3 D2 D1 D0

X9440

FN8200.0

March 28, 2005

Figure 6. Three-Byte Command Sequence (Read)

Figure 7. Increment/Decrement Command Sequence

Increment/Decrement
The final command is Increment/Decrement. It is differ-
ent from the other commands, because it's length is
indeterminate. Once the command is issued, the mas-
ter can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
capability to the host. For each SCK clock pulse (t

HIGH

)

while SI is HIGH, the selected wiper will move one
resistor segment towards the V

terminal. Similarly, for

each SCK clock pulse while SI is LOW, the selected

wiper will move one resistor segment towards the V

terminal. A detailed illustration of the sequence and tim-
ing for this operation are shown in Figure 7 and 8.

Write in Process
The contents of the data registers are saved to nonvol-
atile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write opera-
tion can be monitored by a write in process bit (WIP).
The WIP bit is read with a read status command.

Figure 8. Increment/Decrement Timing Limits

A1 A0

I1 I0

R1 R0 P1 P0

SCL

D5 D4 D3 D2 D1 D0

Don't Care

A1 A0

0 P1 P0

SCK

INC/DEC CMD Issued

Voltage Out

WRID

X9440

FN8200.0

March 28, 2005

Figure 9. Memory Map

Figure 10. Instruction Set

Read Wiper Counter Register (WCR) or Analog Control Register (ACR)
Read the contents of the Wiper Counter Register or Analog Control Register pointed to by P

- P

P1 P0: 00 - WCR0, 01 - WCR1
P1 P0: 10 - ACR0, 11 - ACR1

Write Wiper Counter Register (WCR) or Analog Control Register (ACR)
Write new value to the Wiper Counter Register or Analog Control Register pointed to by P

- P

P1 P0: 00 - WCR0, 01 - WCR1
P1 P0: 10 - ACR0, 11 - ACR1

Read Data Register (DR)
Read the contents of the Register pointed to by P

- P

and R

- R

R1 R0: 00 - R0, 10 - R1

01 - R2,11 - R3

Write Data Register (DR)
Write new value to the Register pointed to by P

- P

and R

- R

WCRO

WCR1

ACR0

ACR1

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR/ACR

addresses

(sent by slave on SDA)

Rising

Edge

0 1 0 1 0 0 A

0 1 0 0 1 0 0

0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR/ACR

addresses

(sent by master on SDA)

Rising

Edge

0 1 0 1 0 0 A

0 1 0 1 0 0 0

0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR/ACR/DR

addresses

(sent by master on SDA)

Rising

Edge

0 1 0 1 0 0 A

0 1 0 1 1

0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR/ACR/DR

addresses

(sent by master on SDA)

Falling

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 0 0 A

0 1 1 0 0

0 0 0

X9440

FN8200.0

March 28, 2005

Transfer Data Register to Wiper Counter Register or Analog Control Register
Transfer the contents of the Register pointed to by R

- R

to the WCR or ACR pointed to by P

- P

Transfer Wiper Counter or Analog Control Register to Data Register
Transfer the contents of the WCR or ACR pointed to by P

- P

to the Register pointed to by R

- R

Global Transfer Data Register to Wiper Counter or Analog Control Register
Transfer the contents of all four Data Registers pointed to by R

- R

to their respective WCR or ACR.

Global Transfer Wiper Counter or Analog Control Register to Data Register
Transfer the contents of all WCRs and ACRs to their respective data Registers pointed to by R

- R

Increment/Decrement Wiper Counter Register
Enable Increment/decrement of the WCR pointed to by P

- P

P1 P0: 00 or 01 only.
I/D: Increment/Decrement, 1/0

Read Status

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR/ACR/DR

addresses

Rising

Edge

0 1 0 1 0 0 A

0 1 1 0 1

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR/ACR/DR

addresses

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 0 0 A

0 1 1 1 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

addresses

Rising

Edge

0 1 0 1 0 0 A

0 0 0 0 1

0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

addresses

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 0 0 A

0 1 0 0 0

0 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

increment/decrement

(sent by master on SDA)

Rising

Edge

0 1 0 1 0 0 A

0 0 0 1 0 0 0

D .

. I/

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

wiper

addresses

Data Byte

(sent by X9440 on SO)

Rising

Edge

0 1 0 1 0 0 A

0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0

X9440

FN8200.0

March 28, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SCK, SCL or any address input

with respect to V

.................................. -1V to +7V

Voltage on V+ (referenced to V

) ........................+7V

Voltage on V- (referenced to V

) ..........................-7V

(V+) - (V-) .............................................................. 12V
Any V

.....................................................................V+

Any V

......................................................................V-

Lead temperature (soldering, 10 seconds)........ 300°C

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-

eter. It is a measure of the error in step size.

(3) MI = RTOT/63 or (V

- V

)/63, single pot

(4) Individual array resolutions.

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Commercial

°C

+70°C

Industrial

-40

°C

+85

°C

Military

-55°C

+125°C

Device

Supply Voltage (V

) Limits

X9440

10%

X9440-2.7

2.7V to 5.5V

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Unit

TOTAL

End to end resistance

+20

Power rating

C, each pot

Wiper current

Wiper resistance

100

= 5V, Wiper Current = 3mA

100

250

= 2.7-5V, Wiper Current = 3mA

Vv+

Voltage on V+ pin

X9440

+4.5

+5.5

X9440-2.7

+2.7

+5.5

Vv-

Voltage on V- pin

X9440

-5.5

-4.5

X9440-2.7

-5.5

-2.7

TERM

Voltage on any V

or V

V-

V+

Noise

-120

dBV

Ref: 1kHz

Resolution

(4)

1.6

Absolute linearity

(1)

-1

(3)

w(n)(actual)

- V

w(n)(expected)

Relative linearity

(2)

-0.2

+0.2

(3)

w(n + 1

- [V

w(n) + MI

]

Temperature coefficient of R

TOTAL

300

ppm/

X9440

FN8200.0

March 28, 2005

COMPARATOR ELECTRICAL CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)

Notes: (1) 100mV step with 100mV overdrive, ZL = 10k

|| 15pF, 10-90% risetime

(2) Time from leading edge of Enable bit to valid V

OUT

Symbol

Parameter

Limits

Unit

Test Conditions

Min.

Typ.

Max.

Input offset voltage

-1
-5

1
5

mV
mV

V+/V- =

Input current

Input voltage range

V-

V+

Response time

200

note 1

Output current

-1

Voltage gain

300

V/mV

PSRR

Power supply rejection ratio

Output voltage range

Input offset voltage drift

µV/°C

Supply current (V+ to V-)

1.2

mA
mA

V+/V- =

Comparator enable time

µs

note 2

Output low voltage

0.4

= 1mA

Output high voltage

-0.8

= 1mA

X9440

FN8200.0

March 28, 2005

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

ENDURANCE AND DATA RETENTION

CAPACITANCE

POWER-UP SEQUENCE

A.C. TEST CONDITIONS

Note:

(1) Applicable to recall and power consumption applica-

tions

EQUIVALENT A.C. LOAD CIRCUIT

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Unit

CC1

supply current (active)

400

µA

SCK

= 2MHz, SO = Open,

Other Inputs = V

CC2

supply current (nonvolatile

write)

SCK

= 2MHz, SO = Open,

Other Inputs = V

current (standby)

µA

SCK = SI = V

, Addr. = V

Input leakage current

µA

= V

to V

Output leakage current

µA

OUT

= V

to V

Input HIGH voltage

x 0.7

+ 0.5

Input LOW voltage

-0.5

x 0.1

Output LOW voltage

0.4

= 3mA

Parameter

Min.

Unit

Minimum endurance

100,000

Data changes per bit per register

Data retention

100

Years

Symbol

Test

Max.

Unit

Test Conditions

I/O

Output capacitance (SO)

OUT

= 0V

Input capacitance (A0, A1, SI, and SCK)

= 0V

, C

Potentiometer capacitance

10/10/25

Power-up Sequence

(1)

: (1) V

(2) V+ and V- {V+

at all times}

Power-down Sequence: no limitation

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x 0.5

1533

100pF

SDA Output

2.7V

100pF

X9440

FN8200.0

March 28, 2005

AC TIMING

HIGH-VOLTAGE WRITE CYCLE TIMING

XDCP TIMING

Symbol

Parameter

Min.

Max.

Unit

SCK

SSI/SPI clock frequency

2.0

MHz

CYC

SSI/SPI clock cycle time

500

SSI/SPI clock high time

200

SSI/SPI clock low time

200

LEAD

Lead time

250

LAG

Lag time

250

SI, SCK, HOLD and CS input setup time

SI, SCK, HOLD and CS input hold time

SI, SCK, HOLD and CS input rise time

µs

SI, SCK, HOLD and CS input fall time

µs

DIS

SO output disable time

500

SO output valid time

100

SO output hold time

SO output rise time

SO output fall time

HOLD

HOLD time

400

HSU

HOLD setup time

100

HOLD hold time

100

HOLD low to output in high Z

100

HOLD high to output in low Z

100

Noise suppression time constant at
SI, SCK, HOLD and CS inputs

CS Deselect Time

µs

WPASU

WP, A0 and A1 setup time

WPAH

WP, A0 and A1 hold time

Symbol

Parameter

Typ.

Max.

Unit

High-voltage write cycle time (store instructions)

Symbol

Parameter

Min. Max. Unit

WRPO

Wiper response time after the third (last) power supply is stable

µs

WRL

Wiper response time after instruction issued (all load instructions)

µs

WRID

Wiper response time from an active SCL/SCK edge (increment/decrement instruction)

450

µs

X9440

FN8200.0

March 28, 2005

BASIC APPLICATIONS

+5V

V+

SCL

SDA

OUT

SCL

SDA

9440

REF1

(+5V)

TRANSDUCER

)

OUT

Programmable Window Detector with Memory

SCL

SDA

+5V

9440

OUT0

OUT1

OUT0

)

> V

, V

OUT

= High

< V

, V

OUT

= Low

OUT0

= L

OUT1

= L

OUT0

= H

OUT1

= H

OUT0

= L

OUT1

= H

For the signal voltage

> the upper limit V

, (V

OUT0

= H) · (V

OUT1

= H)

< the lower limit V

, (V

OUT0

= L) · (V

OUT1

= L)

For the window V

, (V

OUT0

= L) · (V

OUT1

= H)

(+5V)

(-5V)

REF2

(5V)

Programmable Level Detector with Memory (typical bias conditions)

X9440

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8200.0

March 28, 2005

Ordering Information

Device

Limits

Blank = 5V

10%

-2.7 = 2.7 to 5.5V

Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C

Package
P24 = 24-Lead Plastic DIP
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP

Potentiometer Organization

Pot 0

Pot 1

W =

10k

Y =

2.5k

X9440

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9440WV24-2.7

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9440WV24-2.7