FN8206.0

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PRELIMINARY

X9520

Fiber Channel/Gigabit Ethernet Laser Diode Control for Fiber Optic Modules

Triple DCP, POR, 2kbit EEPROM Memory,

Dual Voltage Monitors

FEATURES

· Three Digitally Controlled Potentiometers (DCPs)

--64 Tap - 10k

--100 Tap - 10k

--256 Tap - 100k

--Nonvolatile
--Write Protect Function

· 2kbit EEPROM Memory with Write Protect & Block

Lock

· 2-Wire industry standard Serial Interface

--Complies to the Gigabit Interface Converter

(GBIC) specification

· Power-on Reset (POR) Circuitry

--Programmable Threshold Voltage
--Software Selectable reset timeout
--Manual Reset

· Two Supplementary Voltage Monitors

--Programmable Threshold Voltages

· Single Supply Operation

--2.7V to 5.5V

· Hot Pluggable
· 20 Pin packages

--CSP (Chip Scale Package)
--TSSOP

DESCRIPTION

The X9520 combines three Digitally Controlled Potenti-
ometers (DCPs), V1 / Vcc Power-on Reset (POR) cir-
cuitry, two programmable voltage monitor inputs with
software and hardware indicators, and integrated
EEPROM with Block LockTM protection. All functions of
the X9520 are accessed by an industry standard 2-Wire
serial interface.

Two of the DCPs of the X9520 may be utilized to control
the bias and modulation currents of the laser diode in a
Fiber Optic module. The third DCP may be used to set
other various reference quantities, or as a coarse trim
for one of the other two DCPs. The 2kbit integrated
EEPROM may be used to store module definition data.
The programmable POR circuit may be used to ensure
that V1 / Vcc is stable before power is applied to the
laser diode / module. The programmable voltage moni-
tors may be used for monitoring various module alarm
levels.

The features of the X9520 are ideally suited to simplify-
ing the design of fiber optic modules which comply to
the Gigabit Interface Converter (GBIC) specification.
The integration of these functions into one package sig-
nificantly reduces board area, cost and increases reli-
ability of laser diode modules.

BLOCK DIAGRAM

DATA

COMMAND
DECODE &

CONTROL

LOGIC

SDA

SCL

POWER-ON /

LOW VOLTAGE

CONSTAT

PROTECT LOGIC

EEPROM

THRESHOLD

RESET LOGIC

GENERATION

RESET

VTRIP

V1 / Vcc

VTRIP

2kbit

V1RO

6 - BIT

NONVOLATILE

MEMORY

WIPER

COUNTER

V2RO

V3RO

7 - BIT

NONVOLATILE

MEMORY

NONVOLATILE

MEMORY

WIPER

COUNTER

WIPER

COUNTER

ARRAY

8 - BIT

VTRIP

Data Sheet

March 8, 2005

FN8206.0

March 8, 2005

DETAILED DEVICE DESCRIPTION

The X9520 combines three Intersil Digitally Controlled
Potentiometer (DCP) devices, V1 / Vcc power-on reset
control, V1 / Vcc low voltage reset control, two supple-
mentary voltage monitors, and integrated EEPROM with
Block LockTM protection, in one package. These func-
tions are suited to the control, support, and monitoring of
various system parameters in Fiber Channel / Gigabit
Ethernet fiber optic modules, such as in Gigabit Interface
Converter (GBIC) applications. The combination of the
X9520 fucntionality lowers system cost, increases reli-
ability, and reduces board space requirements using
Intersil's unique XBGATM packaging.

Two high resolution DCPs allow for the "set-and-forget"
adjustment of Laser Driver IC parameters such as Laser
Diode Bias and Modulation Currents. One lower resolu-
tion DCP may be used for setting sundry system param-
eters such as maximum laser output power (for eye
safety requirements).

Applying voltage to V

activates the Power-on Reset

circuit which allows the V1RO output to go HIGH, until
the supply the supply voltage stabilizes for a period of
time (selectable via software). The V1RO output then
goes LOW. The Low Voltage Reset circuitry allows the
V1RO output to go HIGH when V

falls below the mini-

mum V

trip point. V1RO remains HIGH until V

returns to proper operating level. A Manual Reset (MR)
input allows the user to externally trigger the V1RO out-
put (HIGH).

Two supplementary Voltage Monitor circuits continuously
compare their inputs to individual trip voltages. If an input
voltage exceeds it's associated trip level, a hardware

output (V3RO, V2RO) are allowed to go HIGH. If the
input voltage becomes lower than it's associated trip
level, the corresponding output is driven LOW. A
corresponding binary representation of the two monitor
circuit outputs (V2RO and V3RO) are also stored in
latched, volatile (CONSTAT) register bits. The status of
these two monitor outputs can be read out via the 2-wire
serial port.

An application of the V1RO output may be to drive the
"ENABLE" input of a Laser Driver IC, with MR as a
"TX_DISABLE" input. V2RO and V3RO may be used to
monitor "TX_FAULT" and "RX_LOS" conditions respec-
tively.

Intersil's unique circuits allow for all internal trip voltages
to be individually programmed with high accuracy. This
gives the designer great flexibility in changing system
parameters, either at the time of manufacture, or in the
field.

The memory portion of the device is a CMOS serial
EEPROM array with Intersil's Block LockTM protection.
This memory may be used to store fiber optic module
manufacturing data, serial numbers, or various other sys-
tem parameters. The EEPROM array is internally orga-
nized as x 8, and utilizes Intersil's proprietary Direct
WriteTM cells, providing a minimum endurance of
1,000,000 cycles and a minimum data retention of 100
years.

The device features a 2-Wire interface and software
protocol allowing operation on an I

CTM compatible

serial bus.

PIN CONFIGURATION

3
4

V1 / Vcc

SCL

7
8

12
11

SDA

V3RO

V1RO

V2RO

NOT TO SCALE

Top View Bumps Down

CSP

20 Pin TSSOP

V3RO

SCL

SDA

V2RO

V1 / Vcc

V1RO

X9520

FN8206.0

March 8, 2005

PIN ASSIGNMENT

TSSOP

CSP

Name

Function

Connection to end of resistor array for (the 256 Tap) DCP 2.

Connection to terminal equivalent to the "Wiper" of a mechanical potentiometer for DCP 2.

Connection to other end of resistor array for (the 256 Tap) DCP 2.

V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When

the V3 input is higher than the

VTRIP3

threshold voltage, V3RO makes a transition to a

HIGH level. Connect V3 to V

when not used.

V3RO

V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is

greater than

VTRIP3

and goes LOW when V3 is less than VTRIP3. There is no delay cir-

cuitry on this pin. The V3RO pin requires the use of an external "pull-up" resistor.

Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates

a reset cycle to the V1RO pin (V1 / Vcc RESET Output pin). V1RO will remain HIGH for time

purst

after MR has returned to it's normally LOW state. The reset time can be selected using

bits POR1 and POR0 in the CONSTAT Register. The MR pin requires the use of an external

"pull-down" resistor.

Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Pro-

tection is enabled. In the enabled state, this pin prevents all nonvolatile "write" operations. Al-

so, when the Write Protection is enabled, and the device Block Lock feature is active (i.e. the

Block Lock bits are NOT [0,0]), then no "write" (volatile or nonvolatile) operations can be per-

formed in the device (including the wiper position of any of the integrated Digitally Controlled

Potentiometers (DCPs). The WP pin uses an internal "pull-down" resistor, thus if left floating

the write protection feature is disabled.

SCL

Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for

data input and output.

SDA

Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and

out of the device. The SDA pin input buffer is always active (not gated). This pin requires an

external pull up resistor.

Vss

Ground.

Connection to other end of resistor for (the 100 Tap) DCP 1.

Connection to terminal equivalent to the "Wiper" of a mechanical potentiometer for DCP 1.

Connection to end of resistor array for (the 100 Tap) DCP 1.

Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer (DCP) 0.

Connection to terminal equivalent to the "Wiper" of a mechanical potentiometer for DCP 0.

Connection to the other end of resistor array for (the 64 Tap) DCP 0.

V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When

the V2 input is greater than the

VTRIP2

threshold voltage, V2RO makes a transition to a

HIGH level. Connect V2 to V

when not used.

V2RO

V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is

greater than

VTRIP2

, and goes LOW when V2 is less than

VTRIP2

. There is no power-up

reset delay circuitry on this pin. The V2RO pin requires the use of an external "pull-up" re-

sistor.

V1RO

V1 / Vcc RESET Output. This is an active HIGH, open drain output which becomes active

whenever V1 / Vcc falls below

VTRIP1

. V1RO becomes active on power-up and remains

active for a time t

purst

after the power supply stabilizes (t

purst

can be changed by varying the

POR0 and POR1 bits of the internal control register). The V1RO pin requires the use of an

external "pull-up" resistor. The V1RO pin can be forced active (HIGH) using the manual reset

(MR) input pin.

V1 / Vcc

Supply Voltage.

X9520

FN8206.0

March 8, 2005

PRINCIPLES OF OPERATION

SERIAL INTERFACE

Serial Interface Conventions

The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the
slave. The master always initiates data transfers, and
provides the clock for both transmit and receive opera-
tions. Therefore, the X9520 operates as a slave in all
applications.

Serial Clock and Data

Data states on the SDA line can change only while SCL
is LOW. SDA state changes while SCL is HIGH are
reserved for indicating START and STOP conditions.
See Figure 1. On power-up of the X9520, the SDA pin is
in the input mode.

Serial Start Condition

All commands are preceded by the START condition,
which is a HIGH to LOW transition of SDA while SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the START condition and does not respond
to any command until this condition has been met. See
Figure 2.

Serial Stop Condition

All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. The STOP condition is also used to
place the device into the Standby power mode after a
read sequence. A STOP condition can only be issued
after the transmitting device has released the bus. See
Figure 2.

Serial Acknowledge

An ACKNOWLE DGE (ACK) is a software convention
used to indicate a successful data transfer. The trans-
mitting device, either master or slave, will release the
bus after transmitting eight bits. During the ninth clock
cycle, the receiver will pull the SDA line LOW to
ACKNOWLEDGE that it received the eight bits of data.
Refer to Figure 3.

The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device
Identifier bits are contained in the Slave Address Byte. If
a write operation is selected, the device will respond with
an ACKNOWLEDGE after the receipt of each subse-
quent eight bit word.

In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected
and no STOP condition is generated by the master, the
device will continue to transmit data. The device will ter-

SCL

SDA

Data Stable

Data Change

Data Stable

Figure 1.

Valid Data Changes on the SDA Bus

SCL

SDA

Start

Stop

Figure 2.

Valid Start and Stop Conditions

X9520

FN8206.0

March 8, 2005

minate further data transmissions if an ACKNOWLEDGE
is not detected. The master must then issue a STOP
condition to place the device into a known state.

DEVICE INTERNAL ADDRESSING

Addressing Protocol Overview

The user addressable internal components of the X9520
can be split up into three main parts:

--Three Digitally Controlled Potentiometers (DCPs)

--EEPROM array

--Control and Status (CONSTAT) Register

Depending upon the operation to be performed on each
of these individual parts, a 1, 2 or 3 Byte protocol is used.
All operations however must begin with the Slave
Address Byte being issued on the SDA pin. The Slave
address selects the part of the X9520 to be addressed,
and specifies if a Read or Write operation is to be per-
formed.

It should be noted that in order to perform a write opera-
tion to either a DCP or the EEPROM array, the Write
Enable Latch (WEL) bit must first be set (See "BL1, BL0:
Block Lock protection bits - (Nonvolatile)" on page 13.)

Slave Address Byte

Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con-
sists of three parts:

--The Device Type Identifier which consists of the most

significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9520.

--The next three bits (SA3 - SA1) are the Internal Device

Address bits. Setting these bits to 000 internally
selects the EEPROM array, while setting these bits to
111 selects the DCP structures in the X9520. The
CONSTAT Register may be selected using the Inter-
nal Device Address 010.

--The Least Significant Bit of the Slave Address (SA0)

Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W bit is "1", then a
READ operation is selected. A "0" selects a WRITE
operation (Refer to Figure 4.)

SCL

from

Master

Data Output

from

Transmitter

Data Output

from

Receiver

Start

Acknowledge

Figure 3.

Acknowledge Response From Receiver

SCL

from

Master

SA6

SA7

SA5

SA3 SA2

SA1

SA0

DEVICE TYPE

IDENTIFIER

READ /

SA4

Internal Address

(SA3 - SA1)

Internally Addressed

Device

000

EEPROM Array

010

CONSTAT Register

111

DCP

Bit SA0

Operation

WRITE

READ

R/W

Figure 4.

Slave Address Format

1 0 1 0

WRITE

ADDRESS

INTERNAL

DEVICE

X9520

FN8206.0

March 8, 2005

Nonvolatile Write Acknowledge Polling

After a nonvolatile write command sequence (for either
the EEPROM array, the Non Volatile Memory of a DCP
(NVM), or the CONSTAT Register) has been correctly
issued (including the final STOP condition), the X9520
initiates an internal high voltage write cycle. This cycle
typically requires 5 ms. During this time, no further Read
or Write commands can be issued to the device. Write
Acknowledge Polling is used to determine when this high
voltage write cycle has been completed.

To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal
Device Address. The LSB of the Slave Address (R/W)
can be set to either 1 or 0 in this case. If the device is still
busy with the high voltage cycle then no ACKNOWL-
EDGE will be returned. If the device has completed the
write operation, an ACKNOWLEDGE will be returned
and the host can then proceed with a read or write opera-
tion (Refer to Figure 5.).

DIGITALLY CONTROLLED POTENTIOMETERS

DCP Functionality

The X9520 includes three independent resistor arrays.
These arrays respectively contain 63, 99 and 255
discrete resistive segments that are connected in series.
The physical ends of each array are equivalent to the
fixed terminals of a mechanical potentiometer (R

and

inputs - where x = 0,1,2).

At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper
(R

) output. Within each individual array, only one

switch may be turned on at any one time. These
switches are controlled by the Wiper Counter Register
(WCR) (See Figure 6). The WCR is a volatile register.

On power-up of the X9520, wiper position data is auto-
matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The Table below
shows the Initial Values of the DCP WCR's before the
contents of the NVM is loaded into the WCR.

ACK

returned?

Issue Slave Address
Byte (Read or Write)

Byte load completed

by issuing STOP.

Enter ACK Polling

Issue STOP

Issue START

YES

High Voltage Cycle

complete. Continue

command sequence?

Issue STOP

Continue normal

Read or Write

command sequence

PROCEED

YES

Figure 5.

Acknowledge Polling Sequence

DECODER

RESISTOR

ARRAY

FET

SWITCHES

WIPER

COUNTER

NON

MEMORY

VOLATILE

(WCR)

(NVM)

"WIPER"

Figure 6.

DCP Internal Structure

DCP

Initial Values Before Recall

/ 64 TAP

/ TAP = 63

/ 100 TAP

/ TAP = 0

/ 256 TAP

/ TAP = 255

X9520

FN8206.0

March 8, 2005

The data in the WCR is then decoded to select and
enable one of the respective FET switches. A "make
before break" sequence is used internally for the FET
switches when the wiper is moved from one tap position
to another.

Hot Pluggability

Figure 7 shows a typical waveform that the X9520 might
experience in a Hot Pluggable situation. On power-up,
V1 / Vcc applied to the X9520 may exhibit some amount
of ringing, before it settles to the required value.

The device is designed such that the wiper terminal
(R

) is recalled to the correct position (as per the last

stored in the DCP NVM), when the voltage applied to V1
/ Vcc exceeds VTRIP1

for a time exceeding t

purst

(the

Power-on Reset time, set in the CONSTAT Register -
See "CONTROL AND STATUS REGISTER" on
page 13.).

Therefore, if

trans

is defined as the time taken for V1 /

Vcc to settle above VTRIP1

(Figure 7): then the desired

wiper terminal position is recalled by (a maximum) time:

trans

purst. It should be noted that

trans

is deter-

mined by system hot plug conditions.

DCP Operations

In total there are three operations that can be performed
on any internal DCP structure:

--DCP Nonvolatile Write

--DCP Volatile Write

--DCP Read

A nonvolatile write to a DCP will change the "wiper
position" by simultaneously writing new data to the
associated WCR and NVM. Therefore, the new "wiper
position" setting is recalled into the WCR after V1 / Vcc of
the X9520 is powered down and then powered back up.

A volatile write operation to a DCP however, changes the
"wiper position" by writing new data to the associated
WCR only. The contents of the associated NVM register
remains unchanged. Therefore, when V1 / Vcc to the
device is powered down then back up, the "wiper
position" reverts to that last position written to the DCP
using a nonvolatile write operation.

Both volatile and nonvolatile write operations are
executed using a three byte command sequence: (DCP)
Slave Address Byte, Instruction Byte, followed by a Data
Byte (See Figure 9)

A DCP Read operation allows the user to "read out" the
current "wiper position" of the DCP, as stored in the
associated WCR. This operation is executed using the
Random Address Read command sequence, consisting
of the (DCP) Slave Address Byte followed by an
Instruction Byte and the Slave Address Byte again (Refer
to Figure 10.).

Instruction Byte

While the Slave Address Byte is used to select the DCP
devices, an Instruction Byte is used to determine which
DCP is being addressed.

The Instruction Byte (Figure 8) is valid only when the
Device Type Identifier and the Internal Device Address
bits of the Slave Address are set to 1010111. In this
case, the two Least Significant Bit's (I1 - I0) of the
Instruction Byte are used to select the particular DCP (0
- 2). In the case of a Write to any of the DCPs (i.e. the
LSB of the Slave Address is 0), the Most Significant Bit of
the Instruction Byte (I7), determines the Write Type (WT)
performed.

If WT is "1", then a Nonvolatile Write to the DCP

occurs.

In this case, the "wiper position" of the DCP is changed
by simultaneously writing new data to the associated

Figure 7.

DCP Power

V1 / Vcc

VTRIP1

V1 / Vcc (Max.)

purst

Maximum Wiper Recall time

trans

X9520

FN8206.0

March 8, 2005

WCR and NVM. Therefore, the new "wiper position" set-
ting is recalled into the WCR after V1 / Vcc of the X9520
has been powered down then powered back up

If WT is "0" then a DCP Volatile Write is performed. This
operation changes the DCP "wiper position" by writing
new data to the associated WCR only. The contents of
the associated NVM register remains unchanged. There-
fore, when V1 / Vcc to the device is powered down then
back up, the "wiper position" reverts to that last written to
the DCP using a nonvolatile write operation.

DCP Write Operation

A write to DCPx (x = 0,1,2) can be performed using the
three byte command sequence shown in Figure 9.

In order to perform a write operation on a particular DCP,
the Write Enable Latch (WEL) bit of the CONSTAT Reg-
ister must first be set (See "BL1, BL0: Block Lock protec-
tion bits - (Nonvolatile)" on page 13.)

The Slave Address Byte 10101110 specifies that a Write
to a DCP is to be conducted. An ACKNOWLEDGE is
returned by the X9520 after the Slave Address, if it has
been received correctly.

Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to be
written, while the WT bit determines if the Write is to be
volatile or nonvolatile. If the Instruction Byte format is
valid, another ACKNOWLEDGE is then returned by the
X9520.

Following the Instruction Byte, a Data Byte is issued to
the X9520 over SDA. The Data Byte contents is latched
into the WCR of the DCP on the first rising edge of the
clock signal, after the LSB of the Data Byte (D0) has
been issued on SDA (See Figure 34).

The Data Byte determines the "wiper position" (which
FET switch of the DCP resistive array is switched ON) of
the DCP. The maximum value for the Data Byte depends
upon which DCP is being addressed (see Table below).

Using a Data Byte larger than the values specified above
results in the "wiper terminal" being set to the highest tap
position. The "wiper position" does NOT roll-over to the
lowest tap position.

For DCP0 (64 Tap) and DCP2 (256 Tap), the Data Byte
maps one to one to the "wiper position" of the DCP
"wiper terminal". Therefore, the Data Byte 00001111
(1510) corresponds to setting the "wiper terminal" to tap

position 15. Similarly, the Data Byte 00011100 (2810)

corresponds to setting the "wiper terminal" to tap position
28. The mapping of the Data Byte to "wiper position" data
for DCP1 (100 Tap), is shown in "APPENDIX 1" . An
example of a simple C language function which "trans-
lates" between the tap position (decimal) and the Data
Byte (binary) for DCP1, is given in "APPENDIX 2" .

Description

Select a Volatile Write operation to be performed

on the DCP pointed to by bits P1 and P0

Select a Nonvolatile Write operation to be per-

formed on the DCP pointed to by bits P1 and P0

WRITE TYPE

DCP SELECT

This bit has no effect when a Read operation is being performed.

Figure 8.

Instruction Byte Format

P1 P0 A

D7 D6 D5 D4 D3 D2 D1 D0

SLAVE ADDRESS BYTE

INSTRUCTION BYTE

DATA BYTE

Figure 9.

DCP Write Command Sequence

P1 - P0

DCPx

# Taps

Max. Data Byte

x = 0

3Fh

x = 1

100

Refer to Appendix 1

x = 2

256

FFh

Reserved

X9520

FN8206.0

March 8, 2005

It should be noted that all writes to any DCP of the X9520
are random in nature. Therefore, the Data Byte of con-
secutive write operations to any DCP can differ by an
arbitrary number of bits. Also, setting the bits P1 = 1,
P0 = 1 is a reserved sequence, and will result in no
ACKNOWLEDGE after sending an Instruction Byte on
SDA.

The factory default setting of all "wiper position" settings
is with 00h stored in the NVM of the DCPs. This corre-
sponds to having the "wiper teminal" R

(x = 0,1,2) at

the "lowest" tap position, Therefore, the resistance
between R

and R

is a minimum (essentially only

the Wiper Resistance, R

DCP Read Operation

A read of DCPx (x = 0,1,2) can be performed using the
three byte random read command sequence shown in
Figure 10.

The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a "dummy"
write" is to be conducted. This "dummy" write operation
sets which DCP is to be read (in the preceding Read

operation). An ACKNOWLEDGE is returned by the
X9520 after the Slave Address if received correctly. Next,
an Instruction Byte is issued on SDA. Bits P1-P0 of the
Instruction Byte determine which DCP "wiper position" is
to be read. In this case, the state of the WT bit is "don't
care". If the Instruction Byte format is valid, then another
ACKNOWLEDGE is returned by the X9520.

Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave
address byte with the R/W bit set to 1. Then the X9520
issues an ACKNOWLEDGE followed by Data Byte, and
finally, the master issues a STOP condition. The Data
Byte read in this operation, corresponds to the "wiper
position" (value of the WCR) of the DCP pointed to by
bits P1 and P0.

It should be noted that when reading out the data byte
for DCP0 (64 Tap), the upper two most significant bits
are "unknown" bits. For DCP1 (100 Tap), the upper
most significant bit is an "unknown". For DCP2 (256
Tap) however, all bits of the data byte are relevant (See
Figure 10).

Slave

Address

Instruction

Byte

Slave

Address

Data Byte

SDA Bus

Signals from
the Slave

Signals from
the Master

Figure 10. DCP Read Sequence

"Dummy" write

READ Operation

1 0 1 1 1 1

0 0 0 0

1 0 1 1 1 1

WRITE Operation

- -

MSB

LSB

DCPx

x = 0

x = 1

x = 2

"-" = DON'T CARE

Slave

Address

Byte

Data

Byte

SDA Bus

Signals from

the Slave

Signals from

the Master

Figure 11. EEPROM Byte Write Sequence

Internal

Device

Address

1 0 1 0 0 0 0

WRITE Operation

X9520

FN8206.0

March 8, 2005

2kbit EEPROM ARRAY

Operations on the 2kbit EEPROM Array, consist of either
1, 2 or 3 byte command sequences. All operations on the
EEPROM must begin with the Device Type Identifier of
the Slave Address set to 1010000. A Read or Write to
the EEPROM is selected by setting the LSB of the Slave
Address to the appropriate value R/W (Read = "1",
Write = "0").

In some cases when performing a Read or Write to the
EEPROM, an Address Byte may also need to be speci-
fied. This Address Byte can contain the values 00h to
FFh.

EEPROM Byte Write

In order to perform an EEPROM Byte Write operation to
the EEPROM array, the Write Enable Latch (WEL) bit of
the CONSTAT Register must first be set (See "BL1, BL0:
Block Lock protection bits - (Nonvolatile)" on page 13.)

For a write operation, the X9520 requires the Slave
Address Byte and an Address Byte. This gives the mas-
ter access to any one of the words in the array. After
receipt of the Address Byte, the X9520 responds with an
ACKNOWLEDGE, and awaits the next eight bits of data.
After receiving the 8 bits of the Data Byte, it again
responds with an ACKNOWLEDGE. The master then
terminates the transfer by generating a STOP condition,
at which time the X9520 begins the internal write cycle to
the nonvolatile memory (See Figure 11). During this
internal write cycle, the X9520 inputs are disabled, so it
does not respond to any requests from the master. The
SDA output is at high impedance. A write to a region of
EEPROM memory which has been protected with the
Block-Lock feature (See "BL1, BL0: Block Lock protec-
tion bits - (Nonvolatile)" on page 13.), suppresses the
ACKNOWLEDGE bit after the Address Byte.

EEPROM Page Write

In order to perform an EEPROM Page Write operation to
the EEPROM array, the Write Enable Latch (WEL) bit of
the CONSTAT Register must first be set (See "BL1, BL0:
Block Lock protection bits - (Nonvolatile)" on page 13.)

The X9520 is capable of a page write operation. It is initi-
ated in the same manner as the byte write operation; but
instead of terminating the write cycle after the first data
byte is transferred, the master can transmit an unlimited
number of 8-bit bytes. After the receipt of each byte, the
X9520 responds with an ACKNOWLEDGE, and the
address is internally incremented by one. The page
address remains constant. When the counter reaches
the end of the page, it "rolls over" and goes back to `0' on
the same page.

For example, if the master writes 12 bytes to the page
starting at location 11 (decimal), the first 5 bytes are writ-
ten to locations 11 through 15, while the last 7 bytes are
written to locations 0 through 6. Afterwards, the address
counter would point to location 7. If the master supplies
more than 16 bytes of data, then new data overwrites the
previous data, one byte at a time (See Figure 13).

The master terminates the Data Byte loading by issuing
a STOP condition, which causes the X9520 to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 12 for the address, ACKNOWL-
EDGE, and data transfer sequence.

Stops and EEPROM Write Modes

Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
and receiving the subsequent ACKNOWLEDGE signal.
If the master issues a STOP within a Data Byte, or before
the X9520 issues a corresponding ACKNOWLEDGE,
the X9520 cancels the write operation. Therefore, the
contents of the EEPROM array does not change.

Slave

Address

Byte

Data

(n)

SDA Bus

Signals from
the Slave

Signals from
the Master

Data

(1)

(2 < n < 16)

Figure 12. EEPROM Page Write Operation

1 0 1 0 0 0 0 0

X9520

FN8206.0

March 8, 2005

EEPROM Array Read Operations

Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of the
Slave Address Byte is set to one. There are three basic
read operations: Current EEPROM Address Read, Ran-
dom EEPROM Read, and Sequential EEPROM Read.

Current EEPROM Address Read

Internally the device contains an address counter that
maintains the address of the last word read incremented
by one. Therefore, if the last read was to address n, the
next read operation would access data from address
n+1. On power-up, the address of the address counter is
undefined, requiring a read or write operation for initial-
ization.

Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an ACKNOWLEDGE and
then transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond
with an ACKNOWLEDGE during the ninth clock and then
issues a STOP condition (See Figure 14 for the address,
ACKNOWLEDGE, and data transfer sequence).

It should be noted that the ninth clock cycle of the read
operation is not a "don't care." To terminate a read oper-
ation, the master must either issue a STOP condition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a STOP condition.

Another important point to note regarding the "Current
EEPROM Address Read" , is that this operation is not
available if the last executed operation was an access to
a DCP or the CONSTAT Register (i.e.: an operation
using the Device Type Identifier 1010111 or 1010010).
Immediately after an operation to a DCP or CONSTAT
Register is performed, only a "Random EEPROM Read"
is available. Immediately following a "Random EEPROM
Read" , a "Current EEPROM Address Read" or "Sequen-
tial EEPROM Read" is once again available (assuming
that no access to a DCP or CONSTAT Register occur in
the interim).

Random EEPROM Read

Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master
must first perform a "dummy" write operation. The master
issues the START condition and the Slave Address Byte,
receives an ACKNOWLEDGE, then issues an Address

address

5 bytes

7 bytes

address

= 6

address pointer

ends here

Addr = 7

Figure 13. Example: Writing 12 bytes to a 16-byte page starting at location 11.

5 bytes

Slave

Address

Data

SDA Bus

Signals from
the Slave

Signals from
the Master

Figure 14. Current EEPROM Address Read Sequence

01 0

0 0 0

X9520

FN8206.0

March 8, 2005

Byte. This "dummy" Write operation sets the address
pointer to the address from which to begin the random
EEPROM read operation.

After the X9520 acknowledges the receipt of the Address
Byte, the master immediately issues another START
condition and the Slave Address Byte with the R/W bit
set to one. This is followed by an ACKNOWLEDGE from
the X9520 and then by the eight bit word. The master ter-
minates the read operation by not responding with an
ACKNOWLEDGE and instead issuing a STOP condition
(Refer to Figure 15.).

A similar operation called "Set Current Address" also
exists. This operation is performed if a STOP is issued
instead of the second START shown in Figure 15. In this
case, the device sets the address pointer to that of the
Address Byte, and then goes into standby mode after the
STOP bit. All bus activity will be ignored until another
START is detected.

Sequential EEPROM Read

Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an ACKNOWLEDGE,
indicating it requires additional data. The X9520 contin-
ues to output a Data Byte for each ACKNOWLEDGE
received. The master terminates the read operation by
not responding with an ACKNOWLEDGE and instead
issuing a STOP condition.

The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
the entire memory contents to be serially read during
one operation. At the end of the address space the
counter "rolls over" to address 00h and the device con-
tinues to output data for each ACKNOWLEDGE
received (Refer to Figure 16.).

Slave

Address

Byte

Slave

Address

Data

SDA Bus

Signals from
the Slave

Signals from
the Master

Figure 15. Random EEPROM Address Read Sequence

0 1 0 0 0 0

1 0 1 0 0 0 0

WRITE Operation

"Dummy" Write

READ Operation

Data

(2)

Slave

Address

Data

(n)

SDA Bus

Signals from
the Slave

Signals from
the Master

Data
(n-1)

(n is any integer greater than 1)

Data

(1)

Figure 16. Sequential EEPROM Read Sequence

0 0 0

X9520

FN8206.0

March 8, 2005

CONTROL AND STATUS REGISTER

The Control and Status (CONSTAT) Register provides
the user with a mechanism for changing and reading
the status of various parameters of the X9520 (See
Figure 17).

The CONSTAT register is a combination of both volatile
and nonvolatile bits. The nonvolatile bits of the CON-
STAT register retain their stored values even when V1 /
Vcc is powered down, then powered back up. The vola-
tile bits however, will always power-up to a known logic
state "0" (irrespective of their value at power-down).

A detailed description of the function of each of the CON-
STAT register bits follows:

WEL: Write Enable Latch (Volatile)

The WEL bit controls the Write Enable status of the
entire X9520 device. This bit must first be enabled before
ANY write operation (to DCPs, EEPROM memory array,
or the CONSTAT register). If the WEL bit is not first
enabled, then ANY proceeding (volatile or nonvolatile)
write operation to DCPs, EEPROM array, as well as the
CONSTAT register, is aborted and no ACKNOWLEDGE
is issued after a Data Byte.

The WEL bit is a volatile latch that powers up in the dis-
abled, LOW (0) state. The WEL bit is enabled / set by
writing 00000010 to the CONSTAT register. Once
enabled, the WEL bit remains set to "1" until either it is
reset to "0" (by writing 00000000 to the CONSTAT regis-
ter) or until the X9520 powers down, and then up again.

Writes to the WEL bit do not cause an internal high volt-
age write cycle. Therefore, the device is ready for
another operation immediately after a STOP condition is
executed in the CONSTAT Write command sequence
(See Figure 18).

RWEL: Register Write Enable Latch (Volatile)

The RWEL bit controls the (CONSTAT) Register Write
Enable status of the X9520. Therefore, in order to write
to any of the bits of the CONSTAT Register (except
WEL), the RWEL bit must first be set to "1". The RWEL
bit is a volatile bit that powers up in the disabled, LOW
("0") state.

It must be noted that the RWEL bit can only be set, once
the WEL bit has first been enabled (See "CONSTAT
Register Write Operation").

The RWEL bit will reset itself to the default "0" state, in
one of three cases:

--After a successful write operation to any bits of

the CONSTAT register has been completed (See
Figure 18).

--When the X9520 is powered down.

--When attempting to write to a Block Lock protected

region of the EEPROM memory (See "BL1, BL0: Block
Lock protection bits - (Nonvolatile)", below).

BL1, BL0: Block Lock protection bits - (Nonvolatile)

The Block Lock protection bits (BL1 and BL0) are used
to:

--Inhibit a write operation from being performed to cer-

tain addresses of the EEPROM memory array

--Inhibit a DCP write operation (changing the "wiper

position").

The region of EEPROM memory which is protected /
locked is determined by the combination of the BL1 and
BL0 bits written to the CONSTAT register. It is possible
to lock the regions of EEPROM memory shown in the
table below:

If the user attempts to perform a write operation on a pro-
tected region of EEPROM memory, the operation is
aborted without changing any data in the array.

Bit(s)

Description

WEL

Write Enable Latch bit

RWEL

V2OS

V2 Output Status flag

V3OS

V3 Output Status flag

BL1 - BL0

Sets the Block Lock partition

POR1 - POR0

Sets the Power-on Reset time

POR1

WEL

POR0

CS5

CS6

CS7

CS4

CS3

CS2

CS1

CS0

V3OS

V2OS

BL0

BL1

RWEL

Figure 17. CONSTAT Register Format

NOTE: Bits labelled NV are nonvolatile (See "CONTROL AND STATUS REGISTER").

BL1 BL0

Protected Addresses

(Size)

Partition of array

locked

None (Default)

C0h - FFh

(64 bytes

)

Upper 1/4

80h - FFh

(128 bytes

)

Upper 1/2

00h - FFh

(256 bytes)

All

X9520

FN8206.0

March 8, 2005

When the Block Lock bits of the CONSTAT register are
set to something other than BL1 = 0 and BL0 = 0, then
the "wiper position" of the DCPs cannot be changed - i.e.
DCP write operations cannot be conducted:

The factory default setting for these bits are BL1 = 0,
BL0 = 0.

IMPORTANT NOTE: If the Write Protect (WP) pin of the
X9520 is active (HIGH), then all nonvolatile write opera-
tions to both the EEPROM memory and DCPs are inhib-
ited, irrespective of the Block Lock bit settings (See "WP:
Write Protection Pin").

POR1, POR0: Power-on Reset bits (Nonvolatile)

Applying voltage to V

activates the Power-on Reset

circuit which holds V1RO output HIGH, until the supply
voltage stabilizes above the VTRIP1 threshold for a

period of time, t

PURST

(See Figure 30).

The Power-on Reset bits, POR1 and POR0 of the
CONSTAT register determine the t

PURST

delay time of

the Power-on Reset circuitry (See "VOLTAGE MONI-
TORING FUNCTIONS"). These bits of the CONSTAT
register are nonvolatile, and therefore power-up to the
last written state.

The nominal Power-on Reset delay time can be selected
from the following table, by writing the appropriate bits to
the CONSTAT register:

The default for these bits are POR1 = 0, POR0 = 1.

V2OS, V3OS: Voltage Monitor Status Bits (Volatile)

Bits V2OS and V3OS of the CONSTAT register are
latched, volatile flag bits which indicate the status of the
Voltage Monitor reset output pins V2RO and V3RO.

At power-up the VxOS (x = 2,3) bits default to the value
"0". These bits can be set to a "1" by writing the appropri-
ate value to the CONSTAT register. To provide consis-
tency between the VxRO and VxOS however, the status
of the VxOS bits can only be set to a "1" when the corre-
sponding VxRO output is HIGH.

Once the VxOS bits have been set to "1", they will be
reset to "0" if:

--The device is powered down, then back up,

--The corresponding VxRO output becomes LOW.

BL1

BL0

DCP Write Operation Permissible

YES (Default)

POR1

POR0

Power-on Reset delay (t

PUV1RO

)

50ms

100ms (Default)

200ms

300ms

R/W A

SCL

SDA

CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0

SLAVE ADDRESS BYTE

ADDRESS BYTE

CONSTAT REGISTER DATA IN

Figure 18. CONSTAT Register Write Command Sequence

X9520

FN8206.0

March 8, 2005

CONSTAT Register Write Operation

The CONSTAT register is accessed using the Slave
Address set to 1010010 (Refer to Figure 4.). Following
the Slave Address Byte, access to the CONSTAT regis-
ter requires an Address Byte which must be set to FFh.
Only one data byte is allowed to be written for each
CONSTAT register Write operation. The user must issue
a STOP, after sending this byte to the register, to initiate
the nonvolatile cycle that stores the BP1, BP0, POR1
and POR0 bits. The X9520 will not ACKNOWLEDGE
any data bytes written after the first byte is entered (Refer
to Figure 18.).

Prior to writing to the CONSTAT register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps

--Write a 02H to the CONSTAT Register to set the Write

Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a START and ended with a STOP).

--Write a 06H to the CONSTAT Register to set the Reg-

ister Write Enable Latch (RWEL) AND the WEL bit.
This is also a volatile cycle. The zeros in the data byte
are required. (Operation preceded by a START and
ended with a STOP).

--Write a one byte value to the CONSTAT Register that

has all the bits set to the desired state. The CONSTAT
register can be represented as qxyst01r in binary,
where xy are the Voltage Monitor Output Status
(V2OS and V3OS) bits, st are the Block Lock Protec-
tion (BL1 and BL0) bits, and qr are the Power-on Reset
delay time (t

PUV1RO

) control bits (POR1 - POR0).

This operation is proceeded by a START and ended
with a STOP bit. Since this is a nonvolatile write cycle,
it will typically take 5ms to complete. The RWEL bit is
reset by this cycle and the sequence must be repeated
to change the nonvolatile bits again. If bit 2 is set to `1'
in this third step (qxys t11r) then the RWEL bit is set,
but the V2OS, V3OS, POR1, POR0, BL1 and BL0 bits
remain unchanged. Writing a second byte to the con-
trol register is not allowed. Doing so aborts the write
operation and the X9520 does not return an
ACKNOWLEDGE.

For example, a sequence of writes to the device CON-
STAT register consisting of [02H, 06H, 02H] will reset all
of the nonvolatile bits in the CONSTAT Register to "0".

It should be noted that a write to any nonvolatile bit of
CONSTAT register will be ignored if the Write Protect
pin of the X9520 is active (HIGH) (See "WP: Write Pro-
tection Pin").

CONSTAT Register Read Operation

The contents of the CONSTAT Register can be read at
any time by performing a random read (See Figure 19).
Using the Slave Address Byte set to 10100101, and an
Address Byte of FFh. Only one byte is read by each reg-
ister read operation. The X9520 resets itself after the first
byte is read. The master should supply a STOP condition
to be consistent with the bus protocol.

After setting the WEL and / or the RWEL bit(s) to a "1",
a CONSTAT register read operation may occur, without
interrupting a proceeding CONSTAT register write
operation.

Slave

Address

Byte

Slave

Address

Data

SDA Bus

Signals from
the Slave

Signals from
the Master

Figure 19. CONSTAT Register Read Command Sequence

0 1 0 0 1 0

WRITE Operation

"Dummy" Write

READ Operation

CS7 ... CS0

X9520

FN8206.0

March 8, 2005

DATA PROTECTION

There are a number of levels of data protection features
designed into the X9520. Any write to the device first
requires setting of the WEL bit in the CONSTAT register.
A write to the CONSTAT register itself, further requires
the setting of the RWEL bit. Block Lock protection of the
device enables the user to inhibit writes to certain regions
of the EEPROM memory, as well as to all the DCPs. One
further level of data protection in the X9520, is incorpo-
rated in the form of the Write Protection pin.

WP: Write Protection Pin

When the Write Protection (WP) pin is active (HIGH), it
disables nonvolatile write operations to the X9520.

The table below (X9520 Write Permission Status) sum-
marizes the effect of the WP pin (and Block Lock), on the
write permission status of the device.

Additional Data Protection Features

In addition to the preceding features, the X9520 also
incorporates the following data protection functionality:

--The proper clock count and data bit sequence is

required prior to the STOP bit in order to start a nonvol-
atile write cycle.

VOLTAGE MONITORING FUNCTIONS

V1 / Vcc Monitoring

The X9520 monitors the supply voltage and drives the
V1RO output HIGH (using an external "pull up" resistor)
if V1 / Vcc is lower than V

TRIP1

threshold. The V1RO

output will remain HIGH until V1 / Vcc exceeds V

TRIP1

for a minimum time of t

PURST

. After this time, the

V1RO pin is driven to a LOW state. See Figure 30.

For the Power-on / Low Voltage Reset function of the
X9520, the V1RO output may be driven HIGH down to a
V1 / Vcc of 1V (V

RVALID

). See Figure 30. Another fea-

ture of the X9520, is that the value of t

PURST

may be

selected in software via the CONSTAT register (See
"POR1, POR0: Power-on Reset bits (Nonvolatile)" on
page 14.).

It is recommended to stop communication to the device
while V1R0 is HIGH. Also, setting the Manual Reset
(MR) pin HIGH overrides the Power-on / Low Voltage cir-
cuitry and forces the V1RO output pin HIGH (See "MR:
Manual Reset").

MR: Manual Reset

The V1RO output can be forced HIGH externally using
the Manual Reset (MR) input. MR is a de-bounced, TTL
compatible input, and so it may be operated by connect-
ing a push-button directly from V1 / Vcc to the MR pin.

V1RO remains HIGH for time t

PURST

after MR has

returned to its LOW state (See Figure 20). An external
"pull down" resistor is required to hold this pin (nor-
mally) LOW.

X9520 Write Permission Status

V1RO

V1 / Vcc

0 Volts

PURST

Figure 20. Manual Reset Response

0 Volts

TRIP1

Block Lock

Bits

DCP Volatile Write

Permitted

DCP Nonvolatile

Write Permitted

Write to EEPROM

Permitted

Write to CONSTAT Register

Permitted

BL0

BL1

Volatile Bits

Nonvolatile

Bits

YES

Not in locked region

YES

Not in locked region

YES

Yes (All Array)

YES

X9520

FN8206.0

March 8, 2005

V2 Monitoring

The X9520 asserts the V2RO output HIGH if the volt-
age V2 exceeds the corresponding V

TRIP2

threshold

(See Figure 21). The bit V2OS in the CONSTAT regis-
ter is then set to a "0" (assuming that it has been set to
"1" after system initilization).

The V2RO output may remain active HIGH with V

down to 1V.

V3 Monitoring

The X9520 asserts the V3RO output HIGH if the volt-
age V3 exceeds the corresponding V

TRIP3

threshold

(See Figure 21). The bit V3OS in the CONSTAT regis-
ter is then set to a "0" (assuming that it has been set to
"1" after system initilization).

The V3RO output may remain active HIGH with V

down to 1V.

TRIPX

THRESHOLDS (X=1,2,3)

The X9520 is shipped with pre-programmed threshold
(V

TRIPx

) voltages. In applications where the required

thresholds are different from the default values, or if a
higher precision / tolerance is required, the X9520 trip
points may be adjusted by the user, using the steps
detailed below.

Setting a V

TRIPx

Voltage (x=1,2,3)

There are two procedures used to set the threshold
voltages (V

TRIPx

), depending if the threshold voltage

to be stored is higher or lower than the present value.
For example, if the present V

TRIPx

is 2.9 V and the

new V

TRIPx

is 3.2 V, the new voltage can be stored

directly into the V

TRIPx

cell. If however, the new set-

ting is to be lower than the present setting, then it is
necessary to "reset" the V

TRIPx

voltage before setting

the new value.

Setting a Higher V

TRIPx

Voltage (x=1,2,3)

To set a V

TRIPx

threshold to a new voltage which is

higher than the present threshold, the user must apply
the desired V

TRIPx

threshold voltage to the corre-

sponding input pin (V1 / Vcc, V2 or V3). Then, a pro-
gramming voltage (Vp) must be applied to the WP pin
before a START condition is set up on SDA. Next, issue
on the SDA pin the Slave Address A0h, followed by
the Byte Address 01h for V

TRIP1

, 09h for V

TRIP2

, and

0Dh for V

TRIP3

, and a 00h Data Byte in order to pro-

gram V

TRIPx

. The STOP bit following a valid write

operation initiates the programming sequence. Pin WP
must then be brought LOW to complete the operation

0 1 2 3 4 5 6 7

SCL

SDA

A0h

0 1 2 3 4 5 6 7

TRIPx

V2, V3

01h

sets V

TRIP1

Figure 22. Setting V

TRIPx

to a higher level (x=1,2,3).

09h

sets V

TRIP2

0Dh

sets V

TRIP3

Data Byte

V1 / Vcc

00h

All others Reserved.

Figure 21. Voltage Monitor Response

VxRO

TRIPx

(x = 2,3)

0 Volts

TRIP1

V1 / Vcc

X9520

FN8206.0

March 8, 2005

(See Figure 23). The user does not have to set the
WEL bit in the CONSTAT register before performing
this write sequence.

Setting a Lower V

TRIPx

Voltage (x=1,2,3).

In order to set V

TRIPx

to a lower voltage than the

present value, then V

TRIPx

must first be "reset"

according to the procedure described below. Once
V

TRIPx

has been "reset", then V

TRIPx

can be set to

the desired voltage using the procedure described in
"Setting a Higher V

TRIPx

Voltage".

Resetting the V

TRIPx

Voltage (x=1,2,3).

To reset a V

TRIPx

voltage, apply the programming

voltage (Vp) to the WP pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
V

TRIP1

, 0Bh for V

TRIP2

, and 0Fh for V

TRIP3

, followed

by 00h for the Data Byte in order to reset V

TRIPx

. The

STOP bit following a valid write operation initiates the
programming sequence. Pin WP must then be brought
LOW to complete the operation (See Figure 23).The
user does not have to set the WEL bit in the CON-
STAT register before performing this write sequence.

After being reset, the value of V

TRIPx

becomes a nom-

inal value of 1.7V.

TRIPx

Accuracy (x=1,2,3).

The accuracy with which the V

TRIPx

thresholds are set,

can be controlled using the iterative process shown in
Figure 24.

If the desired threshold is less that the present threshold
voltage, then it must first be "reset" (See "Resetting the
VTRIPx Voltage (x=1,2,3).").

The desired threshold voltage is then applied to the
appropriate input pin (V1 / Vcc, V2 or V3) and the pro-
cedure described in Section "Setting a Higher V

TRIPx

Voltage" must be followed.

Once the desired V

TRIPx

threshold has been set, the

error between the desired and (new) actual set threshold
can be determined. This is achieved by applying V1 / Vcc
to the device, and then applying a test voltage higher
than the desired threshold voltage, to the input pin of the
voltage monitor circuit whose V

TRIPx

was programmed.

For example, if V

TRIP2

was set to a desired level of 3.0

V, then a test voltage of 3.4 V may be applied to the volt-
age monitor input pin V2. In the case of setting of V

TRIP1

then only V1 / Vcc need be applied. In all cases, care
should be taken not to exceed the maximum input volt-
age limits.

After applying the test voltage to the voltage monitor
input pin, the test voltage can be decreased (either in dis-
crete steps, or continuously) until the output of the volt-
age monitor circuit changes state. At this point, the error
between the actual / measured, and desired threshold
levels is calculated.

For example, the desired threshold for V

TRIP2

is set to

3.0 V, and a test voltage of 3.4 V was applied to the input
pin V2 (after applying power to V1 / Vcc). The input volt-
age is decreased, and found to trip the associated output
level of pin V2RO from a LOW to a HIGH, when V2
reaches 3.09 V. From this, it can be calculated that the
programming error is 3.09 - 3.0 = 0.09 V.

SDA

A0h

0 1 2 3 4 5 6 7

SCL

0 1 2 3 4 5 6 7

Figure 23. Resetting the V

TRIPx

Level

03h

Resets

VTRIP1

0Bh

Resets

VTRIP2

0Fh

Resets

VTRIP3

Data Byte

00h

All others Reserved.

X9520

FN8206.0

March 8, 2005

If the error between the desired and measured V

TRIPx

less than the maximum desired error, then the program-
ming process may be terminated. If however, the error is
greater than the maximum desired error, then another
iteration of the V

TRIPx

programming sequence can be

performed (using the calculated error) in order to further
increase the accuracy of the threshold voltage.

If the calculated error is greater than zero, then the
V

TRIPx

must first be "reset", and then programmed to the

a value equal to the previously set V

TRIPx

minus the cal-

culated error. If it is the case that the error is less than
zero, then the V

TRIPx

must be programmed to a value

equal to the previously set V

TRIPx

plus the absolute

value of the calculated error.

Continuing the previous example, we see that the calcu-
lated error was 0.09V. Since this is greater than zero, we
must first "reset" the V

TRIP2

threshold, then apply a volt-

age equal to the last previously programmed voltage,
minus the last previously calculated error. Therefore, we
must apply V

TRIP2

= 2.91 V to pin V2 and execute the

programming sequence ( ) .

Using this process, the desired accuracy for a particu-

lar V

TRIPx

threshold may be attained using a succes-

sive number of iterations.

TRIPx

Programming

Apply Vcc & Voltage

Decrease Vx

switches?

Actual

TRIPx

Desired

TRIPx

DONE

Execute

Sequence

TRIPx

Reset

Set Vx = desired

TRIPx

Execute

Sequence

Set Higher

TRIPx

New Vx applied =

Old Vx applied

| Error |

Execute

Sequence

Reset

TRIPx

New Vx applied =

Old Vx applied

| Error |

Error < MDE

| Error | < | MDE |

YES

Error >MDE

YES

Figure 24. V

TRIPx

Setting / Reset Sequence (x=1,2,3)

> Desired

TRIPx

to Vx

Desired V

TRIPx

present value?

Note: X = 1,2,3.

Let: MDE = Maximum Desired Error

Output

Acceptable

Error Range

MDE

Error = Actual - Desired

= Error

Desired Value

X9520

FN8206.0

March 8, 2005

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This
is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect device reliability.

Figure 25. Equivalent A.C. Circuit

Figure 26. DCP SPICE Macromodel

Parameter

Min.

Max.

Units

Temperature under Bias

-65

+135

°C

Storage Temperature

-65

+150

°C

Voltage on WP pin (With respect to Vss)

-1.0

+15

Voltage on other pins (With respect to Vss)

-1.0

| Voltage on R

Voltage on R

(x = 0,1,2.

Referenced to Vss

)

V1 / Vcc

D.C. Output Current (SDA,V1RO,V2RO,V3RO)

Lead Temperature (Soldering, 10 seconds)

300

°C

Supply Voltage Limits (Applied V1 / Vcc voltage, referenced to Vss)

2.7

5.5

Temperature

Min.

Max.

Units

Industrial

-40

+85

°C

V1 / Vcc = 5V

V2RO

100pF

SDA

2300

V3RO

V1RO

10pF

TOTAL

25pF

(x = 0,1,2)

X9520

FN8206.0

March 8, 2005

D.C. OPERATING CHARACTERISTICS

Notes: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave

Address Byte are incorrect; 200nS after a STOP ending a read operation; or t

after a STOP ending a write operation.

Notes: 2. The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; t

after a STOP that ini-

tiates a high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave Address
Byte.

Notes: 3. Current through external pull up resistor not included.
Notes: 4.

= Voltage applied to input pin.

Notes: 5.

OUT

= Voltage applied to output pin.

Notes: 6. See "ORDERING INFORMATION" on page 33.
Notes: 7. V

Min. and V

Max. are for reference only and are not tested

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions / Notes

CC1

(1)

Current into V

(X9520: Active)

Read memory array

(3)

Write nonvolatile memory

0.4

1.5

SCL

= 400kHz

CC2

(2)

Current into V

(X9520:Standby)

With 2-Wire bus activity

(3)

No 2-Wire bus activity

SDA

= V

MR = Vss

WP = Vss or Open/Floating

SCL

= V

(when no bus

activity else f

SCL

= 400kHz)

Input Leakage Current (SCL, SDA, MR)

0.1

(4)

= GND to V

CC.

Input Leakage Current (WP)

Analog Input Leakage

µA

= V

to V

with all other

analog inputs floating

Output Leakage Current (SDA, V1RO,

V2RO, V3RO)

0.1

OUT

(5)

= GND to V

CC.

X9520 is in Standby

(2)

TRIP1PR

TRIP1

Programming Range

2.75

4.70

TRIPxPR

TRIPx

Programming Range (x=2,3)

1.8

4.70

TRIP1

(6)

Pre - programmed V

TRIP1

threshold

2.85

4.55

3.0

4.7

3.05

4.75

Factory shipped default option A

Factory shipped default option B

TRIP2

(6)

Pre - programmed V

TRIP2

threshold

1.65

2.85

1.8

3.0

1.85

3.05

Factory shipped default option A

Factory shipped default option B

TRIP3

(6)

Pre - programmed V

TRIP3

threshold

1.65

2.85

1.8

3.0

1.85

3.05

Factory shipped default option A

Factory shipped default option B

V2 Input leakage current

V3 Input leakage current

SDA

= V

SCL

= V

Others=GND or V

(7)

Input LOW Voltage (SCL, SDA, WP, MR)

-0.5

0.8

(7)

Input HIGH Voltage (SCL,SDA, WP, MR)

2.0

+0.5

OLx

V1RO, V2RO, V3RO, SDA Output Low

Voltage

0.4

SINK

= 2.0mA

X9520

FN8206.0

March 8, 2005

A.C. CHARACTERISTICS (See Figure 27, Figure 28, Figure 29)

A.C. TEST CONDITIONS

NONVOLATILE WRITE CYCLE TIMING

CAPACITANCE (T

= 25°C, F = 1.0 MHZ, V

= 5V)

Notes: 1. Typical values are for T

= 25°C and V

= 5.0V

Notes: 2. Cb = total capacitance of one bus line in pF.
Notes: 3. Over recommended operating conditions, unless otherwise specified
Notes: 4. t

is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It

is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

Notes: 5. This parameter is not 100% tested.

Symbol Parameter

400kHz

Min

Max

Units

SCL

SCL Clock Frequency

400

kHz

(5)

Pulse width Suppression Time at inputs

(5)

SCL LOW to SDA Data Out Valid

0.1

0.9

BUF

Time the bus free before start of new transmission

1.3

LOW

Clock LOW Time

1.3

HIGH

Clock HIGH Time

0.6

SU:STA

Start Condition Setup Time

0.6

HD:STA

Start Condition Hold Time

0.6

SU:DAT

Data In Setup Time

100

HD:DAT

Data In Hold Time

SU:STO

Stop Condition Setup Time

0.6

(5)

Data Output Hold Time

(5)

SDA and SCL Rise Time

20 +.1Cb

(2)

300

(5)

SDA and SCL Fall Time

20 +.1Cb

(2)

300

SU:WP

WP Setup Time

0.6

HD:WP

WP Hold Time

(5)

Capacitive load for each bus line

400

Input Pulse Levels

0.1V

to 0.9V

Input Rise and Fall Times

10ns

Input and Output Timing Levels

0.5V

Output Load

See Figure 25

Symbol Parameter

Min.

Typ.(1)

Max.

Units

(4)

Nonvolatile Write Cycle Time

Symbol

Parameter

Max

Units

Test Conditions

OUT

(5)

Output Capacitance (SDA, V1RO, V2RO, V3RO)

OUT

= 0V

(5)

Input Capacitance (SCL, WP, MR)

= 0V

X9520

FN8206.0

March 8, 2005

POTENTIOMETER CHARACTERISTICS

Notes: 1. Power Rating between the wiper terminal R

WX(n)

and the end terminals R

or R

- for ANY tap position n, (x = 0,1,2).

Notes: 2. Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance = (R

wx(n)

(actual) - R

wx(n)

(expected)) = ±1

Ml Maximum (x = 0,1,2).

Notes: 3. Relative Linearity is a measure of the error in step size between taps = R

Wx(n+1)

- [R

wx(n)

+ Ml] = ±1 Ml (x = 0,1,2)

Notes: 4. 1 Ml = Minimum Increment = R

TOT

/ (Number of taps in DCP - 1).

Notes: 5. Typical values are for T

= 25°C and nominal supply voltage.

Notes: 6. This parameter is periodically sampled and not 100% tested.

Symbol

Parameter

Limits

Test Conditions/Notes

Min.

Typ.

Max.

Units

TOL

End to End Resistance Tolerance

-20

+20

RHx

Terminal Voltage (x = 0,1,2)

Vss

RLx

Terminal Voltage (x = 0,1,2)

Vss

Power Rating

(1)(6)

TOTAL

= 10k

(

DCP0, DCP1)

TOTAL

= 100k

(

DCP2)

DCP Wiper Resistance

200

400

= 1mA, V

= 5 V,

RHx

= Vcc, V

RLx

= Vss

(x = 0,1,2).

400

1200

= 1mA, V

= 2.7 V,

RHx

= Vcc, V

RLx

= Vss

(x = 0,1,2)

Wiper Current

(6)

4.4

Noise

mV/

sqt(Hz)

TOTAL

= 10k

(

DCP0, DCP1)

mV/

sqt(Hz)

TOTAL

= 100k

(

DCP2)

Absolute Linearity

(2)

-1

(4)

w(n)(actual)

- R

w(n)(expected)

Relative Linearity

(3)

-1

(4)

w(n+1)

- [R

w(n)+MI

]

TOTAL

Temperature Coefficient

±300

ppm/°C

TOTAL

= 10k

(

DCP0, DCP1)

±300

ppm/°C

TOTAL

= 100k

(

DCP2)

Potentiometer Capacitances

(6)

10/10/25

See Figure 26.

Wiper Response time

(6)

200

See Figure 34.

X9520

FN8206.0

March 8, 2005

TRIPX

(X=1,2,3) PROGRAMMING PARAMETERS (See Figure 33)

Notes:

The above parameters are not 100% tested.

V1RO, V2RO, V3RO OUTPUT TIMING. (See Figure 30, Figure 31, Figure 32)

Notes: 1. See Figure 31 for timing diagram.
Notes: 2. See Figure 25 for equivalent load.
Notes: 3. This parameter describes the lowest possible V1 / Vcc level for which the outputs V1RO, V2RO, and V3RO will be correct with respect to

their inputs (V1 / Vcc, V2, V3).

Notes: 4. From MR rising edge crossing V

, to V1RO rising edge crossing V

Notes: 5. The above parameters are not 100% tested.

Parameter

Description

Min

Typ

Max

Units

VPS

TRIPx

Program Enable Voltage Setup time

VPH

TRIPx

Program Enable Voltage Hold time

TSU

TRIPx

Setup time

THD

TRIPx

Hold (stable) time

VPO

TRIPx

Program Enable Voltage Off time

(Between successive adjustments)

TRIPx

Write Cycle time

Programming Voltage

TRIPx

Program Voltage accuracy

(Programmed at 25

C.)

-100

+100

TRIP

Program variation after programming (-40 - 85

C).

(Programmed at 25

C.)

-25

+10

+25

Symbol

Description

Condition

Min.

Typ.

Max.

Units

PURST

(5)

Power On Reset delay time

POR1 = 0, POR0 = 0

POR1 = 0, POR0 = 1

100

150

POR1 = 1, POR0 = 0

100

200

300

POR1 = 1, POR0 = 1

150

300

450

MRD

(31)(2)(5)

MR to V1RO propagation delay

See

(1)(2)(4)

MRDPW

(5)

MR pulse width

500

RPDx

(5)

V1 / Vcc, V2, V3 to V1RO,

V2RO, V3RO propagation

delay (respectively)

(5)

V1 / Vcc, V2, V3 Fall Time

mV/

(5)

V1 / Vcc, V2, V3 Rise Time

mV/

RVALID

(5)

V1 / Vcc for V1RO, V2RO,
V3RO Valid

(3)

X9520

FN8206.0

March 8, 2005

APPENDIX 2

DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 1)

unsigned DCP1_TAP_Position(int tap_pos)

{

int block;

int i;

int offset;

int wcr_val;

offset= 0;

block = tap_pos / 25;

if (block < 0) return ((unsigned)0);

else if (block <= 3)

{

switch(block)

{

case (0): return ((unsigned)tap_pos) ;

case (1):

{

wcr_val = 56;

offset = tap_pos - 25;

for (i=0; i<= offset; i++) wcr_val-- ;

return ((unsigned)++wcr_val);

}

case (2):

{

wcr_val = 64;

offset = tap_pos - 50;

for (i=0; i<= offset; i++) wcr_val++ ;

return ((unsigned)--wcr_val);

}

case (3):

{

wcr_val = 120;

offset = tap_pos - 75;

for (i=0; i<= offset; i++) wcr_val-- ;

return ((unsigned)++wcr_val);

}

return((unsigned)01100000);

}

X9520

FN8206.0

March 8, 2005

Ball Matrix:

RL2

RW2

Vcc

V2RO

RH2

V1RO

V3RO

RL0

RW0

SCL

RH0

RH1

SDA

RL1

RW1

Vss

Package Dimensions

Symbol

Millimeters

Inches

Min

Nominal

Max

Min

Nominal

Max

Package Width

2.542

2.572

2.602

Package Length

3.812

3.842

3.872

Package Height

0.644

0.677

0.710

Body Thickness

0.444

0.457

0.470

Ball Height

0.220

0.240

0.260

Ball Diameter

0.310

0.330

0.350

Ball Pitch Width

0.5

Ball Pitch Length

0.5

Ball to Edge Spacing Width

0.511

0.536

0.561

Ball to Edge Spacing Length

0.896

0.921

0.946

9520RR YWW IA LOT #

20-Bump Chip Scale Package (CSP B20)

Package Outline Drawing

Top View (Marking Side)

Bottom View (Bumped Side)

Side View

X9520

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8206.0

March 8, 2005

ORDERING INFORMATION

Device

X9520

For details of preset threshold values

See "D.C. OPERATING CHARACTERISTICS"

Preset (Factory Shipped) V

TRIPx

Threshold Levels (x=1,2,3)

A = Optimized for 3.3 V system monitoring

B = Optimized for 5 V system monitoring

Temperature Range
I = Industrial -40

C to +85

Package
V20 = 20-Lead TSSOP
B20 = 20-Lead CSP

X9520

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9520B20IA

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9520B20IA