Motorola TMOS Power MOSFET Transistor Device Data

Designer's

Data Sheet

TMOS E-FET

Power Field Effect Transistor

DPAK for Surface Mount

NChannel EnhancementMode Silicon Gate

This advanced TMOS EFET is designed to withstand high

energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

Avalanche Energy Specified

SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode

Diode is Characterized for Use in Bridge Circuits

IDSS and VDS(on) Specified at Elevated Temperature

Surface Mount Package Available in 16 mm, 13inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number

MAXIMUM RATINGS

(TC = 25

C unless otherwise noted)

Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

100

Vdc

DraintoGate Voltage (RGS = 1.0 M

)

VDGR

100

Vdc

GatetoSource Voltage -- Continuous

GatetoSource Voltage

-- NonRepetitive (tp

10 ms)

VGS

VGSM

Vdc
Vpk

Drain Current -- Continuous

Drain Current

-- Continuous @ 100

Drain Current

-- Single Pulse (tp

ID
ID

IDM

6.0

Adc

Apk

Total Power Dissipation @ TC = 25

Derate above 25

Total Power Dissipation @ TA = 25

C, when mounted to minimum recommended pad size

0.32
1.75

Watts

Operating and Storage Temperature Range

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy -- Starting TJ = 25

(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 10 Apk, L = 1.0 mH, RG =25

)

EAS

Thermal Resistance -- Junction to Case

Thermal Resistance

-- Junction to Ambient

Thermal Resistance

-- Junction to Ambient, when mounted to minimum recommended pad size

3.13

100

71.4

C/W

Maximum Temperature for Soldering Purposes, 1/8

from case for 10 seconds

260

Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.

EFET and Designer's are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.

Preferred devices are Motorola recommended choices for future use and best overall value.

Order this document

by MTD10N10EL/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Motorola, Inc. 1995

MTD10N10EL

TMOS POWER FET

10 AMPERES

100 VOLTS

RDS(on) = 0.22 OHM

Motorola Preferred Device

CASE 369A13, Style 2

DPAK Surface Mount

MTD10N10EL

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS

(TJ = 25

C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS

DraintoSource Breakdown Voltage

(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

100

115

--
--

Vdc

mV/

Zero Gate Voltage Drain Current

(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125

IDSS

--
--

100

Adc

GateBody Leakage Current (VGS =

15 Vdc, VDS = 0 Vdc)

IGSS

100

nAdc

ON CHARACTERISTICS (1)

Gate Threshold Voltage

(VDS = VGS, ID = 250

Adc)

Threshold Temperature Coefficient (Negative)

VGS(th)

1.0

1.45

4.0

2.0

Vdc

mV/

Static DraintoSource OnResistance (VGS = 5.0 Vdc, ID = 5.0 Adc)

RDS(on)

0.17

0.22

Ohm

DraintoSource OnVoltage

(VGS = 5.0 Vdc, ID = 10 Adc)
(VGS = 5.0 Vdc, ID = 5.0 Adc, TJ = 125

VDS(on)

--
--

1.85

2.6
2.3

Vdc

Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc)

gFS

2.5

7.9

mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Ciss

741

1040

Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Coss

175

250

Reverse Transfer Capacitance

f = 1.0 MHz)

Crss

18.9

SWITCHING CHARACTERISTICS (2)

TurnOn Delay Time

(VDD = 50 Vdc, ID = 10 Adc,

VGS = 5.0 Vdc,

RG = 9.1

)

td(on)

Rise Time

(VDD = 50 Vdc, ID = 10 Adc,

VGS = 5.0 Vdc,

RG = 9.1

)

150

TurnOff Delay Time

VGS = 5.0 Vdc,

RG = 9.1

)

td(off)

Fall Time

G = 9.1

)

Gate Charge

(See Figure 8)

(VDS = 80 Vdc, ID = 10 Adc,

VGS = 5.0 Vdc)

9.3

(See Figure 8)

(VDS = 80 Vdc, ID = 10 Adc,

VGS = 5.0 Vdc)

2.56

(VDS = 80 Vdc, ID = 10 Adc,

VGS = 5.0 Vdc)

4.4

4.66

SOURCEDRAIN DIODE CHARACTERISTICS

Forward OnVoltage (1)

(IS = 10 Adc, VGS = 0 Vdc)

(IS = 10 Adc, VGS = 0 Vdc, TJ = 125

VSD

--
--

0.98

0.898

1.6

Vdc

Reverse Recovery Time

(See Figure 14)

(IS = 10 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/

trr

124.7

(See Figure 14)

(IS = 10 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/

(IS = 10 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/

38.7

Reverse Recovery Stored Charge

QRR

0.539

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the drain lead 0.25

from package to center of die)

4.5

Internal Source Inductance

(Measured from the source lead 0.25

from package to source bond pad)

7.5

(1) Pulse Test: Pulse Width

300

s, Duty Cycle

2%.

(2) Switching characteristics are independent of operating junction temperature.

MTD10N10EL

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

Figure 3. OnResistance versus Drain Current

and Temperature

Figure 4. OnResistance versus Drain Current

and Gate Voltage

Figure 5. OnResistance Variation with

Temperature

Figure 6. DrainToSource Leakage

Current versus Voltage

DI , DRAIN CURRENT

(AMPS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

7 V

3.5 V

4 V

5 V

TJ = 25

DI , DRAIN CURRENT

(AMPS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VDS

5 V

TJ = 100

4.5 V

3 V

2 V

DS(on)

, DRAINT

OSOURCE RESIST

ANCE (OHMS)

ID, DRAIN CURRENT (AMPS)

TJ = 25

VGS = 5 V

10 V

0.25

0.2

DS(on)

, DRAINT

OSOURCE RESIST

ANCE (OHMS)

0.35

0.25

0.15

0.05

ID, DRAIN CURRENT (AMPS)

VGS = 10 V

TJ = 25

100

0.15

0.1

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

I DSS

, LEAKAGE (nA)

VGS = 0 V

100

TJ = 125

100

DS(on)

, DRAINT

OSOURCE RESIST

ANCE

(NORMALIZED)

TJ, JUNCTION TEMPERATURE (

VGS = 5 V
ID = 5 A

100

150

125

1.5

0.5

MTD10N10EL

Motorola TMOS Power MOSFET Transistor Device Data

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (

t) are deter-

mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat-
ing rise and fall because draingate capacitance varies great-
ly with applied voltage. Accordingly, gate charge data is used.
In most cases, a satisfactory estimate of average input current
(IG(AV)) can be made from a rudimentary analysis of the drive
circuit so that

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive
load, VGS remains virtually constant at a level known as the
plateau voltage, VSGP. Therefore, rise and fall times may be
approximated by the following:

tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where

VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is not
constant. The simplest calculation uses appropriate values
from the capacitance curves in a standard equation for voltage
change in an RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

The capacitance (Ciss) is read from the capacitance curve at a
voltage corresponding to the offstate condition when calcu-
lating td(on) and is read at a voltage corresponding to the on
state when calculating td(off).

At high switching speeds, parasitic circuit elements com-

plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.

The resistive switching time variation versus gate resis-

tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.

Figure 7. Capacitance Variation

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

C, CAP

ACIT

ANCE (pF)

VGS

VDS

TJ = 25

VDS = 0 V

VGS = 0 V

1400

1000

Ciss

Coss

Crss

Ciss

Crss

1800

1200

200

1600

400

600

800

MTD10N10EL

Motorola TMOS Power MOSFET Transistor Device Data

DRAINTOSOURCE DIODE CHARACTERISTICS

Figure 8. GateToSource and DrainToSource

Voltage versus Total Charge

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

Figure 10. Diode Forward Voltage versus Current

QG, TOTAL GATE CHARGE (nC)

, DRAINT

OSOURCE VOL

T
AGE (VOL

TS)

, GA

TET

OSOURCE VOL

T
AGE (VOL

TS)

TJ = 25

ID = 10 A

VGS

TIME (ns)

1000

100

RG, GATE RESISTANCE (OHMS)

TJ = 25

ID = 10 A
VDS = 100 V
VGS = 5 V

td(off)

td(on)

VDS

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

I S

, SOURCE CURRENT

(AMPS)

0.5

0.9

1.0

0.8

0.6

0.7

VGS = 0 V
TJ = 25

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25

C. Peak

repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, "Transient Thermal ResistanceGener-
al Data and Its Use."

Switching between the offstate and the onstate may tra-

verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10

s. In addition the total power aver-

aged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(R

JC).

A Power MOSFET designated EFET can be safely used

in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases nonlinearly with an in-
crease of peak current in avalanche and peak junction
temperature.

Although many EFETs can withstand the stress of drain

tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.

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