www.docs.chipfind.ru
* Although, all of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR block, proper layout techniques
should be applied for the design of the power supply board. The iPOWIR block will function normally, but not optimally without any additional input decoupling
capacitors. Input decoupling capacitors should be added at Vin pin for stable and reliable long term operation. See layout guidelines in datasheet for more
detailed information.
PD-94593C
10/28/04
iP1202
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1
5.5V to 13.2V input voltage
0.8V to 5V output voltage
2 Phase Synchronous Buck Power Block
180
out of phase operation
Single or Dual output capability
Dual 15A maximum load capability
Single 2 phase 30A maximum load capability
200-400kHz per channel nominal switching frequency
Over Current Hiccup or Over Current Latch
External Synchronization Capable
Overvoltage protection
Individual soft start per outputs
Over Temperature protection
Internal features minimize layout sensitivity *
Ease of layout
Very small outline 15.5mm x 9.25mm x 2.6mm
iP1202 Power Block
Features
Dual Output Full Function 2 Phase
Synchronous Buck Power Block
Integrated Power Semiconductors,
PWM Control & Passives
The iP1202 is a fully optimized solution for medium current synchronous buck applications requiring up to 15A
or 30A. The iP1202 is optimized for 2 phase single output applications up to 30A or dual output, each up to
15A with interleaved input. It includes full function PWM control, with optimized power semiconductor chip-sets
and associated passives, achieving high power density. Very few external components are required to create
a complete synchronous buck power supply.
iPOWIR technology offers designers an innovative space-saving solution for applications requiring high power
densities. iPOWIR technology eases design for applications where component integration offers benefits in
performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat
transfer and component selection.
Description
iP1202 Configurations
Dual Output
Single Output
V
IN
V
OUT
V
IN
V
OUT
Channel 1
Channel 2
V
OUT
Channel 1
Channel 2
V
IN
V
OUT
Channel 1
Channel 2
V
OUT
Channel 1
Channel 2
V
IN
V
OUT
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2
iP1202
Absolute Maximum Ratings
Recommended Operating Conditions
Electrical Specifications @ V
IN
= 12V
All specifications @ 25C (unless otherwise specified)
Parameter
Symbol
Min
Typ
Max
Units
Conditions
V
IN
V
IN
-0.3
-
15
Feedback
VFB1/VFB2
-0.3
-
6
Output Overvoltage Sense
VFB1
S
/VFB2
S
-0.3
-
6
PGOOD
-0.3
-
15
ENABLE
-0.3
-
15
Soft Start
SS1/SS2
-0.3
-
6
Vp-ref
-0.3
-
6
HICCUP
HICCUP
-0.3
-
15
SYNC
-0.3
-
6
Output RMS Current Per Channel
Iout
VSW
-
-
15
A
2 Independent outputs. See Fig. 3
Block Temperature
T
BLK
-40
-
125
C
Capable of start up over full temperature
range. See Note 1.
V
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Input Voltage Range
V
IN
5.5
-
13.2
-
-
15
A
2 Independent outputs
T
PCB
= T
CASE
= 90C. See Fig. 3
-
-
11
A
2 Independent outputs
T
PCB
= 90C, T
CASE
= no airflow, no
heatsink. See Fig. 3
0.8
-
5.0
For V
IN
= 12V
0.8
-
3.3
For V
IN
= 5.5V
Output Voltage Range
V
OUT
V
Output RMS Current Per Channel
Iout
VSW
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Over Current Shutdown
I
OC
-
25
-
A
V
IN
= 12V, V
OUT
= 1.5V
f
SW
= 300KHz, R
OCSET
= 51.1k
HICCUP pin pulled Low
HICCUP duty cycle
D
HICCUP
-
5
-
%
HICCUP pin pulled high, output short
circuited.
Soft Start Time
t
SS
5
ms
V
IN
= 12V, V
OUT
= 1.5V,
C
SS1
= C
SS2
=0.1F
Reference Voltage
V
REF
-
0.8
-
V
V
OUT_ACC1
-3
-
3
T
BLK
= -40C to 125C, See Note 1.
V
IN
= 12V, V
OUT
= 1.5V
V
OUT_ACC2
-2.5
-
2.5
T
BLK
= 0C to 125C, See Note 1.
V
IN
= 12V, V
OUT
= 1.5V
Error Amplifier 2 input offset
voltage
V
OS2
-4
-
4
mV
V
IN
= 12V, V
OUT
= 1.5V, specified for
current share accuracy in parallel
configuration. R
shunt1
= R
shunt2
=5m
,
Iout= 30A. See Fig. 15
FB1/FB2 Input bias current
I
BFB
-
-0.1
-
A
Error Amplifier
source/sink Current
I
ERR
-
60
-
A
Error Amplifier
Transconductance
g
m1,
g
m2
-
2000
-
mho
Output Overvoltage Shutdown
Threshold
OVP
-
1.15 x V
OUT
-
V
See OVP note in Design Guidelines
OVP Fault Propagation Delay
t
OVP
-
25
-
s
Output forced to 1.125Vref
PGOOD Trip Threshold
V
Th_PGOOD
-
0.85 x V
OUT
V
FB1 or FB2 ramping down
PGOOD Output Low Voltage
V
LO_PGOOD
-
0.25
-
V
I
SINK
=2mA
f
SW =
300kHz, V
IN
= 12V, T
BLK
= 25C
V
OUT1
= V
OUT2
= 1.5V, I
OUT1
= I
OUT2
= 15A
-
7.0
8.75
%
V
OUT
Accuracy
W
P
LOSS
Power Loss
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3
iP1202
Electrical Specifications (continued)
Note 1: Guaranteed to meet specifications from T
BLK
= 0C to 90C. Specifications outside of this tempera-
ture range are guaranteed by design, and not production tested.
Parameter
Symbol
Min
Typ
Max
Units
Conditions
170
-
230
kHz
R
T
= 48.7k
( See Fig.9 for
Frequency
f
SW
255
-
345
kHz
R
T
= 30.9k
R
T
selection )
340
-
460
kHz
R
T
= 21.5k
Oscillator Ramp Voltage
V
ramp
-
1.25
-
V
SYNC Frequency Range
f
SYNC
480
-
800
kHz
Free running frequency
set 20% below sync frequency
SYNC Pulse Duration
t
SYNC
-
200
-
ns
SYNC, HICCUP High Level
Threshold Voltage
2
-
-
V
SYNC, HICCUP Low Level
Threshold Voltage
-
-
0.8
V
V
IN
Quiescent Current
I
IN-LEAKAGE
-
15
-
mA
V
IN
= 12V, ENABLE high
Thermal Shutdown
Temp
shdn
-
140
-
C
Max Duty Cycle
D
MAX
85
-
-
%
f
SW
= 200kHz, T
BLK
= 25C
ENABLE Threshold Voltage
V
EN-LO
5
-
-
V
Measured between V
IN
and ENABLE
V
IN
Turn On Threshold Voltage
V
ON_th
-
4.8
-
V
Measured at start of soft start, ENABLE
pulled low, V
IN
ramping up
V
IN
Turn Off Threshold Voltage
V
OFF_th
-
4.3
-
V
Measured at fall of soft start, ENABLE
pulled low, V
IN
ramping down
Output Disable Voltage Soft
Start Low Threshold Voltage
V
SS-DIS
-
-
0.25
V
SS1 / SS2 Pins Pulled Low
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4
iP1202
Fig. 1: iP1202 Internal Block Diagram
H
i
ccu
p
C
ont
r
o
l
OC
La
t
c
h
/
P
G
ood
OVP
(
-
10%
)
(
+
15%
)
Bi
as
Ge
n
e
r
a
t
o
r
SS1
SS2
O
C
SET1
O
C
SET2
HI
CCUP
FB
1
CC1
S
YNC
RT
VRE
F
VP
-
R
E
F
FB
2
CC2
FB
1
S
FB
2
S
25uA
25uA
25k
25k
25k
25k
Erro
r A
m
p
1
Erro
r A
m
p
2
0.
8V
T
w
o phase
O
s
c
illa
t
o
r
PW
M
C
o
m
p
1
PW
M
C
o
m
p
2
R
S
Q
R
S
Q
Ra
m
p
1
Ra
m
p
2
SW
1 /
SW
3 O
F
F
SW
2 /
SW
4 O
N
EN
A
B
L
E
P
GOOD
VS
W
1
SW
2
SW
1
SW
4
SW
3
0.
8V
VCC
VS
W
2
20k
UV
L
O
20k
3uA
3uA
VI
N
Dri
v
e
r
1
Dri
v
e
r
2
PW
M
1
PW
M
2
P
GND
64uA
64uA
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5
iP1202
Fig. 2: Power Loss vs. Current
Fig. 3: Safe Operating Area (SOA) vs. T
PCB
& T
CASE
0
10
20
30
40
50
60
70
80
90
100
120
110
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
10
20
30
40
50
60
70
80
90
100
110
120
PCB Temperature (C)
Out
put
C
u
r
r
e
n
t
P
e
r
C
h
a
nne
l
(
A
)
Case Temperature (
&
T
X
V
IN
= 12V
V
OUT 1
= V
OUT 2
= 1.5V
I
OUT
= 15A
f
SW
= 300kHz
L = 1.0H
Safe
Operating
Area
0
1
2
3
4
5
6
7
8
9
10
11
12
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Output Current per Channel (A)
Tot
a
l
P
o
w
e
r
Lo
s
s
,
B
o
t
h
O
u
t
put
s
(
W
)
V
IN
= 12V
V
OUT 1
= V
OUT 2
= 1.5V
f
SW
= 300kHz
L = 1.0H
T
BLK
= 125C
M aximum
T ypical
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