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ADVANCE INFORMATION Data Sheet PD 60178A
IR1175
Package
Synchronous Rectifier Driver
Features
n
Provides constant and proper gate drive to power
MOSFETs regardless of transformer output
n
Minimizes loss due to power MOSFET body
drain diode conduction
n
Stand alone operation - no ties to primary side
n
Schmitt trigger input with double pulse suppress-
ion allows operation in noisy environments
n
High current drive capability - 2A
n
High speed operation - 2MHz
n
Adaptable to multiple topologies (such as single-
ended forward, double-ended forward)
Description
The IR1175 is a high speed CMOS controller designed
to drive N-channel power MOSFETs used as synchro-
nous rectifiers in high current, high frequency forward
converters with output voltages equal or below 5V
DC
.
Schmitt trigger inputs with double pulse suppression
allow the controller to operate in noisy environments.
The circuit does not require any ties to the primary
side and derives its operating power directly from
the secondary. The circuit functions by anticipating
transformer output transitions, then turns the power
MOSFETs on or off before the transitions of the trans-
former to minimize body drain diode conduction and
reduce associated losses. Turn on/off lead time can
be adjusted to accommodate a variety of power
MOSFET sizes and circuit conditions. The IR1175 also
provides gate drive overlap/dead-time control via
external components to further minimize diode con-
duction by nulling effects of secondary loop and de-
vice package inductance.
20 Lead Surface Mount (SSOP-20)
V
dd
5Vdc
I
O+/-
2A/2A
F
max
2MHz
Max lead time
500nsec
Product Summary
2
IR1175
ADVANCE INFORMATION
www.irf.com
Symbol Definition
Min.
Max.
Units
V
dd
Supply voltage
--
7
V
DC
I
in
Input clamp current
--
+/- 10
mA
DC
P
D
Power dissipation (SSOP-20)
--
400
mW
Rth
JC
Thermal resistance (SSOP-20) junction-to-case
--
28.5
C/W
Rth
JA
Thermal resistance (SSOP-20) junction-to-ambient
--
90.5
C/W
T
J
Junction temperature
--
150
C
T
S
Storage temperature
-55
150
C
T
L
Lead temperature (soldering, 10 seconds)
--
300
C
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur.
Symbol Definition
Min.
Typ.
Max.
Units
Vdd
Supply voltage operating range
--
5
--
V
DC
T
A
Ambient temperature
-40
--
85
C
Freq
Operating frequency
250
--
500
KHz
Rbias
Required bias resistor (+/- 1%)
--
69.8
--
K
W
UV
Voltage at UVSET pin
1.75
--
2.25
V
DC
Xin
Maximum voltage at X1 and X2 inputs
--
--
5.6
V
DC
Cd1/Cd2
Capacitance at pins DTIN1 and DTIN2
--
--
22
pF
Cf
Loop filter bypass capacitor
470
--
--
K
W
Recommended Operating Conditions
3
IR1175
ADVANCE INFORMATION
www.irf.com
Dynamic Electrical Characteristics
Vdd=5V, T
A
= 25
o
C, Rbias = 69.8K unless otherwise specified.
Symbol Definition
Min.
Typ.
Max.
Units
Vdd
Supply voltage operating range
4.0
--
5.5
V
DC
Iqdd
Vdd quiescent current (Vin=0 or 5V, Iout=0)
--
3
5
mA
DC
Freq
Operating frequency
100
--
2000
KHz
UVSET+
UVSET positive going threshold
1.10
--
1.4
V
UVSET-
UVSET negative going threshold
0.8
--
1.1
V
Vxth+
X1/X2 Input positive going threshold
--
1.4
--
V
DC
Vxth-
X1/X2 Input negative going threshold
--
1.0
--
V
DC
Tadv
Externally adjustable lead time (advance)
--
--
500
nsec
Td
Externally adjustable dead-time for Q1 and Q2
20
--
--
nsec
Isink
Q1,Q2 output sink current (Vdd=5.0V,
--
--
2
A
pulsed, 10 usec)
Isource
Q1,Q2 output source current (Vdd=5.0V,
--
--
2
A
pulsed, 10 usec)
tio
Input to output delay (PLL bypassed, cross coupled
--
20
--
nsec
mode)
tr
Gate turn-on rise time (C1=1000pf, Vdd=5V)
--
20
--
nsec
tf
Gate turn-off fall time (C1=1000pf, Vdd=5V)
--
20
--
nsec
Vtr
Cross-over voltage (Vdd=5Vdc, DTIN shorted to
--
2.5
--
V
DC
DTOUT, C1=1000pf) Fig. 3
Rbias
Required bias resistor
68
--
71
K
W
Vbias
Voltage at Rbias pin
--
1.25
--
V
DC
Tjitter
Phase-lock loop output jitter
-20
--
20
nsec
Ichgpump
Charge pump output current (at VFLTR pin)
--
50
--
m
A
DC
Vchgpump
Charge pump output voltage (at VFLTR pin)
1.3
1.5
1.7
V
DC
Kvco_dc
PLL Vco DC gain
--
62
--
KHz/
4
IR1175
ADVANCE INFORMATION
www.irf.com
Lead Definitions and Assignments
Symbol Description
AVDD
Power - + 5 V
DC
to MOSFET drivers
Q1
Output - gate drive for Q1 power MOSFET
DTOUT1
Output - sets dead time for Q1 output - used with DTIN1
DTIN1
Input - sets dead time for Q1 - used with DTOUT1
RADV1
Output - sets lead time (advance) for Q1
VFLTR1
Output - PLL loop filter for Q1 output
RVCO1
Output - sets PLL center frequency for Q1 output
X1
Input - transformer input for Q1
VDD
Power - +5 Vdc for internal logic
UVSET
Input - sets UVLO+
If this pin is pulled below 1.25VDC externally, then both Q1 and Q2
outputs will be at Vss (disabled)
RBIAS
Output - connected to 249K +/- 1% resistor - sets operating current
AVSS
Ground for logic supply (AVDD)
X2
Input - transformer input for Q2
RVCO2
Output - sets PLL center frequency for Q2 output
VFLTR2
Output - PLL loop filter for Q2
RADV2
Output - sets lead time (advance) for Q2
DTIN2
Input - sets dead time for Q2 - used with DTOUT2
DTOUT2
Output - sets dead time for Q2 - used with DTIN2
VSS
Ground for MOSFET driver supply (VDD)
Q2
Output - gate drive for Q2 power MOSFET
20
19
18
4
3
2
1
DTOUT2
VFLTRI
DTIN2
RADV1
VFLTR2
DTIN1
DTOUT1
RADV2
17
5
7
6
8
16
15
14
13
RVCO1
X1
RVCO2
X2
VSS
Q2
*VDD
Q1
9
10
12
11
AVDD
UVSET
AVSS
RBIAS
20 Lead SSOP
IR1175
5
IR1175
ADVANCE INFORMATION
www.irf.com
Fig. 1 Typical application circuit when supply Vout < 5.0 V
DC
Fig. 2 Typical application circuit when supply Vout = 5.0 V
DC
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