Features
Floating channel designed for bootstrap operation
Fully operational up to +200V
Tolerant to negative transient voltage, dV/dt immune
Gate drive supply range from 10V to 20V
Independent low and high side channels
Input logicHIN/LIN active high
Undervoltage lockout for both channels
3.3V and 5V input logic compatible
CMOS Schmitt-triggered inputs with pull-down
Matched propagation delay for both channels
8-Lead SOIC is also available LEAD-FREE (PbF)
Packages
HIGH AND LOW SIDE DRIVER
Product Summary
V
OFFSET
200V max.
I
O
+/-
1.0A /1.0A typ.
V
OUT
10 - 20V
t
on/off
80 & 60 ns typ.
Delay Matching
20 ns max.
IR2011(
S) & (PbF
)
www.irf.com
1
Typical Connection
(Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please
refer to our Application Notes and DesignTips for proper circuit board layout.
Data Sheet No.PD60217 Rev A
Applications
Audio Class D amplifiers
High power DC-DC SMPS converters
Other high frequency applications
Description
The IR2011 is a high power, high speed power MOSFET driver with independent high
and low side referenced output channels, ideal for Audio Class D and DC-DC converter
applications. Logic inputs are compatible with standard CMOS or LSTTL output, down
to 3.0V logic. The output drivers feature a high pulse current buffer stage designed for
minimum driver cross-conduction. Propagation delays are matched to simplify use in
high frequency applications. The floating channel can be used to drive an N-channel
power MOSFET in the high side configuration which operates up to 200 volts. Propri-
etary HVIC and latch immune CMOS technologies enable ruggedized monolithic con-
struction.
8-Lead SOIC
IR2011S
also available
LEAD-FREE (PbF)
8-Lead PDIP
IR2011
200V
TO
LOAD
V
CC
COM
LIN
HIN
V
S
V
B
HO
HIN
COM
V
CC
LIN
LO
1
8
4
5
2
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IR2011(S) & (PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
V
B
High side floating supply voltage
-0.3
250
V
S
High side floating supply offset voltage
V
B
- 25
V
B
+ 0.3
V
HO
High side floating output voltage
V
S
- 0.3
V
B
+ 0.3
V
CC
Low side fixed supply voltage
-0.3
25
V
LO
Low side output voltage
-0.3
V
CC
+0.3
V
IN
Logic input voltage (HIN & LIN)
COM -0.3
V
CC
+0.3
dV
s
/dt
Allowable offset supply voltage transient (figure 2)
--
50
V/ns
P
D
Package power dissipation @ T
A
+25
C
(8-lead DIP)
--
1.0
(8-lead SOIC)
--
0.625
R
THJA
Thermal resistance, junction to ambient
(8-lead DIP)
--
125
(8-lead SOIC)
--
200
T
J
Junction temperature
--
150
T
S
Storage temperature
-55
150
T
L
Lead temperature (soldering, 10 seconds)
--
300
C/W
W
V
C
Note 1: Logic operational for V
S
of -4 to +200V. Logic state held for V
S
of -4V to -V
BS
.
Symbol
Definition
Min.
Max.
Units
V
B
High side floating supply absolute voltage
V
S
+ 10
V
S
+ 20
V
S
High side floating supply offset voltage
Note 1
200
V
HO
High side floating output voltage
V
S
V
B
V
CC
Low side fixed supply voltage
10
20
V
LO
Low side output voltage
0
V
CC
V
IN
Logic input voltage (HIN & LIN)
COM
5.5
T
A
Ambient temperature
-40
125
C
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. The VS and COM offset ratings
are tested with all supplies biased at 15V differential.
V
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3
IR2011(S) & (PbF)
Symbol
Definition
Min. Typ. Max. Units Test Conditions
V
IH
Logic "1" input voltage
2.2
--
--
V
IL
Logic "0" input voltage
--
--
0.7
V
OH
High level output voltage, V
BIAS
- V
O
--
--
2.0
I
O
= 0A
V
OL
Low level output voltage, V
O
--
--
0.2
20mA
I
LK
Offset supply leakage current
--
--
50
V
B
=V
S
= 200V
I
QBS
Quiescent V
BS
supply current
--
90
210
V
IN
= 0V or 3.3V
I
QCC
Quiescent V
CC
supply current
--
140
230
V
IN
= 0V or 3.3V
I
IN+
Logic "1" input bias current
--
7.0
20
V
IN
= 3.3V
I
IN-
Logic "0" input bias current
--
--
1.0
V
IN
= 0V
V
BSUV+
V
BS
supply undervoltage positive going
8.2
9.0
9.8
threshold
V
BSUV-
V
BS
supply undervoltage negative going
7.4
8.2
9.0
threshold
V
CCUV+
V
CC
supply undervoltage positive going
8.2
9.0
9.8
threshold
V
CCUV-
V
CC
supply undervoltage negative going
7.4
8.2
9.0
threshold
I
O+
Output high short circuit pulsed current
--
1.0
--
V
O
= 0V,
PW
10
s
I
O-
Output low short circuit pulsed current
--
1.0
--
V
O
= 15V,
PW
10
s
V
A
V
A
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V, and T
A
= 25
C
unless otherwise specified. The V
IN
, V
TH
and I
IN
parameters are referenced to
COM and are applicable to all logic input leads: HIN and LIN. The V
O
and I
O
parameters are referenced to COM and are
applicable to the respective output leads: HO or LO.
V
CC
= 10V - 20V
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V, C
L
= 1000 pF, T
A
= 25
C unless otherwise specified. Figure 1 shows the timing definitions.
Symbol
Definition
Min. Typ. Max. Units Test Conditions
t
on
Turn-on propagation delay
--
80
--
V
S
= 0V
t
off
Turn-off propagation delay
--
75
--
V
S
= 200V
t
r
Turn-on rise time
--
35
50
t
f
Turn-off fall time
--
20
35
DM1
Turn-on delay matching | t
on
(H) - t
on
(L) |
--
5
20
DM2
Turn-off delay matching | t
off
(H) - t
off
(L) |
--
5
20
ns
4
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IR2011(S) & (PbF)
Functional Block Diagram
Lead Definitions
Symbol Description
8-Lead PDIP
8-Lead SOIC also available LEAD-FREE (PbF)
IR2011
IR2011S
Part Number
Lead Assignments
HIN
Logic input for high side gate driver output (HO), in phase
LIN
Logic input for low side gate driver output (LO), in phase
V
B
High side floating supply
HO
High side gate drive output
V
S
High side floating supply return
V
CC
Low side supply
LO
Low side gate drive output
COM
Low side return
V
B
LIN
UV
DETECT
DELAY
V
CC
UV
DETECT
LO
V
S
COM
S
R
UV
Q
HIN
HO
LEVEL
SHIFT
CIRCUIT
LOW
VOLTAGE
LEVEL
SHIFT
3V S-TRIGGER
3V S-TRIGGER
HIGH
VOLTAGE
BUFFER
LOW
VOLTAGE
LEVEL
SHIFT
V
S
V
B
HO
HIN
COM
V
CC
LIN
LO
1
8
4
5
6
7
3
2
V
S
V
B
HO
HIN
COM
V
CC
LIN
LO
1
8
4
5
6
7
3
2
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5
IR2011(S) & (PbF)
Figure 1. Timing Diagram
50%
50%
10%
90%
10%
90%
10%
90%
HIN / LIN
HO
LO
t
rise
t
fall
t
on
(H)
t
on
(L)
t
off
(H)
t
off
(L)
DM1
DM2
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