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V
CC
V
B
V
S
HO
LO
IN
COM
IN
up to 600V
TO
LOAD
V
CC
Features
n
Floating channel designed for bootstrap operation
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
n
Gate drive supply range from 10 to 20V
n
Undervoltage lockout for both channels
n
CMOS Schmitt-triggered inputs with pull-down
n
Matched propagation delay for both channels
n
Internally set deadtime
n
High side output in phase with input
Description
The IR2111 is a high voltage, high speed power
MOSFET and IGBT driver with dependent high and
low side referenced output channels designed for
half-bridge applications. Proprietary HVIC and latch
immune CMOS technologies enable ruggedized
monolithic construction. Logic input is compatible
with standard CMOS outputs. The output drivers
feature a high pulse current buffer stage designed
for minimum driver cross-conduction. Internal
deadtime is provided to avoid shoot-through in the
output half-bridge. The floating channel can be used
to drive an N-channel power MOSFET or IGBT in
the high side configuration which operates up to
600 volts.
Typical Connection
Data Sheet No. PD-6.028C
IR2111
HALF-BRIDGE DRIVER
Product Summary
V
OFFSET
600V max.
I
O
+/-
200 mA / 420 mA
V
OUT
10 - 20V
t
on/off
(typ.)
850 & 150 ns
Deadtime (typ.)
700 ns
Packages
C
ONTROL
I
NTEGRATED
C
IRCUIT
D
ESIGNERS
M
ANUAL
B-39
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IR2111
B-40 C
ONTROL
I
NTEGRATED
C
IRCUIT
D
ESIGNERS
M
ANUAL
Parameter
Value
Symbol
Definition
Min.
Max.
Units
V
B
High Side Floating Supply Voltage
-0.3
625
V
S
High Side Floating Supply Offset Voltage
V
B
- 25
V
B
+ 0.3
V
HO
High Side Floating Output Voltage
V
S
- 0.3
V
B
+ 0.3
V
CC
Low Side and Logic Fixed Supply Voltage
-0.3
25
V
LO
Low Side Output Voltage
-0.3
V
CC
+ 0.3
V
IN
Logic Input Voltage
-0.3
V
CC
+ 0.3
dV
s
/dt
Allowable Offset Supply Voltage Transient (Figure 2)
--
50
V/ns
P
D
Package Power Dissipation @ T
A
+25C
(8 Lead DIP)
--
1.0
(8 Lead SOIC)
--
0.625
R
JA
Thermal Resistance, Junction to Ambient
(8 Lead DIP)
--
125
(8 Lead SOIC)
--
200
T
J
Junction Temperature
--
150
T
S
Storage Temperature
-55
150
C
T
L
Lead Temperature (Soldering, 10 seconds)
--
300
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are
absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board
mounted and still air conditions. Additional information is shown in Figures 7 through 10.
V
W
C/W
Parameter
Value
Symbol
Definition
Min.
Max.
Units
V
B
High Side Floating Supply Absolute Voltage
V
S
+ 10
V
S
+ 20
V
S
High Side Floating Supply Offset Voltage
Note 1
600
V
HO
High Side Floating Output Voltage
V
S
V
B
V
CC
Low Side and Logic Fixed Supply Voltage
10
20
V
LO
Low Side Output Voltage
0
V
CC
V
IN
Logic Input Voltage
0
V
CC
T
A
Ambient Temperature
-40
125
Note 1: Logic operational for V
S
of -5 to +600V. Logic state held for V
S
of -5V to -V
BS
.
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. The V
S
offset rating is tested with all supplies biased at 15V differential.
C
V
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IR2111
C
ONTROL
I
NTEGRATED
C
IRCUIT
D
ESIGNERS
M
ANUAL
B-41
Parameter
Value
Symbol
Definition
Min.
Typ. Max. Units Test Conditions
t
on
Turn-On Propagation Delay
--
850
1,000
V
S
= 0V
t
off
Turn-Off Propagation Delay
--
150
180
V
S
= 600V
t
r
Turn-On Rise Time
--
80
130
t
f
Turn-Off Fall Time
--
40
65
DT
Deadtime, LS Turn-Off to HS Turn-On &
--
700
900
HS Turn-Off to LS Turn-On
MT
Delay Matching, HS & LS Turn-On/Off
--
30
--
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V, C
L
= 1000 pF and T
A
= 25C unless otherwise specified. The dynamic electrical characteristics
are measured using the test circuit shown in Figure 3.
ns
Parameter
Value
Symbol
Definition
Min.
Typ. Max. Units Test Conditions
V
IH
Logic "1" Input Voltage for HO & Logic "0" for LO
6.4
--
--
V
CC
= 10V
9.5
--
--
V
CC
= 15V
12.6
--
--
V
CC
= 20V
V
IL
Logic "0" Input Voltage for HO & Logic "1" for LO
--
--
3.8
V
CC
= 10V
--
--
6.0
V
CC
= 15V
--
--
8.3
V
CC
= 20V
V
OH
High Level Output Voltage, V
BIAS
- V
O
--
--
100
I
O
= 0A
V
OL
Low Level Output Voltage, V
O
--
--
100
I
O
= 0A
I
LK
Offset Supply Leakage Current
--
--
50
V
B
= V
S
= 600V
I
QBS
Quiescent V
BS
Supply Current
--
50
100
V
IN
= 0V or V
CC
I
QCC
Quiescent V
CC
Supply Current
--
70
180
A
V
IN
= 0V or V
CC
I
IN+
Logic "1" Input Bias Current
--
20
40
V
IN
= V
CC
I
IN-
Logic "0" Input Bias Current
--
--
1.0
V
IN
= 0V
V
BSUV+
V
BS
Supply Undervoltage Positive Going Threshold
7.3
8.4
9.5
V
BSUV-
V
BS
Supply Undervoltage Negative Going Threshold
7.0
8.1
9.2
V
CCUV+
V
CC
Supply Undervoltage Positive Going Threshold
7.6
8.6
9.6
V
CCUV-
V
CC
Supply Undervoltage Negative Going Threshold
7.2
8.2
9.2
I
O+
Output High Short Circuit Pulsed Current
200
250
--
V
O
= 0V, V
IN
= V
CC
PW
10 s
I
O-
Output Low Short Circuit Pulsed Current
420
500
--
V
O
= 15V, V
IN
= 0V
PW
10 s
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V and T
A
= 25C unless otherwise specified. The V
IN
, V
TH
and I
IN
parameters are referenced to
COM. The V
O
and I
O
parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
V
mV
mA
V
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IR2111
B-42 C
ONTROL
I
NTEGRATED
C
IRCUIT
D
ESIGNERS
M
ANUAL
Lead Definitions
Lead
Symbol
Description
IN
Logic input for high side and low side gate driver outputs (HO & LO), in phase with HO
V
B
High side floating supply
HO
High side gate drive output
V
S
High side floating supply return
V
CC
Low side and logic fixed supply
LO
Low side gate drive output
COM
Low side return
Functional Block Diagram
8 Lead DIP
SO-8
IR2111
IR2111S
Part Number
Lead Assignments
P U L S E
G E N
IN
U V
D E T E C T
C O M
H O
V
S
V
C C
L O
V
B
Q
S
R
R
P U L S E
F I L T E R
H V
L E V E L
S H I F T
D E A D
T I M E
D E A D
T I M E
U V
D E T E C T
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IR2111
C
ONTROL
I
NTEGRATED
C
IRCUIT
D
ESIGNERS
M
ANUAL
B-43
Thickness of Gate Oxide
800
Connections
Material
Poly Silicon
First
Width
4 m
Layer
Spacing
6 m
Thickness
5000
Material
Al - Si (Si: 1.0% 0.1%)
Second
Width
6 m
Layer
Spacing
9 m
Thickness
20,000
Contact Hole Dimension
8 m X 8 m
Insulation Layer
Material
PSG (SiO
2
)
Thickness
1.5 m
Passivation
Material
PSG (SiO
2
)
Thickness
1.5 m
Method of Saw
Full Cut
Method of Die Bond
Ablebond 84 - 1
Wire Bond
Method
Thermo Sonic
Material
Au (1.0 mil / 1.3 mil)
Leadframe
Material
Cu
Die Area
Ag
Lead Plating
Pb : Sn (37 : 63)
Package
Types
8 Lead PDIP / SO-8
Materials
EME6300 / MP150 / MP190
Remarks:
Device Information
Process & Design Rule
HVDCMOS 4.0 m
Transistor Count
164
Die Size
70 X 96 X 26 (mil)
Die Outline
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