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Электронный компонент: IR2113-2

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Features
Floating channel designed for bootstrap operation
Fully operational to +500V or +600V
Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 10 to 20V
Undervoltage lockout for both channels
3.3V logic compatible
Separate logic supply range from 3.3V to 20V
Logic and power ground 5V offset
CMOS Schmitt-triggered inputs with pull-down
Cycle by cycle edge-triggered shutdown logic
Matched propagation delay for both channels
Outputs in phase with inputs
Description
The IR2110/IR2113 are high voltage, high speed power
MOSFET and IGBT drivers with independent high and
low side referenced output channels. Proprietary HVIC
and latch immune CMOS technologies enable rugge-
dized monolithic construction. Logic inputs are com-
patible with standard CMOS or LSTTL output, down to
3.3V logic. The output drivers feature a high pulse cur-
Packages
Data Sheet No. PD60147-S
HIGH AND LOW SIDE DRIVER
Product Summary
V
OFFSET
(IR2110)
500V max.
(IR2113)
600V max.
I
O
+/-
2A / 2A
V
OUT
10 - 20V
t
on/off
(typ.)
120 & 94 ns
Delay Matching (IR2110) 10 ns max.
(IR2113) 20ns max.
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1
rent buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use
in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT
in the high side configuration which operates up to 500 or 600 volts.
IR2110/IR2113(
S
)
14-Lead PDIP
IR2110/IR2113
16-Lead SOIC
IR2110S/IR2113S
HIN
up to 500V or 600V
TO
LOAD
V
DD
V
B
V
S
HO
LO
COM
HIN
LIN
V
SS
SD
V
CC
LIN
V
DD
SD
V
SS
V
CC
(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical
connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
Typical Connection
2
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IR2110/IR2113 (
S
)
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical
ratings at other bias conditions are shown in figures 36 and 37.
Note 1: Logic operational for V
S
of -4 to +500V. Logic state held for V
S
of -4V to -V
BS
. (Please refer to the Design Tip
DT97-3 for more details).
Note 2: When V
DD
< 5V, the minimum V
SS
offset is limited to -V
DD.
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.
Symbol
Definition
Min.
Max.
Units
V
B
High side floating supply voltage (IR2110)
-0.3
525
(IR2113)
-0.3
625
V
S
High side floating supply offset voltage
V
B
- 25
V
B
+ 0.3
V
HO
High side floating output voltage
V
S
- 0.3
V
B
+ 0.3
V
CC
Low side fixed supply voltage
-0.3
25
V
LO
Low side output voltage
-0.3
V
CC
+ 0.3
V
DD
Logic supply voltage
-0.3
V
SS
+ 25
V
SS
Logic supply offset voltage
V
CC
- 25
V
CC
+ 0.3
V
IN
Logic input voltage (HIN, LIN & SD)
V
SS
- 0.3
V
DD
+ 0.3
dV
s
/dt
Allowable offset supply voltage transient (figure 2)
--
50
V/ns
P
D
Package power dissipation @ T
A
+25
C
(14 lead DIP)
--
1.6
(16 lead SOIC)
--
1.25
R
THJA
Thermal resistance, junction to ambient
(14 lead DIP)
--
75
(16 lead SOIC)
--
100
T
J
Junction temperature
--
150
T
S
Storage temperature
-55
150
T
L
Lead temperature (soldering, 10 seconds)
--
300
C/W
W
V
C
Symbol
Definition
Min.
Max.
Units
V
B
High side floating supply absolute voltage
V
S
+ 10
V
S
+ 20
V
S
High side floating supply offset voltage (IR2110)
Note 1
500
(IR2113)
Note 1
600
V
HO
High side floating output voltage
V
S
V
B
V
CC
Low side fixed supply voltage
10
20
V
LO
Low side output voltage
0
V
CC
V
DD
Logic supply voltage
V
SS
+ 3
V
SS
+ 20
V
SS
Logic supply offset voltage
-5 (Note 2)
5
V
IN
Logic input voltage (HIN, LIN & SD)
V
SS
V
DD
T
A
Ambient temperature
-40
125
C
V
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3
IR2110/IR2113 (
S
)
Symbol
Definition
Figure Min. Typ. Max. Units Test Conditions
t
on
Turn-on propagation delay
7
--
120
150
V
S
= 0V
t
off
Turn-off propagation delay
8
--
94
125
V
S
= 500V/600V
t
sd
Shutdown propagation delay
9
--
110
140
V
S
= 500V/600V
t
r
Turn-on rise time
10
--
25
35
t
f
Turn-off fall time
11
--
17
25
MT
Delay matching, HS & LS (IR2110)
--
--
--
10
turn-on/off
(IR2113)
--
--
--
20
ns
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
, V
DD
) = 15V, C
L
= 1000 pF, T
A
= 25
C and V
SS
= COM unless otherwise specified. The dynamic
electrical characteristics are measured using the test circuit shown in Figure 3.
Symbol
Definition
Figure Min. Typ. Max. Units Test Conditions
V
IH
Logic "1" input voltage
12
9.5
--
--
V
IL
Logic "0" input voltage
13
--
--
6.0
V
OH
High level output voltage, V
BIAS
- V
O
14
--
--
1.2
I
O
= 0A
V
OL
Low level output voltage, V
O
15
--
--
0.1
I
O
= 0A
I
LK
Offset supply leakage current
16
--
--
50
V
B
=V
S
= 500V/600V
I
QBS
Quiescent V
BS
supply current
17
--
125
230
V
IN
= 0V or V
DD
I
QCC
Quiescent V
CC
supply current
18
--
180
340
V
IN
= 0V or V
DD
I
QDD
Quiescent V
DD
supply current
19
--
15
30
V
IN
= 0V or V
DD
I
IN+
Logic "1" input bias current
20
--
20
40
V
IN
= V
DD
I
IN-
Logic "0" input bias current
21
--
--
1.0
V
IN
= 0V
V
BSUV+
V
BS
supply undervoltage positive going
22
7.5
8.6
9.7
threshold
V
BSUV-
V
BS
supply undervoltage negative going
23
7.0
8.2
9.4
threshold
V
CCUV+
V
CC
supply undervoltage positive going
24
7.4
8.5
9.6
threshold
V
CCUV-
V
CC
supply undervoltage negative going
25
7.0
8.2
9.4
threshold
I
O+
Output high short circuit pulsed current
26
2.0
2.5
--
V
O
= 0V, V
IN
= V
DD
PW
10
s
I
O-
Output low short circuit pulsed current
27
2.0
2.5
--
V
O
= 15V, V
IN
= 0V
PW
10
s
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
, V
DD
) = 15V, T
A
= 25
C and V
SS
= COM
unless otherwise specified. The V
IN
, V
TH
and I
IN
parameters
are referenced to V
SS
and are applicable to all three logic input leads: HIN, LIN and SD. The V
O
and I
O
parameters are
referenced to COM and are applicable to the respective output leads: HO or LO.
V
A
V
A
4
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IR2110/IR2113 (
S
)
Functional Block Diagram
Lead Definitions
Symbol Description
14 Lead PDIP
16 Lead SOIC (Wide Body)
IR2110/IR2113
IR2110S/IR2113S
Part Number
V
B
SD
LIN
V
DD
PULSE
GEN
R
S
Q
V
SS
UV
DETECT
DELAY
HV
LEVEL
SHIFT
V
CC
PULSE
FILTER
UV
DETECT
V
DD
/V
CC
LEVEL
SHIFT
V
DD
/V
CC
LEVEL
SHIFT
LO
V
S
COM
R
S
Q
R
S
R
Q
HIN
HO
V
DD
Logic supply
HIN
Logic input for high side gate driver output (HO), in phase
SD
Logic input for shutdown
LIN
Logic input for low side gate driver output (LO), in phase
V
SS
Logic ground
V
B
High side floating supply
HO
High side gate drive output
V
S
High side floating supply return
V
CC
Low side supply
LO
Low side gate drive output
COM
Low side return
Lead Assignments
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5
IR2110/IR2113 (
S
)
Figure 1. Input/Output Timing Diagram
Figure 2. Floating Supply Voltage Transient Test Circuit
Figure 3. Switching Time Test Circuit
Figure 4. Switching Time Waveform Definition
Figure 6. Delay Matching Waveform Definitions
Figure 5. Shutdown Waveform Definitions
HIN
LIN
tr
ton
tf
toff
HO
LO
50%
50%
90%
90%
10%
10%
HIN
LIN
HO
50%
50%
10%
LO
90%
MT
HO
LO
MT
SD
tsd
HO
LO
50%
90%
10
F
0.1
F
V =15V
cc
9
3
6
5
7
1
2
13
12
11
10
HIN
SD
LIN
HO
LO
0.1
F
10
F
10
F
CL
CL
VB
+
-
S
V
(0 to 500V/600V)
15V
10
F
0.1
F
V =15V
cc
9
3
6
5
7
1
2
13
12
11
10
HO
0.1
F
OUTPUT
MONITOR
10KF6
10KF6
200
H
10KF6
100
F
+
IRF820
HV = 10 to 500V/600V
dVS
>50 V/ns
dt