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Электронный компонент: IRFE120

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Absolute Maximum Ratings
Parameter
Units
ID @ VGS = 10V, TC = 25C
Continuous Drain Current
4.5
ID @ VGS = 10V, TC = 100C
Continuous Drain Current
3.0
IDM
Pulsed Drain Current
1 8
PD @ TC = 25C
Max. Power Dissipation
1 4
W
Linear Derating Factor
0.11
W/C
VGS
Gate-to-Source Voltage
20
V
EAS
Single Pulse Avalanche Energy
7 6
mJ
IAR
Avalanche Current
-
A
EAR
Repetitive Avalanche Energy
-
mJ
dv/dt
Peak Diode Recovery dv/dt
5.5
V/ns
T J
Operating Junction
-55 to 150
TSTG
Storage Temperature Range
Pckg. Mounting Surface Temp.
300 (for 5 S)
Weight
0.42(typical)
g
PD - 93983
The leadless chip carrier (LCC) package represents the
logical next step in the continual evolution of surface
mount technology. Desinged to be a close replacement
for the TO-39 package, the LCC will give designers the
extra flexibility they need to increase circuit board den-
sity. International Rectifier has engineered the LCC pack-
age to meet the specific needs of the power market by
increasing the size of the bottom source pad, thereby
enhancing the thermal and electrical performance. The
lid of the package is grounded to the source to reduce
RF interference.
o
C
A
1/16/01
www.irf.com
1
LCC-18
Product Summary
Part Number B
VDSS
R
DS(on)
I
D
IRFE120 100V 0.30
4.5A
Features:
!
Surface Mount
!
Small Footprint
!
Alternative to TO-39 Package
!
Hermetically Sealed
!
Dynamic dv/dt Rating
!
Avalanche Energy Rating
!
Simple Drive Requirements
!
Light Weight
For footnotes refer to the last page
REPETITIVE AVALANCHE AND dv/dt RATED
IRFE120
HEXFET
TRANSISTORS JANTX2N6788U
SURFACE MOUNT (LCC-18) [REF:MIL-PRF-19500/555]
100V, N-CHANNEL
IRFE120
2
www.irf.com
Thermal Resistance
Parameter
Min Typ Max Units
Test Conditions
RthJC
Junction to Case
--
--
9.1
RthJ-PCB
Junction to PC Board
--
-- 26" " " Soldered to a copper clad PC board
C/W
Source-Drain Diode Ratings and Characteristics
Parameter
Min Typ Max Units
Test Conditions
IS
Continuous Source Current (Body Diode)
--
--
4.5
ISM
Pulse Source Current (Body Diode)
--
--
1 8
VSD
Diode Forward Voltage
--
--
1.8
V
T
j
= 25C, IS =4.5A, VGS = 0V
trr
Reverse Recovery Time
--
--
240
nS
Tj = 25C, IF = 4.5A, di/dt
100A/
s
QRR
Reverse Recovery Charge
--
--
2.0
c
VDD
50V
ton
Forward Turn-On Time
Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD.
A
For footnotes refer to the last page
Electrical Characteristics
@ Tj = 25C (Unless Otherwise Specified)
Parameter
Min
Typ Max Units
Test Conditions
BVDSS
Drain-to-Source Breakdown Voltage
100
--
--
V
VGS = 0V, ID = 1.0mA
BVDSS/
TJ Temperature Coefficient of Breakdown
--
0.10
--
V/C
Reference to 25C, ID = 1.0mA
Voltage
RDS(on)
Static Drain-to-Source On-State
--
--
0.30
VGS = 10V, ID =3.0A
Resistance
--
-- 0.345
VGS =10V, ID = 4.5A
VGS(th)
Gate Threshold Voltage
2.0
-- 4.0 V VDS = VGS, ID =250A
gfs
Forward Transconductance
1.5
--
--
S (
)
VDS > 15V, IDS =3.0A
IDSS
Zero Gate Voltage Drain Current
--
--
2 5
VDS=80V, VGS=0V
--
--
250
VDS =80V
VGS = 0V, TJ = 125C
IGSS
Gate-to-Source Leakage Forward
--
--
100
VGS = 20V
IGSS
Gate-to-Source Leakage Reverse
--
--
-100
VGS = -20V
Qg
Total Gate Charge
--
--
1 7
VGS =10V, ID= 4.5A
Qgs
Gate-to-Source Charge
--
--
4.0
nC
VDS =50V
Qgd
Gate-to-Drain (`Miller') Charge
--
--
7.7
td
(on)
Turn-On Delay Time
--
--
4 0
VDD =50V, ID =4.5A,
t r
Rise Time
--
--
7 0
RG =7.5
td
(off)
Turn-Off Delay Time
--
--
4 0
tf
Fall Time
--
--
7 0
LS + LD
Total Inductance
--
6.1
--
Ciss
Input Capacitance
--
350
VGS = 0V, VDS = 25V
Coss
Output Capacitance
--
150
--
pF
f = 1.0MHz
Crss
Reverse Transfer Capacitance
--
2 4
--
nA
nH
n s
A
Measured from the center of
drain pad to center of source
p a d
www.irf.com
3
IRFE120
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
IRFE120
4
www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
13 a& b
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5
IRFE120
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
V
DS
Pulse Width
1
s
Duty Factor
0.1 %
R
D
V
GS
R
G
D.U.T.
10V
+
-
V
DD
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature