IRFZ46S/L
HEXFET
Power MOSFET
PD - 9.922A
l
Advanced Process Technology
l
Surface Mount (IRFZ46S)
l
Low-profile through-hole (IRFZ46L)
l
175C Operating Temperature
l
Fast Switching
V
DSS
= 50V
R
DS(on)
= 0.024
I
D
= 72A
2
D P a k
T O - 2 6 2
S
D
G
8/25/97
Parameter
Typ.
Max.
Units
R
JC
Junction-to-Case
1.0
R
JA
Junction-to-Ambient ( PCB Mounted,steady-state)**
40
Thermal Resistance
C/W
Parameter
Max.
Units
I
D
@ T
C
= 25C
Continuous Drain Current, V
GS
@ 10V
50
I
D
@ T
C
= 100C
Continuous Drain Current, V
GS
@ 10V
38
A
I
DM
Pulsed Drain Current
220
P
D
@T
A
= 25C
Power Dissipation
3.7
W
P
D
@T
C
= 25C
Power Dissipation
150
W
Linear Derating Factor
1.0
W/C
V
GS
Gate-to-Source Voltage
20
V
E
AS
Single Pulse Avalanche Energy
100
mJ
dv/dt
Peak Diode Recovery dv/dt
4.5
V/ns
T
J
Operating Junction and
-55 to + 175
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
C
Absolute Maximum Ratings
Description
Third Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs
are well known for, provides the designer with an extremely
efficient and reliable device for use in a wide variety of
applications.
The D
2
Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D
2
Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRFZ46L) is available for low-
profile applications.
C
IRFZ46S/L
V
DD
= 25V
,
starting T
J
= 25C, L = 34H
R
G
= 25
, I
AS
= 54A. (See Figure 12)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Notes:
** When mounted on 1" square PCB (FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
I
SD
54A, di/dt
250A/s, V
DD
V
(BR)DSS
,
T
J
175C
Pulse width
300s; duty cycle
2%.
Uses IRFZ46 data and test conditions
Parameter
Min. Typ. Max. Units
Conditions
I
S
Continuous Source Current
MOSFET symbol
(Body Diode)
showing the
I
SM
Pulsed Source Current
integral reverse
(Body Diode)
p-n junction diode.
V
SD
Diode Forward Voltage
2.5
V
T
J
= 25C, I
S
= 54A, V
GS
= 0V
t
rr
Reverse Recovery Time
66
99
ns
T
J
= 25C, I
F
= 54A
Q
rr
Reverse Recovery Charge
170
310
nC
di/dt = 100A/s
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Source-Drain Ratings and Characteristics
A
Parameter
Min. Typ. Max. Units
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
50
V
V
GS
= 0V, I
D
= 250A
V
(BR)DSS
/
T
J
Breakdown Voltage Temp. Coefficient
0.057
V/C
Reference to 25C, I
D
=1mA
R
DS(on)
Static Drain-to-Source On-Resistance
0.024
V
GS
=10V, I
D
= 32A
V
GS(th)
Gate Threshold Voltage
2.0
4.0
V
V
DS
= V
GS
, I
D
= 250A
g
fs
Forward Transconductance
27
S
V
DS
= 25V, I
D
= 32A
25
A
V
DS
= 50V, V
GS
= 0V
250
V
DS
= 48V, V
GS
= 0V, T
J
= 150C
Gate-to-Source Forward Leakage
100
V
GS
= 20V
Gate-to-Source Reverse Leakage
-100
nA
V
GS
= -20V
Q
g
Total Gate Charge
66
I
D
= 54A
Q
gs
Gate-to-Source Charge
21
nC
V
DS
= 48V
Q
gd
Gate-to-Drain ("Miller") Charge
25
V
GS
= 10V, See Fig. 6 and 13
t
d(on)
Turn-On Delay Time
12
V
DD
= 28V
t
r
Rise Time
120
I
D
= 54A
t
d(off)
Turn-Off Delay Time
42
R
G
= 9.1
t
f
Fall Time
96
R
D
= 0.49
,
See Fig. 10
Between lead,
and center of die contact
C
iss
Input Capacitance
1800
V
GS
= 0V
C
oss
Output Capacitance
960
pF
V
DS
= 25V
C
rss
Reverse Transfer Capacitance
160
= 1.0MHz, See Fig. 5
Electrical Characteristics @ T
J
= 25C (unless otherwise specified)
I
GSS
ns
I
DSS
Drain-to-Source Leakage Current
nH
7.5
L
S
Internal Source Inductance
50
220
Calculated continuous current based on maximum allowable
junction temperature; for recommended current-handling of the
package refer to Design Tip # 93-4
S
D
G
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