IRU3007
1
Rev. 2.1
08/20/02
www.irf.com
TYPICAL APPLICATION
DESCRIPTION
The IRU3007 controller IC is specifically designed to meet
Intel specification for Pentium II
TM
microprocessor ap-
plications as well as the next generation of P6 family
processors. The IRU3007 provides a single chip control-
ler IC for the Vcore, LDO controller for GTL+ and an
internal 200mA regulator for clock supply which are re-
quired for the Pentium II applications. It also contains a
switching controller to convert 5V to 3.3V regulator for
on-board applications that uses either AT type power
supply or is desired not to rely on the ATX power supply's
3.3V output. These devices feature a patented topology
that in combination with a few external components, as
shown in the typical application circuit, will provide in
excess of 14A of output current for an on-board DC/DC
converter while automatically providing the right output
voltage via the 5-bit internal DAC. The IRU3007 also fea-
tures, loss-less current sensing for both switchers by
using the R
DS(on)
of the high-side power MOSFET as the
sensing resistor, internal current limiting for the clock
supply, a Power Good window comparator that switches
its open collector output low when any one of the out-
puts is outside of a pre-programmed window. Other fea-
tures of the device are: Under-Voltage Lockout for both
5V and 12V supplies, an external programmable soft-
start function, programming the oscillator frequency via
an external resistor, Over-Voltage Protection (OVP) cir-
cuitry for both switcher outputs and an internal thermal
shutdown.
Provides Single Chip Solution for Vcore, GTL+,
Clock Supply & 3.3V Switcher On-Board
Second switcher provides simple control for the
on-board 3.3V supply
200mA On-Board LDO Regulator
Designed to meet Intel VRM 8.2 and 8.3 specifica-
tion for Pentium II
TM
On-Board DAC programs the output voltage from
1.3V to 3.5V
Linear Regulator Controller On-Board for 1.5V
GTL+ supply
Loss-less Short Circuit Protection
Synchronous Operation allows maximum efficiency
Patented architecture allows fixed frequency
operation as well as 100% duty cycle during
dynamic load
Minimum Part Count
Soft-Start
High current totem pole drivers for directly driving
the external Power MOSFETs
Power Good function monitors all outputs
Over-Voltage Protection circuitry protects the
switcher outputs and generates a fault output
Thermal Shutdown
PACKAGE ORDER INFORMATION
FEATURES
5-BIT PROGRAMMABLE SYNCHRONOUS BUCK, NON-SYNCHRO-
NOUS, ADJUSTABLE LDO AND 200mA ON-BOARD LDO
APPLICATIONS
Total Power Solution for Pentium II processor
application
Note: Pentium II and Pentium Pro are trademarks of Intel Corp.
T
A
(C) DEVICE PACKAGE
0 To 70 IRU3007CW 28-pin Plastic SOIC WB (W)
Data Sheet No. PD94142
Figure 1 - Typical application of IRU3007.
LINEAR
CONTROL
SWITCHER2
CONTROL
LINEAR
REGULATOR
SWITCHER1
CONTROL
IRU3007
V
O U T
3
V
O U T
2
5V
V
O U T
1
V
O U T
4
2
Rev. 2.1
08/20/02
IRU3007
www.irf.com
ELECTRICAL SPECIFICATIONS
Supply UVLO Section
UVLO Threshold-12V
UVLO Hysteresis-12V
UVLO Threshold-5V
UVLO Hysteresis-5V
Supply Current
Operating Supply Current
VID Section (Vcore only)
DAC Output Voltage (Note 1)
DAC Output Line Regulation
DAC Output Temp Variation
VID Input LO
VID Input HI
VID Input Internal Pull-Up
Resistor to V5
V
FB
2 Voltage
Oscillator Section (Internal)
Osc Frequency
ABSOLUTE MAXIMUM RATINGS
V5 Supply Voltage .................................................... 7V
V12 Supply Voltage .................................................. 20V
Storage Temperature Range ...................................... -65C To 150C
Operating Junction Temperature Range ..................... 0C To 125C
PACKAGE INFORMATION
28-PIN WIDE BODY PLASTIC SOIC (W)
Unless otherwise specified, these specifications apply over V12=12V, V5=5V and T
A
=0 to 70C. Typical values refer
to T
A
=25C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
u
JA
=80
8
C/W
UGate2
Phase2
VID4
VID3
VID2
VID1
VID0
PGood
OCSet2
NC
Fb1
V
SEN
1
OCSet1
PGnd
LGate1
Phase1
UGate1
V12
4
3
2
1
25
26
27
28
7
6
5
22
23
24
TOP VIEW
9
20
8
21
Fb2
V5
SS
Fault / Rt
Fb4
V
SEN
2
V
OUT
4
Gnd
Gate3
Fb3
14
15
13
16
12
17
11
18
10
19
PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS
Switching Controllers; Vcore (V
OUT
1) and I/O (V
OUT
2)
Supply Ramping Up
Supply Ramping Up
V12
V5
Rt=Open
0.99Vs
2
27
10
0.4
4.3
0.3
6
30
Vs
0.1
0.5
2
200
1.01Vs
0.8
V
V
V
V
mA
V
%
%
V
V
K
V
V
KHz
IRU3007
3
Rev. 2.1
08/20/02
www.irf.com
Error Comparator Section
Input Bias Current
Input Offset Voltage
Delay to Output
Current Limit Section
CS Threshold Set Current
CS Comp Offset Voltage
Hiccup Duty Cycle
Output Drivers Section
Rise Time
Fall Time
Dead Band Time Between
High Side and Synch Drive
(Vcore Switcher Only)
2.5V Regulator (V
OUT
4)
Reference Voltage
Reference Voltage
Dropout Voltage
Load Regulation
Line Regulation
Input Bias Current
Output Current
Current Limit
Thermal Shutdown
1.5V Regulator (V
OUT
3)
Reference Voltage
Reference Voltage
Input Bias Current
Output Drive Current
Power Good Section
Core UV Lower Trip Point
Core UV Upper Trip Point
Core UV Hysteresis
Core OV Upper Trip Point
Core OV Lower Trip Point
Core OV Hysteresis
I/O UV lower trip point
I/O UV Upper Trip Point
Fb4 Lower Trip Point
Fb4 Upper Trip Point
Fb3 Lower Trip Point
Fb3 Upper Trip Point
Power Good Output LO
Power Good Output HI
Fault (Over-Voltage) Section
Core OV Upper Trip Point
Core OV Lower Trip Point
Soft-Start Section
Pull-Up Resistor to 5V
I/O OV Upper Trip Point
I/O OV Lower Trip Point
Fault Output HI
PARAMETER
SYM TEST CONDITION MIN TYP MAX UNITS
V
DIFF
=10mV
C
SS
=0.1
m
F
C
L
=3000pF
C
L
=3000pF
C
L
=3000pF
T
A
=25
8
C, V
OUT
4=Fb4
I
O
=200mA
1mA<I
O
<200mA
3.1V<V
I/O
<4V, V
O
=2.5V
T
A
=25
8
C, Gate3=Fb3
V
SEN
1 Ramping Down
V
SEN
1 Ramping Up
V
SEN
1 Ramping Up
V
SEN
1 Ramping Down
V
SEN
2 Ramping Down
V
SEN
2 Ramping Up
Fb4 Ramping Down
Fb4 Ramping Up
Fb3 Ramping Down
Fb3 Ramping Up
R
L
=3mA
R
L
=5K Pull Up to 5V
V
SEN
1 Ramping Up
V
SEN
1 Ramping Down
OCSet=0V, Phase=5V
V
SEN
2 Ramping Up
V
SEN
2 Ramping Down
I
O
=3mA
-2
-5
200
300
50
m
A
mV
ns
m
A
mV
%
ns
ns
ns
V
V
V
%
%
m
A
mA
mA
8
C
V
V
m
A
mA
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
K
V
V
V
V
2
+2
100
+5
2
2
200
10
70
70
200
1.260
1.260
0.6
0.5
0.2
145
1.260
1.260
0.90Vs
0.92Vs
0.02Vs
1.10Vs
1.08Vs
0.02Vs
2.4
2.6
0.95
1.05
0.95
1.05
0.4
4.8
1.17Vs
1.15Vs
23
4.3
4.2
10
V
O
4
V
O
3
4
Rev. 2.1
08/20/02
IRU3007
www.irf.com
PIN DESCRIPTIONS
Note 1: Vs refers to the set point voltage given in Table 1
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
D4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
Table 1 - Set point voltage vs. VID codes
Output driver for the high-side power MOSFET for the I/O supply.
This pin is connected to the Source of the power MOSFET for the I/O supply and it
provides the negative sensing for the internal current sensing circuitry.
This pin selects a range of output voltages for the DAC. When in the LO state the range
is 1.3V to 2.05V and when it switches to HI state the range is 2.0V to 3.5V. This pin is
TTL compatible that realizes a logic "1" as either HI or Open. When left open, this pin is
pulled up internally by a 27K
V
resistor to 5V supply.
MSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic "1" as either HI or Open. When left open, this pin is pulled up internally by
a 27K
V
resistor to 5V supply.
Input to the DAC that programs the output voltage. This pin is TTL compatible that real-
izes a logic "1" as either HI or Open. When left open, this pin is pulled up internally by a
27K
V
resistor to 5V supply.
Input to the DAC that programs the output voltage. This pin is TTL compatible that real-
izes a logic "1" as either HI or Open. When left open, this pin is pulled up internally by a
27K
V
resistor to 5V supply.
LSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic "1" as either HI or Open. When left open, this pin is pulled up internally by
a 27K
V
resistor to 5V supply.
This pin is an open collector output that switches LO when any of the outputs are outside
of the specified under voltage trip point. It also switches low when V
SEN
1 pin is more than
10% above the DAC voltage setting.
This pin is connected to the Drain of the power MOSFET of the I/O supply and it provides
the positive sensing for the internal current sensing circuitry. An external resistor pro-
grams the CS threshold depending on the R
DS
of the power MOSFET. An external ca-
pacitor is placed in parallel with the programming resistor to provide high frequency noise
filtering.
PIN# PIN SYMBOL PIN DESCRIPTION
1
2
3
4
5
6
7
8
9
UGate2
Phase2
VID4
VID3
VID2
VID1
VID0
PGood
OCSet2
IRU3007
5
Rev. 2.1
08/20/02
www.irf.com
This pin provides the feedback for the non-synchronous switching regulator. A resistor
divider is connected from this pin to V
OUT
2 and ground that sets the output voltage. The
value of the resistor connected from V
OUT
2 to Fb2 must be less than 100
V
.
5V supply voltage. A high frequency capacitor (0.1 to 1
m
F) must be placed close to this
pin and connected from this pin to the ground plane for noise free operation.
This pin provides the soft-start for the 2 switching regulators. An internal resistor charges
an external capacitor that is connected from 5V supply to this pin which ramps up the
outputs of the switching regulators, preventing the outputs from overshooting as well as
limiting the input current. The second function of the Soft-Start cap is to provide long off
time (HICCUP) for the synchronous MOSFET during current limiting.
This pin has dual function. It acts as an output of the OVP circuitry or it can be used to
program the frequency using an external resistor. When used as a fault detector, if any of
the switcher outputs exceed the OVP trip point, the Fault pin switches to 12V and the
soft-start cap is discharged. If the Fault pin is to be connected to any external circuitry,
it needs to be buffered as shown in the application circuit.
This pin provides the feedback for the internal LDO regulator that its output is V
OUT
4.
This pin is connected to the output of the I/O switching regulator. It is an input that
provides sensing for the Under/Over-voltage circuitry for the I/O supply as well as the
power for the internal LDO regulator.
This pin is the output of the internal LDO regulator.
This pin serves as the ground pin and must be connected directly to the ground plane.
This pin controls the gate of an external transistor for the 1.5V GTL+ linear regulator.
This pin provides the feedback for the linear regulator that its output drive is Gate3.
No connection.
This pin provides the feedback for the synchronous switching regulator. Typically this pin
can be connected directly to the output of the switching regulator. However, a resistor
divider is recommended to be connected from this pin to V
OUT
1 and ground to adjust the
output voltage for any drop in the output voltage that is caused by the trace resistance.
The value of the resistor connected from V
OUT
1 to Fb1 must be less than 100
V
.
This pin is internally connected to the undervoltage and overvoltage comparators sensing
the Vcore status. It must be connected directly to the Vcore supply.
This pin is connected to the Drain of the power MOSFET of the Core supply and it
provides the positive sensing for the internal current sensing circuitry. An external resis-
tor programs the CS threshold depending on the R
DS
of the power MOSFET. An external
capacitor is placed in parallel with the programming resistor to provide high frequency
noise filtering.
This pin serves as the Power ground pin and must be connected directly to the ground
plane close to the source of the synchronous MOSFET. A high frequency capacitor
(typically 1
m
F) must be connected from V12 pin to this pin for noise free operation.
Output driver for the synchronous power MOSFET for the Core supply.
This pin is connected to the Source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
Output driver for the high-side power MOSFET for the Core supply.
This pin is connected to the 12V supply and serves as the power Vcc pin for the output
drivers. A high frequency capacitor (typically 1
m
F) must be placed close to this pin and
PGnd pin and be connected directly from this pin to the ground plane for noise free
operation.
PIN# PIN SYMBOL PIN DESCRIPTION
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Fb2
V5
SS
Fault / Rt
Fb4
V
SEN
2
V
OUT
4
Gnd
Gate3
Fb3
NC
Fb1
V
SEN
1
OCSet1
PGnd
LGate1
Phase1
UGate1
V12
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