IRS2101(S)PbF
Data Sheet No. PD60250
Typical Connection
Features
Floating channel designed for bootstrap operation
Fully operational to +600 V
Tolerant to negative transient voltage
,
dV/dt immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout
3.3 V, 5 V, and 15 V logic input compatible
Matched propagation delay for both channels
Outputs in phase with inputs
HIGH AND LOW SIDE DRIVER
Product Summary
V
OFFSET
600 V max.
I
O
+/-
130 mA/270 mA
V
OUT
10 V - 20 V
t
on/off
(typ.)
160 ns/150 ns
Delay Matching
50 ns
IRS2101(S)PbF
Description
The IRS2101 is a high voltage, high speed power
MOSFET and IGBT driver with independent high and
low side referenced output channels. Proprietary
HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. The logic input
is compatible with standard CMOS or LSTTL output,
down to 3.3 V logic. The output drivers feature a high
pulse current buffer stage designed for minimum driver
cross-conduction. The floating channel can be used to
drive an N-channel power MOSFET or IGBT in the high
side configuration which operates up to 600 V.
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(Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only.
Please refer to our Application Notes and DesignTips for proper circuit board layout.
IRS2101
V
CC
V
B
V
S
HO
LO
COM
HIN
LIN
LIN
HIN
up to 600 V
TO
LOAD
V
CC
Packages
8-Lead PDIP
IRS2101
8-Lead SOIC
IRS2101S
IRS2101(S)PbF
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Symbol
Definition
Min.
Max.
Units
V
B
High side floating supply voltage -0.3
625
V
S
High side floating supply offset voltage
V
B
- 25
V
B
+ 0.3
V
HO
High side floating output voltage
V
S
- 0.3
V
B
+ 0.3
V
CC
Low side and logic fixed supply voltage -0.3
25
V
LO
Low side output voltage
-0.3
V
CC
+ 0.3
V
IN
Logic input voltage (HIN & LIN)
-0.3
V
CC
+ 0.3
dV
S
/dt
Allowable offset supply voltage transient
--
50
V/ns
P
D
Package power dissipation @ T
A
+25
C
(8 lead PDIP)
--
1.0
(8 lead SOIC)
--
0.625
Rth
JA
Thermal resistance, junction to ambient
(8 lead PDIP)
--
125
(8 lead SOIC)
--
200
T
J
Junction temperature
--
150
T
S
Storage temperature
-55
150
T
L
Lead temperature (soldering, 10 seconds)
--
300
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
W
C/W
V
C
Symbol
Definition
Min.
Max.
Units
V
B
High side floating supply absolute voltage
V
S
+ 10
V
S
+ 20
V
S
High side floating supply offset voltage
Note
1 600
V
HO
High side floating output voltage
V
S
V
B
V
CC
Low side and logic fixed supply voltage
10
20
V
LO
Low side output voltage
0
V
CC
V
IN
Logic input voltage (HIN & LIN)
0
V
CC
T
A
Ambient temperature
-40
125
Note
1: Logic operational for V
S
of -5 V to +600 V. Logic state held for V
S
of -5 V to -V
BS
. (Please refer to the Design
Tip DT97-3 for more details).
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The V
S
offset rating is tested with all supplies biased at a 15 V differential.
C
V
IRS2101(S)PbF
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Symbol
Definition
Min. Typ. Max. Units Test Conditions
V
IH
Logic "1" input voltage
2.5 -- --
V
IL
Logic "0" input voltage
--
--
0.8
V
OH
High level output voltage, V
BIAS
- V
O
--
0.05
0.2
V
OL
Low level output voltage, V
O
--
0.02
0.1
I
LK
Offset supply leakage current
--
--
50
V
B
= V
S
= 600 V
I
QBS
Quiescent V
BS
supply current
--
30
55
I
QCC
Quiescent V
CC
supply current
--
150
270
I
IN+
Logic "1" input bias current
--
3
10
V
IN
= 5 V
I
IN-
Logic "0" input bias current
--
--
1
V
IN
= 0 V
V
CCUV+
V
CC
supply undervoltage positive going threshold
8
8.9
9.8
V
CCUV-
V
CC
supply undervoltage negative going threshold
7.4
8.2
9
V
O
= 0 V
I
O+
Output high short circuit pulsed current
130
290
--
V
IN
= Logic "1"
PW
10
s
V
O
= 15 V
I
O-
Output low short circuit pulsed current
270
600
--
V
IN
= Logic "0"
PW
10
s
Symbol
Definition
Min. Typ. Max. Units Test Conditions
ton
Turn-on propagation delay
--
160
220
V
S
= 0 V
toff
Turn-off propagation delay
--
150
220
V
S
= 600 V
tr
Turn-on rise time
--
70
170
tf
Turn-off fall time
--
35
90
MT
Delay matching, HS & LS turn-on/off
--
--
50
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15 V, C
L
= 1000 pF and T
A
= 25
C unless otherwise specified.
V
mA
V
A
ns
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15 V and T
A
= 25
C unless otherwise specified. The V
IN
, V
TH,
and I
IN
parameters are referenced to
COM. The V
O
and I
O
parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
V
CC
= 10 V to 20 V
I
O
= 2 mA
V
IN
= 0 V or 5 V
IRS2101(S)PbF
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Functional Block Diagram
PULSE
GEN
HIN
UV
DETECT
LIN
COM
HO
V
S
V
CC
LO
V
B
R
Q
S
PULSE
FILTER
HV
LEVEL
SHIFT
IRS2101
IRS2101(S)PbF
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Lead Definitions
Symbol
Description
HIN
Logic input for high side gate driver output (HO), in phase
LIN
Logic input for low side gate driver output (LO), in phase
V
B
High side floating supply
HO
High side gate drive output
V
S
High side floating supply return
V
CC
Low side and logic fixed supply
LO
Low side gate drive output
COM
Low side return
Lead Assignments
8 Lead PDIP
8 Lead SOIC
IRS2101PbF
IRS2101SPbF
Part Number
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