IRU1050
1
Rev. 1.8
08/20/02
www.irf.com
TYPICAL APPLICATION
DESCRIPTION
The IRU1050 is a low dropout three-terminal adjustable
regulator with minimum of 5A output current capability.
This product is specifically designed to provide well regu-
lated supply for low voltage IC applications such as
Pentium
TM
P54C
TM
,P55C
TM
as well as GTL+ termination
for Pentium Pro
TM
and Klamath
TM
processor applications.
The IRU1050 is also well suited for other processors
such as Cyrix
TM
, AMD and Power PC
TM
applications.
The IRU1050 is guaranteed to have <1.3V dropout at full
load current making it ideal to provide well regulated
outputs of 2.5V to 3.3V with 4.75V to 7V input supply.
5A LOW DROPOUT POSITIVE
ADJUSTABLE REGULATOR
Notes: Pentium P54C, P55C, Klamath, Pentium Pro,VRE are trademarks of Intel Corp. Cyrix M2 is trademark of Cyrix Corp.
Power PC is trademark of IBM Corp.
PACKAGE ORDER INFORMATION
T
J
(C) 2-PIN PLASTIC 3-PIN PLASTIC 2-PIN PLASTIC 3-PIN PLASTIC
TO-252 (D-Pak) TO-263 (M) Ultra Thin-Pak
TM
(P) TO-220 (T)
0 To 150 IRU1050CD IRU1050CM IRU1050CP IRU1050CT
Data Sheet No. PD94126
Figure 1 - Typical Application of IRU1050 in a 5V to 3.38V regulator designed
to meet the Intel P54C
TM
processors.
Low Voltage Processor Applications such as:
P54C
TM
, P55C
TM
, Cyrix M2
TM
,
POWER PC
TM
, AMD
GTL+ Termination
PENTIUM PRO
TM
, KLAMATH
TM
Low Voltage Memory Termination Applications
Standard 3.3V Chip Set and Logic Applications
FEATURES
APPLICATIONS
Guaranteed < 1.3V Dropout at Full Load Current
Fast Transient Response
1% Voltage Reference Initial Accuracy
Output Current Limiting
Built-In Thermal Shutdown
5V
3.38V / 5A
R1
121
R2
205
C1
1500uF
C2
2x 1500uF
IRU1050
1
2
3
Adj
V
IN
V
OUT
2
Rev. 1.8
08/20/02
IRU1050
www.irf.com
ABSOLUTE MAXIMUM RATINGS
Input Voltage (V
IN
) .................................................... 7V
Power Dissipation ..................................................... Internally Limited
Storage Temperature Range ...................................... -65C To 150C
Operating Junction Temperature Range ..................... 0C To 150C
PACKAGE INFORMATION
2-Pin Plastic TO-252 (D-Pak) 3-Pin Plastic TO-263 (M) 2-Pin Plastic ULTRA THIN-PAK
TM
(P) 3-Pin Plastic TO-220 (T)
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over C
IN
=1
m
F, C
OUT
=10
m
F, and T
J
=0 to 150
8
C.
Typical values refer to T
J
=25
8
C.
Note 1: Low duty cycle pulse testing with Kelvin con-
nections is required in order to maintain accurate data.
Note 2: Dropout voltage is defined as the minimum dif-
ferential voltage between V
IN
and V
OUT
required to main-
tain regulation at V
OUT
. It is measured when the output
voltage drops 1% below its nominal value.
Note 3: Minimum load current is defined as the mini-
mum current required at the output in order for the out-
put voltage to maintain regulation. Typically the resistor
dividers are selected such that it automatically main-
tains this current.
Adj
Tab is
VOUT
VIN
VOUT
1
2
3
FRONT VIEW
Adj
V
OUT
V
IN
1
2
3
FRONT VIEW
Tab is
V
OUT
Adj
V
IN
FRONT VIEW
1
3
Tab is
V
OUT
Adj
V
IN
1
3
FRONT VIEW
Tab is
V
OUT
JA
=70
C/W for 0.5" Sq pad
JA
=35
C/W for 1" Square pad
JA
=70
C/W for 1" Square pad
JT
=2.7
C/W
JA
=60
C/W
PARAMETER
SYM TEST CONDITION
MIN TYP MAX UNITS
V
REF
D
Vo
I
ADJ
Reference Voltage
Line Regulation
Load Regulation (Note 1)
Dropout Voltage (Note 2)
Current Limit
Minimum Load Current (Note 3)
Thermal Regulation
Ripple Rejection
Adjust Pin Current
Adjust Pin Current Change
Temperature Stability
Long Term Stability
RMS Output Noise
Io=10mA, T
J
=25
8
C, V
IN
-Vo=1.5V
Io=10mA, V
IN
-Vo=1.5
Io=10mA, 1.3V<(V
IN
-Vo)<7V
V
IN
=3.3V, V
ADJ
=0V, 10mA<Io<5A
Note 2, Io=4A
Io=5A
V
IN
=3.3V,
D
Vo=100mV
V
IN
=3.3V, V
ADJ
=0V
30ms Pulse, V
IN
-Vo=3V, Io=5A
f=120Hz, Co=25
m
F Tantalum,
Io=2.5A, V
IN
-Vo=3V
Io=10mA, V
IN
-Vo=1.5V, T
J
=25
8
C,
Io=10mA, V
IN
-Vo=1.5V
Io=10mA, V
IN
-Vo=1.5V, T
J
=25
8
C
V
IN
=3.3V, V
ADJ
=0V, Io=10mA
T
J
=125
8
C, 1000Hrs
T
J
=25
8
C, 10Hz<f<10KHz
1.238
1.225
5.1
60
1.25
1.25
1.1
5
0.01
70
55
0.2
0.5
0.3
0.003
1.262
1.275
0.2
0.4
1.2
1.3
10
0.02
120
5
1
V
%
%
V
A
mA
%/W
dB
m
A
m
A
%
%
%Vo
IRU1050
3
Rev. 1.8
08/20/02
www.irf.com
Introduction
The IRU1050 adjustable Low Dropout (LDO) regulator is
a three-terminal device which can easily be programmed
with the addition of two external resistors to any volt-
ages within the range of 1.25 to 5.5 V. This regulator
unlike the first generation of the three-terminal regula-
tors such as LM117 that required 3V differential between
the input and the regulated output, only needs 1.3V dif-
ferential to maintain output regulation. This is a key re-
quirement for today's microprocessors that need typi-
cally 3.3V supply and are often generated from the 5V
supply. Another major requirement of these micropro-
cessors such as the Intel P54C
TM
is the need to switch
the load current from zero to several amps in tens of
nanoseconds at the processor pins, which translates to
an approximately 300 to 500ns current step at the regu-
lator. In addition, the output voltage tolerances are also
extremely tight and they include the transient response
as part of the specification.For example Intel VRE
TM
specification calls for a total of
100mV including initial
tolerance, load regulation and 0 to 4.6A load step.
The IRU1050 is specifically designed to meet the fast
current transient needs as well as providing an accurate
initial voltage, reducing the overall system cost with the
need for fewer output capacitors.
PIN DESCRIPTIONS
PIN # PIN SYMBOL
PIN DESCRIPTION
Figure 2 - Simplified block diagram of the IRU1050.
A resistor divider from this pin to the V
OUT
pin and ground sets the output voltage.
The output of the regulator. A minimum of 10
m
F capacitor must be connected from this pin
to ground to insure stability.
The input pin of the regulator. Typically a large storage capacitor is connected from this
pin to ground to insure that the input voltage does not sag below the minimum drop out
voltage during the load transient response. This pin must always be 1.3V higher than V
OUT
in order for the device to regulate properly.
BLOCK DIAGRAM
1
2
3
Adj
V
OUT
V
IN
V
IN
3
1 Adj
2 V
OUT
THERMAL
SHUTDOWN
CURRENT
LIMIT
1.25V
+
+
APPLICATION INFORMATION
4
Rev. 1.8
08/20/02
IRU1050
www.irf.com
Output Voltage Setting
The IRU1050 can be programmed to any voltages in the
range of 1.25V to 5.5V with the addition of R1 and R2
external resistors according to the following formula:
Where:
V
REF
= 1.25V Typically
I
ADJ
= 50
m
A Typically
R1 and R2 as shown in Figure 3:
Figure 3 - Typical application of the IRU1050
for programming the output voltage.
The IRU1050 keeps a constant 1.25V between the out-
put pin and the adjust pin. By placing a resistor R1 across
these two pins a constant current flows through R1, add-
ing to the I
ADJ
current and into the R2 resistor producing
a voltage equal to the (1.25/R1)
3
R2 + I
ADJ
3
R2 which
will be added to the 1.25V to set the output voltage.
This is summarized in the above equation. Since the
minimum load current requirement of the IRU1050 is
10mA, R1 is typically selected to be 121
V
resistor so
that it automatically satisfies the minimum current re-
quirement. Notice that since I
ADJ
is typically in the range
of 50
m
A it only adds a small error to the output voltage
and should only be considered when a very precise out-
put voltage setting is required. For example, in a typical
3.3V application where R1=121
V
and R2=200
V
the er-
ror due to I
ADJ
is only 0.3% of the nominal set point.
Load Regulation
Since the IRU1050 is only a three-terminal device, it is
not possible to provide true remote sensing of the output
voltage at the load. Figure 4 shows that the best load
regulation is achieved when the bottom side of R2 is
connected to the load and the top side of R1 resistor is
connected directly to the case or the V
OUT
pin of the
regulator and not to the load. In fact, if R1 is connected
to the load side, the effective resistance between the
regulator and the load is gained up by the factor of (1+R2/
R1), or the effective resistance will be R
P(eff)
=R
P
3
(1+R2/
R1). It is important to note that for high current applica-
tions, this can represent a significant percentage of the
overall load regulation and one must keep the path from
the regulator to the load as short as possible to mini-
mize this effect.
Figure 4 - Schematic showing connection
for best load regulation.
Stability
The IRU1050 requires the use of an output capacitor as
part of the frequency compensation in order to make the
regulator stable. Typical designs for microprocessor ap-
plications use standard electrolytic capacitors with a
typical ESR in the range of 50 to 100m
V
and an output
capacitance of 500 to 1000
m
F. Fortunately as the ca-
pacitance increases, the ESR decreases resulting in a
fixed RC time constant. The IRU1050 takes advantage
of this phenomena in making the overall regulator loop
stable. For most applications a minimum of 100
m
F alu-
minum electrolytic capacitor such as Sanyo MVGX se-
ries, Panasonic FA series as well as the Nichicon PL
series insures both stability and good transient response.
Thermal Design
The IRU1050 incorporates an internal thermal shutdown
that protects the device when the junction temperature
exceeds the maximum allowable junction temperature.
Although this device can operate with junction tempera-
tures in the range of 150
8
C, it is recommended that the
selected heat sink be chosen such that during maxi-
mum continuous load operation the junction tempera-
ture is kept below this number. The example below shows
the steps in selecting the proper regulator heat sink for
the worst case current consumption using Intel 200MHz
microprocessor as the load.
V
O U T
R 1
R 2
V
I N
V
REF
I
ADJ
= 50uA
Adj
V
OUT
V
IN
IRU1050
R1
R2
V
IN
R
L
R
P
PARASITIC LINE
RESISTANCE
IRU1050
Adj
V
OUT
Vin
V
OUT
= V
REF
3
1+
+I
ADJ
3
R2
R2
R1
(
)
IRU1050
5
Rev. 1.8
08/20/02
www.irf.com
Assuming the following specifications:
The steps for selecting a proper heat sink to keep the
junction temperature below 135
8
C is given as:
1) Calculate the maximum power dissipation using:
2) Select a package from the regulator data sheet and
record its junction to case (or tab) thermal resistance.
Selecting TO-220 package gives us:
3) Assuming that the heat sink is black anodized, cal-
culate the maximum heat sink temperature allowed:
Assume,
u
cs=0.05
C/W (heat-sink-to-case thermal
resistance for black anodized)
4) With the maximum heat sink temperature calculated
in the previous step, the heat-sink-to-air thermal re-
sistance (
u
SA
) is calculated by first calculating the
temperature rise above the ambient as follows:
5) Next, a heat sink with lower
u
SA
than the one calcu-
lated in Step 4 must be selected. One way to do this
is to simply look at the graphs of the "Heat Sink Temp
Rise Above the Ambient" vs. the "Power Dissipation"
and select a heat sink that results in lower tempera-
ture rise than the one calculated in previous step.
The following heat sinks from AAVID and Thermalloy
meet this criteria.
P
D
= I
OUT
3
(V
IN
- V
OUT
)
P
D
= 4.6
3
(5 - 3.5) = 6.9W
V
IN
= 5V
V
OUT
= 3.5V
I
OUT(MAX)
= 4.6A
T
A
= 35
8
C
u
JC
= 2.7
8
C/W
T
S
= T
J
- P
D
3
(
u
JC
+
u
CS
)
T
S
= 135 - 6.9
3
(27 + 0.05) = 116
8
C
u
SA
= = = 11.7
8
C/W
D
T
P
D
81
6.9
D
T = T
S
- T
A
= 116 - 35 = 81
8
C
T = Temperature Rise Above Ambient
Note: For further information regarding the above com-
panies and their latest product offerings and application
support contact your local representative or the num-
bers listed below:
AAVID.................PH# (603) 528 3400
Thermalloy...........PH# (214) 243-4321
Designing for Microprocessor Applications
As it was mentioned before, the IRU1050 is designed
specifically to provide power for the new generation of
the low voltage processors requiring voltages in the range
of 2.5V to 3.6V generated by stepping down the 5V sup-
ply. These processors demand a fast regulator that sup-
ports their large load current changes. The worst case
current step seen by the regulator is anywhere in the
range of 1 to 7A with the slew rate of 300 to 500ns which
could happen when the processor transitions from "Stop
Clock" mode to the "Full Active" mode. The load current
step at the processor is actually much faster, in the or-
der of 15 to 20ns, however, the decoupling capacitors
placed in the cavity of the processor socket handle this
transition until the regulator responds to the load current
levels. Because of this requirement the selection of high
frequency low ESR and low ESL output capacitor is
imperative in the design of these regulator circuits.
Figure 5 shows the effects of a fast transient on the
output voltage of the regulator. As shown in this figure,
the ESR of the output capacitor produces an instanta-
neous drop equal to the (
D
V
ESR
=ESR
3D
I) and the ESL
effect will be equal to the rate of change of the output
current times the inductance of the capacitor. (
D
V
ESL
=L
3D
I/
D
t). The output capacitance effect is a droop in
the output voltage proportional to the time it takes for
the regulator to respond to the change in the current,
(
D
Vc=
D
t
3D
I/C) where
D
t is the response time of the
regulator.
Air Flow (LFM)
0 100 200 300 400
Thermalloy 6021PB 6021PB 6073PB 6109PB 7141D
AAVID 534202B 534202B 507302 575002 576802B
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