IRU3011
1
Rev. 1.6
08/20/02
www.irf.com
TYPICAL APPLICATION
DESCRIPTION
The IRU3011 controller IC is specifically designed to meet
Intel specification for latest Pentium III
TM
microproces-
sor applications as well as the next generation P6 fam-
ily processors. These products feature a patented topol-
ogy that in combination with a few external components
as shown in the typical application circuit,will provide in
excess of 20A of output current for an on-board DC/DC
converter while automatically providing the right output
voltage via the 5-bit internal DAC. These devices also
features, loss less current sensing by using the R
DS(ON)
of the high side Power MOSFET as the sensing resis-
tor, a Power Good window comparator that switches its
open collector output low when the output is outside of a
10% window and an Over-Voltage Protection output.
Other features of the device are: Under-voltage lockout
for both 5V and 12V supplies, an external programmable
soft-start function as well as programming the oscillator
frequency by using an external capacitor.
Dual Layout compatible with HIP6004A
Designed to meet Intel specification of VRM8.4 for
Pentium III
TM
On-Board DAC programs the output voltage from
1.3V to 3.5V. The IRU3011 remains on for VID code
of (11111).
Loss-less Short Circuit Protection
Synchronous operation allows maximum efficiency
Patented architecture allows fixed frequency
operation as well as 100% duty cycle during
dynamic load
Over-Voltage Protection Output
Soft-Start
High current totem pole driver for direct driving of the
external power MOSFET
Power Good Function
PACKAGE ORDER INFORMATION
FEATURES
5-BIT PROGRAMMABLE SYNCHRONOUS BUCK
CONTROLLER IC
APPLICATIONS
Pentium III & Pentium II
TM
processor DC to DC
converter application
Low Cost Pentium with AGP
Note: Pentium II and Pentium III are trade marks of Intel Corp.
T
A
(
8
C)
DEVICE PACKAGE VID VOLTAGE RANGE
0 To 70 IRU3011CW 20-Pin Plastic SOIC WB (W) 1.3V to 3.5V
Data Sheet No. PD94143
Figure 1 - Typical application of the IRU3011.
V
OUT
(1.3V - 3.5V)
5V
12V
VID0
Power Good
Q2
VID1
VID2
VID3
VID4
L1
C5
R1
C3
C6
Q1
R2
R3
C8
R4
C10
C14
C1
C7
C2
R6
C12
R8
C13
C11
R7
R9
R5
C9
D1
C4
L2
HDrv
LDrv
NC/Gnd
SS
CS+
Gnd
NC/Sen
D3
D2
D4
D1
D0
IRU3011
V
FB
V5/Comp
CS-
V12
NC/
Boot
OVP
PGd
Ct/Rt
OVP
2
Rev. 1.6
08/20/02
IRU3011
www.irf.com
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over V12=12V, V5=5V and T
A
=0 to 70C. Typical values refer
to T
A
=25C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
ABSOLUTE MAXIMUM RATINGS
V5 Supply Voltage .................................................... 7V
V12 Supply Voltage .................................................. 20V
Storage Temperature Range ...................................... -65C To 150C
Operating Junction Temperature Range ...................... 0C To 125C
PACKAGE INFORMATION
20-PIN WIDE BODY PLASTIC SOIC (W)
VID Section
DAC Output Voltage (Note 1)
DAC Output Line Regulation
DAC Output Temp Variation
VID Input LO
VID Input HI
VID Input Internal Pull-Up
Resistor to V5
Power Good Section
Under-Voltage lower trip point
Under-Voltage upper trip point
UV Hysterises
Over-Voltage upper trip point
Over-Voltage lower trip point
OV Hysteresis
Power Good Output LO
Power Good Output HI
Soft-Start Section
Soft-Start Current
u
JA
=85
8
C/W
Ct
OVP
V12
LDrv
Gnd
NC
HDrv
CS-
PGd
NC
NC
CS+
SS
D0
D1
D2
D3
D4
V5
V
FB
4
3
2
1
7
6
5
18
19
20
TOP VIEW
11
13
12
14
10
15
9
16
8
17
PARAMETER
SYM TEST CONDITION MIN TYP MAX UNITS
V
OUT
Ramping Down
V
OUT
Ramping Up
V
OUT
Ramping Up
V
OUT
Ramping Down
R
L
=3mA
R
L
=5K Pull-Up to 5V
CS+=0V, CS-=5V
0.99Vs
2
0.89Vs
0.015Vs
1.09Vs
0.015Vs
4.8
Vs
27
0.90Vs
0.92Vs
0.02Vs
1.10Vs
1.08Vs
0.02Vs
10
1.01Vs
0.1
0.5
0.4
0.91Vs
0.025Vs
1.11Vs
0.025Vs
0.4
V
%
%
V
V
K
V
V
V
V
V
V
V
V
V
m
A
IRU3011
3
Rev. 1.6
08/20/02
www.irf.com
UVLO Section
UVLO Threshold-12V
UVLO Hysteresis-12V
UVLO Threshold-5V
UVLO Hysteresis-5V
Error Comparator Section
Input Bias Current
Input Offset Voltage
Delay to Output
Current Limit Section
CS Threshold Set Current
CS Comp Offset Voltage
Hiccup Duty Cycle
Supply Current
Operating Supply Current
Output Drivers Section
Rise Time
Fall Time
Dead Band Time
Oscillator Section
Osc Frequency
Osc Valley
Osc Peak
Over-Voltage Section
OVP Drive Current
PARAMETER
SYM TEST CONDITION MIN TYP MAX UNITS
Table 1 - Set point voltage vs. VID codes.
Note 1: Vs refers to the set point voltage given in Table 1.
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
D4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
Supply Ramping Up
Supply Ramping Up
V
DIFF
=10mV
Css=0.1
m
F
C
L
=3000pF:
V5
V12
C
L
=3000pF
C
L
=3000pF
C
L
=3000pF
Ct=150pF
9.2
0.3
4.1
0.2
-2
160
-5
100
190
10
0.4
4.3
0.3
200
20
14
70
70
200
220
V5
10.8
0.5
4.5
0.4
2
+2
100
240
+5
2
100
130
300
250
0.2
V
V
V
V
m
A
mV
ns
m
A
mV
%
mA
ns
ns
ns
KHz
V
V
mA
4
Rev. 1.6
08/20/02
IRU3011
www.irf.com
PIN DESCRIPTIONS
No connection.
This pin is connected to the Drain of the power MOSFET of the Core supply and it
provides the positive sensing for the internal current sensing circuitry. An external resis-
tor programs the CS threshold depending on the R
DS
of the power MOSFET. An external
capacitor is placed in parallel with the programming resistor to provide high frequency
noise filtering.
This pin provides the soft-start for the switching regulator. An internal current source
charges an external capacitor that is connected from this pin to the ground which ramps
up the outputs of the switching regulator, preventing the outputs from overshooting as
well as limiting the input current. The second function of the Soft-Start cap is to provide
long off time for the synchronous MOSFET or the Catch diode (HICCUP) during current
limiting.
LSB input to the DAC that programs the output voltage. This pin can be pulled up exter-
nally by a 10K resistor to either 3.3V or 5V supply.
Input to the DAC that programs the output voltage. This pin can be pulled-up externally
by a 10K
V
resistor to either 3.3V or 5V supply.
Input to the DAC that programs the output voltage. This pin can be pulled-up externally
by a 10K resistor to either 3.3V or 5V supply.
MSB input to the DAC that programs the output voltage. This pin can be pulled-up exter-
nally by a 10K resistor to either 3.3V or 5V supply.
This pin selects a range of output voltages for the DAC.
5V supply voltage.
This pin is connected directly to the output of the Core supply to provide feedback to the
Error comparator.
No connection.
This pin is an open collector output that switches LO when the output of the converter is
not within
10% (typ) of the nominal output voltage. When PGd pin switches LO the
saturation voltage is less than 0.4V at 3mA.
This pin is connected to the Source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
Output driver for the high side power MOSFET.
No connection.
This pin serves as the ground pin and must be connected directly to the ground plane. A
high frequency capacitor (0.1 to 1
m
F) must be connected from V5 and V12 pins to this
pin for noise free operation.
Output driver for the synchronous power MOSFET.
This pin is connected to the 12 V supply and serves as the power Vcc pin for the output
drivers. A high frequency capacitor (0.1 to 1
m
F) must be connected directly from this pin
to ground pin in order to supply the peak current to the power MOSFET during the
transitions.
Over-voltage comparator output.
This pin programs the oscillator frequency in the range of 50KHz to 500KHz with an
external capacitor connected from this pin to the ground.
PIN# PIN SYMBOL PIN DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC
CS+
SS
D0
D1
D2
D3
D4
V5
V
FB
NC
PGd
CS-
HDrv
NC
Gnd
LDrv
V12
OVP
Ct
IRU3011
5
Rev. 1.6
08/20/02
www.irf.com
BLOCK DIAGRAM
Figure 2 - Simplified block diagram of the IRU3011.
PWM
Control
V12
V12
Osc
Slope
Comp
+
5Bit
DAC,
Ctrl
Logic
Enable
Soft
Start &
Fault
Logic
200uA
0.9Vset
1.1Vset
Vset
Enable
UVLO
Vset
Enable
D4
V5
V12
SS
PGd
CS-
Ct
CS+
LDrv
HDrv
V
FB
D3
D2
D1
D0
Over
Current
Enable
Gnd
1.18Vset
OVP
18
9
4
5
6
7
8
19
16
10
14
17
13
2
20
3
12
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