IRU3018
1
Rev. 1.5
07/24/01
TYPICAL APPLICATION
DESCRIPTION
The IRU3018 controller IC is specifically designed to meet
Intel specification for Pentium II
microprocessor appli-
cations as well as the next generation of P6 family pro-
cessors. The IRU3018 provides a single chip controller
IC for the Vcore, LDO controller for GTL+ and an internal
200mA regulator for clock supply which are required for
the Pentium II applications. These devices feature a pat-
ented topology that in combination with a few external
components as shown in the typical application circuit,
will provide in excess of 18A of output current for an on-
board DC-DC converter while automatically providing the
right output voltage via the 5-bit internal DAC. The
IRU3018 also features loss-less current sensing for both
switchers by using the R
DS(on)
of the high-side power
MOSFET as the sensing resistor, internal current limit-
ing for the clock supply, and a Power Good window com-
parator that switches its open collector output low when
any one of the outputs is outside of a pre-programmed
window. Other features of the device are: Under-voltage
lockout for both 5V and 12V supplies, an external pro-
grammable soft-start function, programming the oscilla-
tor frequency via an external resistor, Over-Voltage Pro-
tection (OVP) circuitry for both switcher outputs and an
internal thermal shutdown.
Provides single chip solution for Vcore, GTL+ & clock
supply
200mA On-Board LDO Regulator
Designed to meet the latest Intel specification for
Pentium II
On-Board DAC programs the output voltage from
1.3V to 3.5V
Linear regulator controller on board for 1.5V GTL+
supply
Loss-less Short Circuit Protection with HICCUP
Synchronous operation allows maximum efficiency
patented architecture allows fixed frequency opera-
tion as well as 100% duty cycle during dynamic
load
Soft-Start
High current totem pole driver for direct driving of the
external power MOSFET
Power Good Function monitors all outputs
Over-Voltage Protection circuitry protects the
switcher output and generates a fault signal
Thermal Shutdown
Logic Level Enable Input
PACKAGE ORDER INFORMATION
FEATURES
5-BIT PROGRAMMABLE SYNCHRONOUS BUCK PLUS
LDO CONTROLLER AND 200mA LDO ON-BOARD
APPLICATIONS
Total Power Solution for Pentium II processor
application
Note: Pentium II is trademark of Intel Corp
T
A
(!C) DEVICE PACKAGE
0 To 70 IRU3018CW 24-pin Plastic SOIC WB
Data Sheet No. PD94144
3018app3-1.1
LINEAR
CONTROL
LINEAR
REGULATOR
SWITCHER1
CONTROL
IRU3018
Vout3
5V
Vout1
Vout2
3.3V
Figure 1 - Typical application of IRU3018.
2
Rev. 1.5
07/24/01
IRU3018
ELECTRICAL SPECIFICATIONS
PARAMETER SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
Supply UVLO Section
UVLO Threshold-12V
Supply Ramping Up
10
V
UVLO Hysteresis-12V
0.4
V
UVLO Threshold-5V
Supply Ramping Up
4.3
V
UVLO Hysteresis-5V
0.3
V
Supply Current
Operating Supply Current
I
12
V12
6
I
5
V5
20
mA
Switching Controller, Vcore (Vout 1)
VID Section
DAC Output Voltage (Note 1) V
DAC
0.99Vs
Vs
1.01Vs
V
DAC Output Line Regulation
0.1
%
DAC Output Temp Variation
0.5
%
VID Input LO
0.8
V
VID Input HI
2
V
VID Input Internal Pull-Up
27
K
Resistor to V5
Error Comparator Section
Input Bias Current
2
A
Input Offset Voltage
-2
+2
mV
Delay to Output
Vdiff=10mV
100
ns
Oscillator Section (Internal)
Osc Frequency
200
KHz
ABSOLUTE MAXIMUM RATINGS
V5 Supply Voltage .................................................... 7V
V12 Supply Voltage .................................................. 20V
Storage Temperature Range ...................................... -65C To 150C
Operating Junction Temperature Range ..................... 0C To 125C
PACKAGE INFORMATION
24-PIN WIDE BODY PLASTIC SOIC (W)
V12
VID4
VID3
VID2
VID1
VID0
PGood
V5
SS
Fault / Rt
Fb2
Vin2
Vout2
Gnd
Gate3
Fb3
En
Fb1
Vsen1
OCSet1
PGnd
LGate1
Phase1
UGate1
4
3
2
1
21
22
23
24
7
6
5
18
19
20
TOP VIEW
12
13
11
14
10
15
9
16
8
17
Unless otherwise specified, these specifications apply over V12=12V, V5=5V and T
A
=0 to 70C. Typical values refer
to T
A
=25C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
JA
=80!C/W
IRU3018
3
Rev. 1.5
07/24/01
Current Limit Section
CS Threshold Set Current
200
A
CS Comp Offset Voltage
-5
+5
mV
Hiccup Duty Cycle
Css=0.1F
10
%
Output Drivers Section
Rise Time
C
L
=3000pF
70
ns
Fall Time
C
L
=3000pF
70
ns
Dead Band Time Between
High Side and Synch Drive
Vcore Switcher Only
C
L
=3000pF
200
ns
2.5V Regulator (Vout 2)
Reference Voltage
Vo2
T
A
=25!C, Vout2=Fb2
1.260
V
Reference Voltage
1.260
V
Dropout Voltage
Io=200mA
0.6
V
Load Regulation
1mA< Io <200mA
0.5
%
Line Regulation
3.1V<Vin2<4V, Vo=2.5V
0.2
%
Input Bias Current
2
A
Output Current
200
mA
Current Limit
300
mA
Thermal Shutdown
145
!C
1.5V Regulator (Vout 3)
Reference Voltage
Vo3
T
A
=25!C, Gate3=Fb3
1.260
V
Reference Voltage
1.260
V
Input Bias Current
2
A
Output Drive Current
50
mA
Power Good Section
Core UV Lower Trip Point
Vsen1 Ramping Down
0.90Vs
V
Core UV Upper Trip Point
Vsen1 Ramping Up
0.92Vs
V
Core UV Hysterises
0.02Vs
V
Core OV Upper Trip Point
Vsen1 Ramping Up
1.10Vs
V
Core OV Lower Trip Point
Vsen1 Ramping Down
1.08Vs
V
Core OV Hysterises
0.02Vs
V
Fb2 Lower Trip Point
Fb2 Ramping Down
0.95
V
Fb2 Upper Trip Point
Fb2 Ramping Up
1.05
V
Fb3 Lower Trip Point
Fb3 Ramping Down
0.95
V
Fb3 Upper Trip Point
Fb3 Ramping Up
1.05
V
Power Good Output LO
R
L
=3mA
0.4
V
Power Good Output HI
R
L
=5K, Pull-Up to 5V
4.8
V
Fault (Overvoltage) Section
Core OV Upper Trip Point
Vsen1 Ramping Up
1.17Vs
V
Core OV Lower Trip Point
Vsen1 Ramping Down
1.15Vs
V
Vin2 Upper Trip Point
Vin2 Ramping Up
4.3
V
Vin2 Lower Trip Point
Vin2 Ramping Down
4.2
V
Fault Output HI
Io=3mA
10
V
Soft-Start Section
Pull-Up Resistor to 5V
OCSet=0V, Phase=5V
23
K
Enable Section
En Pin Input LO Voltage Venl
Regulator OFF
0.8 V
En Pin Input HI Voltage Venh
Regulator ON 2
V
En Pin Input LO Current
Ven=0V to 0.8V
0.01
A
En Pin Input HI Current
Ven=2V to 5V
20
A
PARAMETER SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
Note 1: Vs refers to the set point voltage given in Table 1
4
Rev. 1.5
07/24/01
IRU3018
This pin is connected to the 12 V supply and serves as the power Vcc pin for the output
drivers. A high frequency capacitor (typically 1F) must be placed close to this pin and
PGnd pin and be connected directly from this pin to the ground plane for the noise free
operation.
This pin selects a range of output voltages for the DAC. When in the LOW state the range
is 1.3V to 2.05V and when it switches to HI state the range is 2.0V to 3.5V. This pin is TTL
compatible that realizes a logic "1" as either HI or Open. When left open, this pin is pulled
up internally by a 27K resistor to 5V supply.
MSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic "1" as either HI or Open. When left open, this pin is pulled up internally by
a 27K resistor to 5V supply.
Input to the DAC that programs the output voltage. This pin is TTL compatible that realizes
a logic "1" as either HI or Open. When left open, this pin is pulled up internally by a 27K
resistor to 5V supply.
Input to the DAC that programs the output voltage. This pin is TTL compatible that realizes
a logic "1" as either HI or Open. When left open, this pin is pulled up internally by a 27K
resistor to 5V supply.
LSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic "1" as either HI or Open. When left open, this pin is pulled up internally by
a 27K resistor to 5V supply.
This pin is an open collector output that switches LO when any of the outputs are outside
of the specified under voltage trip point. It also switches low when Vsen1 pin is more than
10% above the DAC voltage setting.
5V supply voltage. A high frequency capacitor (0.1 to 1F) must be placed close to this
pin and connected from this pin to the ground plane for noise free operation.
This pin provides the soft start for the switching regulator. An internal resistor charges an
external capacitor that is connected from 5V supply to this pin which ramps up the out-
puts of the switching regulators, preventing the outputs from overshooting as well as
limiting the input current. The second function of the Soft Start cap is to provide long off
time (HICCUP) for the synchronous MOSFET during current limiting.
PIN DESCRIPTIONS
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
D4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
Table 1 - Set point voltage vs. VID codes
PIN# PIN SYMBOL PIN DESCRIPTION
1
2
3
4
5
6
7
8
9
V12
Vid4
Vid3
Vid2
Vid1
Vid0
PGood
V5
SS
IRU3018
5
Rev. 1.5
07/24/01
This pin has dual function. It acts as an output of the OVP circuitry or it can be used to
program the frequency using an external resistor. When used as a fault detector, if the
switcher output exceed the OVP trip point, the Fault pin switches to 12V and the soft-
start cap is discharged. If the Fault pin is to be connected to any external circuitry, it
needs to be buffered as shown in the application circuit.
This pin provides the feedback for the internal LDO regulator which its output is Vout4.
This pin is the input that provides power for the internal LDO regulator. It is also monitored
for the under-voltage and over-voltage conditions.
This pin is the output of the internal LDO regulator.
This pin serves as the ground pin and must be connected directly to the ground plane.
This pin controls the gate of an external transistor for the 1.5V GTL+ linear regulator.
This pin provides the feedback for the linear regulator which its output drive is Gate3.
This pin is a TTL compatible Enable pin. When this pin is left open or pulled high, the
device is enabled and when it is pulled low, it will disable the switcher and the LDO
controller (Vout3) leaving the internal 200mA regulator operational. When signal is given to
enable the device, both switcher and Vout3 will go through soft-start, the same as during
start-up.
This pin provides the feedback for the synchronous switching regulator. Typically this pin
can be connected directly to the output of the switching regulator. However, a resistor
divider is recommended to be connected from this pin to Vout1 and Gnd to adjust the
output voltage for any drop in the output voltage that is caused by the trace resistance.
The value of the resistor connected from Vout1 to Fb1 must be less than 100.
This pin is internally connected to the Under-voltage and over-voltage comparators sens-
ing the Vcore status. It must be connected directly to the Vcore supply.
This pin is connected to the Drain of the power MOSFET of the Core supply and it provides
the positive sensing for the internal current sensing circuitry. An external resistor pro-
grams the CS threshold depending on the R
DS
of the power MOSFET. An external capaci-
tor is placed in parallel with the programming resistor to provide high frequency noise
filtering.
This pin serves as the Power ground pin and must be connected directly to the ground
plane close to the source of the synchronous MOSFET. A high frequency capacitor (typi-
cally 1F) must be connected from V12 pin to this pin for noise free operation.
Output driver for the synchronous power MOSFET for the Core supply.
This pin is connected to the Source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
Output driver for the high side power MOSFET for the Core supply.
PIN# PIN SYMBOL PIN DESCRIPTION
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Fault / Rt
Fb2
Vin2
Vout2
Gnd
Gate3
Fb3
En
Fb1
Vsen1
OCSet1
PGnd
LGate1
Phase1
UGate1
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