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Электронный компонент: W24L01A-12

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Preliminary W24L01A
128K
8 HIGH SPEED CMOS STATIC RAM
Publication Release Date: April 26, 2002
- 1 - Revision A1
GENERAL DESCRIPTION
The W24L01A is a high speed, low power CMOS static RAM organized as 131072 x 8 bits that
operates on a single 3.3-volt power supply.This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
High speed access time:10/12/15 nS (max.)
Low power consumption:
-
Active: 300 mW (typ.)
Single +3.3V power supply
Three-state outputs
All inputs and outputs directly TTL/LVTTL
compatible
Available packages: 32-pin 300 mil SOJ, and
TSOP
Optional temperature range: 0 to 70
C and
-20 to 85
C
PIN CONFIGURATIIONS
1
2
3
4
5
2 4
2 5
2 6
2 7
2 8
6
7
8
9
2 0
2 1
2 2
2 3
1 0
1 1
1 2
1 3
1 6
1 7
1 8
1 9
1 4
1 5
3 2
3 1
3 0
2 9
1
2
3
4
5
6
7
8
9
11
12
14
15
16
32-pin
TSOP
32
31
30
29
27
26
25
24
23
22
21
20
19
18
17
10
13
28
A0
A1
A2
A3
CS#
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
WE#
A4
A5
A6
A7
A8
A9
A10
A11
A12
I/O5
I/O6
Vcc
Vss
I/O7
I/O8
OE#
A13
A14
A15
A16
A8
A9
A10
A11
A12
I/O5
I/O6
Vcc
Vss
I/O7
I/O8
OE#
A13
A14
A15
A16
A0
A1
A2
A4
CS#
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
WE#
A4
A5
A6
A7
BLOCK DIAGRAM
A0
.
CS1
A16
WE
I/O1
I/O8
OE
C O RE
V
V
.
.
DATA I/O
ARRAY
DECODER
CORE
CS2
.
CONTROL
DD
SS
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0
-
A16
Address Inputs
I/O1
-
I/O8
Data Inputs/Outputs
CS
Chip Select Inputs
WE
Write Enable Input
OE
Output Enable Input
V
DD
Power Supply
V
SS
Ground
NC
No Connection
Preliminary W24L01A
- 2 -
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Supply Voltage to V
SS
Potential
-0.5 to +4.6
V
Input/Output to V
SS
Potential
-0.5 to V
DD
+0.5
V
Allowable Power Dissipation
1.0
W
Storage Temperature
-65 to +150
C
Operating Temperature
W24L01AXXXX
0 to +70
C
W24L01AXXXE
-20 to +85
C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
TRUTH TABLE
CS1
CS2
OE
WE
MODE
I/O1
-
I/O8
V
DD
CURRENT
H
X
X
X
Not Selected
High Z
ISB, ISB1
X
L
X
X
Not Selected
High Z
ISB, ISB1
L
H
H
H
Output Disable
High Z
IDD
L
H
L
H
Read
Data Out
IDD
L
H
X
L
Write
Data In
IDD
OPERATING CHARACTERISTICS
(V
DD
= 3.3V
5%, V
SS
= 0V, T
A
= 0 to 70
C for 10/12/15 nS: -20 to 85
C for 12/15 nS)
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input Low Voltage
V
IL
-
-0.5
-
+0.8
V
Input High Voltage
V
IH
-
+2.0
-
V
DD
+0.5
V
Input Leakage Current
I
LI
VIN = V
SS
to V
DD
-10
-
+10
A
Output Leakage Current
I
LO
VI/O = V
SS
to V
DD
CS1 = V
IH
or CS2 = V
IL
or
OE = V
IH
or
WE = V
IL
-10
-
+10
A
Output Low Voltage
V
OL
I
OL
= +8.0 mA
-
-
0.4
V
Output High Voltage
V
OH
I
OH
= -4.0 mA
2.4
-
-
V
10
-
-
130
mA
12
-
-
120
mA
Operating Power Supply
Current
I
DD
CS1 = V
IL
,
CS2 = V
IH
I/O = 0 mA
Cycle = MIN
Duty = 100%
15
-
-
100
mA
I
SB
CS1
= V
IH
, or CS2 = V
IL
-
-
15
mA
Standby Power
Supply Current
I
SB1
CS1
V
DD
-0.2V or
CS2
0.2V
-
-
5
mA
Note: Typical characteristics are at V
DD
= 3.3V, T
A
= 25
C.
Preliminary W24L01A
Publication Release Date: April 26, 2002
- 3 - Revision A1
CAPACITANCE
(V
DD
= 3.3V, T
A
= 25
C, f = 1 MHz)
PARAMETER
SYM.
CONDITIONS
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
8
pF
Input/Output Capacitance
C
I/O
V
OUT
= 0V
10
pF
Note: These parameters are sampled but not 100% tested.
AC TEST CONDITIONS
PARAMETER
CONDITIONS
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3 nS
Input and Output Timing Reference Level
1.5V
Output Load
C
L
= 30 pF, I
OH
/I
OL
= -4 mA/8 mA
AC TEST LOADS AND WAVEFORM
90%
90%
3 nS
10%
3 nS
10%
R1 320 ohm
3.3V
OUTPUT
R2
350 ohm
30 pF
Including
Jig and
Scope
3.0V
0V
3.3V
OUTPUT
R1 320 ohm
5 pF
Including
Jig and
Scope
R2
350 ohm
(For T
CLZ1,
CLZ2,
OLZ,
CHZ1,
CHZ2,
OHZ,
WHZ,
OW
T
T
T
T
T
T
T
)
Preliminary W24L01A
- 4 -
AC CHARACTERISTICS
(V
DD
= 3.3V
5%, V
SS
= 0V, T
A
= 0 to 70
C for 10/12/15 nS ; -20 to 85
C for 12/15 nS)
Read Cycle
PARAMETER
SYM.
W24L01A-10 W24L01A-12
W24L01A-15 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
T
RC
10
-
12
-
15
-
nS
Address Access Time
T
AA
-
10
-
12
-
15
nS
Chip Select Access Time
T
ACS
-
10
-
12
-
15
nS
Output Enable to Output Valid
T
AOE
-
5
-
6
-
7
nS
Chip Selection to Output in Low Z
T
CLZ*
3
-
3
-
3
-
nS
Output Enable to Output in Low Z
T
OLZ*
0
-
0
-
0
-
nS
Chip Deselection to Output in High Z
T
CHZ*
-
5
-
6
-
7
nS
Output Disable to Output in High Z
T
OHZ*
-
5
-
6
-
7
nS
Output Hold from Address Change
T
OH
3
-
3
-
3
-
nS
*
These parameters are sampled but not 100% tested.
Write Cycle
W24L01A-10 W24L01A-12 W24L01A-15
PARAMETER
SYM.
MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time
T
WC
10
-
12
-
15
-
nS
Chip Selection to End of Write
T
CW1
9
-
10
-
13
nS
Address Valid to End of Write
T
AW
9
-
10
-
13
-
nS
Address Setup Time
T
AS
0
-
0
-
0
nS
Write Pulse Width
T
WP
9
-
10
-
10
-
nS
Write Recovery Time
CS
,
WE
T
WR
0
-
0
-
0
-
nS
Data Valid to End of Write
T
DW
5
-
7
-
9
-
nS
Data Hold from End of Write
T
DH
0
-
0
-
0
-
nS
Write to Output in High Z
T
WHZ
*
-
5
-
6
-
8
nS
Output Disable to Output in High Z
T
OHZ
*
-
5
-
6
-
8
nS
Output Active from End of Write
T
OW
0
-
0
-
0
-
nS
*
These parameters are sampled but not 100% tested.
Preliminary W24L01A
Publication Release Date: April 26, 2002
- 5 - Revision A1
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
T
T
T
T
D
OH
AA
RC
OH
OUT
Read Cycle 2
(Chip Select Controlled)
CS1
CS2
D
T
T
T
T
T
T
ACS1
ACS2
CLZ1
CLZ2
CHZ1
CHZ2
OUT
Read Cycle 3
(Output Enable Controlled)
Address
T
OE
CS1
CS2
D
T
T
T
T
T
T
T
T
T
T
T
OH
CHZ1
CHZ2
OHZ
AA
RC
AOE
CLZ1
ACS1
ACS2
CLZ2
OLZ
OUT