PRELIMINARY W925E/C240
8-bit CID Microcontroller
-1-
Release Date : 2002/5/13
Revision : A3
1
GENERAL DESCRIPTION...................................................................................................................... 3
2
FEATURES .................................................................................................................................................. 3
3
PIN CONFIGURATION............................................................................................................................ 5
4
PIN DESCRIPTION ................................................................................................................................... 6
5
BLOCK DIAGRAM ................................................................................................................................... 8
6
FUNCTIONAL DESCRIPTION .............................................................................................................. 9
6.1
M
EMORY
O
RGANIZATION
................................................................................................................... 10
6.2
S
PECIAL
F
UNCTION
R
EGISTERS
........................................................................................................... 13
6.3
I
NSTRUCTION
....................................................................................................................................... 30
6.4
P
OWER
M
ANAGEMENT
........................................................................................................................33
6.5
R
ESET
................................................................................................................................................... 34
6.6
I
NTERRUPT
........................................................................................................................................... 34
6.7
P
ROGRAMMABLE
T
IMERS
/C
OUNTERS
................................................................................................ 36
6.8
S
ERIAL
P
ORT
1 .....................................................................................................................................40
6.9
C
OMPARATOR
...................................................................................................................................... 41
6.10
DTMF G
ENERATOR
............................................................................................................................. 42
6.11
FSK G
ENERATOR
................................................................................................................................ 43
6.12
I/O P
ORTS
.............................................................................................................................................44
6.13
D
IVIDER
................................................................................................................................................45
6.14
C
ALLING
I
DENTITY
D
ELIVERY
(CID) ................................................................................................. 46
7
ELECTRICAL CHARACTERISTICS .................................................................................................59
7.1
M
AXIMUM
R
ATINGS
* .......................................................................................................................... 59
7.2
R
ECOMMENDED
O
PERATING
C
ONDITIONS
......................................................................................... 59
7.3
DC E
LECTRICAL
C
HARACTERISTICS
.................................................................................................. 59
7.4
E
LECTRICAL
C
HARACTERISTICS
- G
AIN
C
ONTROL
OP-A
MPLIFIER
.................................................. 61
7.5
AC E
LECTRICAL
C
HARACTERISTICS
.................................................................................................. 61
8
PACKAGE..................................................................................................................................................64
PRELIMINARY W925E/C240
8-bit CID Microcontroller
-2-
Release Date : 2002/5/13
Revision : A3
F
IGURE
3-1 W925E/C240 P
IN
C
ONFIGURATION
.................................................................................................. 5
F
IGURE
6-1 P
ROGRAM
M
EMORY
M
AP
................................................................................................................10
F
IGURE
6-2
MEMORY MAP
.................................................................................................................................... 11
F
IGURE
6-3 S
CRATCHPAD
RAM/R
EGISTER
A
DDRESSING
.................................................................................. 12
F
IGURE
6-4 T
HE
S
TRUCTURE OF
CID F
LAGS
...................................................................................................... 35
F
IGURE
6-5 M
ODE
0 & M
ODE
1
OF
T
IMER
/C
OUNTER
0 & 1.............................................................................. 37
F
IGURE
6-6 M
ODE
2
OF
T
IMER
/C
OUNTER
0 & 1 ................................................................................................ 38
F
IGURE
6-7 W
ATCHDOG
T
IMER
...........................................................................................................................39
F
IGURE
6-8 T
IMING OF THE
S
ERIAL
P
ORT
1 I
NPUT
F
UNCTION
........................................................................... 41
F
IGURE
6-9 T
IMING OF THE
S
ERIAL
P
ORT
1 O
UTPUT
F
UNCTION
....................................................................... 41
F
IGURE
6-10 T
HE
C
ONFIGURATION OF
C
OMPARATOR
....................................................................................... 42
F
IGURE
6-11 T
HE
R
ELATION
B
ETWEEN
DTMF
AND
K
EYPAD
........................................................................... 42
F
IGURE
6-12 FSK M
ODULATOR
.......................................................................................................................... 43
F
IGURE
6-13 13/14-
BIT
D
IVIDER
......................................................................................................................... 45
F
IGURE
6-14 T
HE
CID B
LOCK
D
IAGRAM
........................................................................................................... 46
F
IGURE
6-15 A
PPLICATION
C
IRCUIT OF THE
R
ING
D
ETECTOR
........................................................................... 47
F
IGURE
6-16 D
IFFERENTIAL
I
NPUT
G
AIN
C
ONTROL
C
IRCUIT
............................................................................48
F
IGURE
6-17 S
INGLE
-E
NDED
I
NPUT
G
AIN
C
ONTROL
C
IRCUIT
........................................................................... 48
F
IGURE
6-18 G
UARD
T
IME
W
AVEFORM OF
A
LERT
T
ONE
S
IGNAL
D
ETECTION
................................................49
F
IGURE
6-19 T
HE
W
AVEFORM OF
DTMF D
ETECTION
....................................................................................... 50
F
IGURE
6-20 FSK D
ETECTION
E
NABLE AND
FSK C
ARRIER
P
RESENT AND
A
BSENT
T
IMING
.......................... 50
F
IGURE
6-21 S
ERIAL
D
ATA
I
NTERFACE
T
IMING OF
FSK D
EMODULATION
....................................................... 51
F
IGURE
6-22 I
NTERNAL
CID G
AIN
C
ONTROL
R
EGISTER
S
ETTING
W
AVEFORM
............................................... 52
F
IGURE
6-23 A
PPLICATION
C
IRCUIT OF
CID ...................................................................................................... 53
F
IGURE
6-24 I
NPUT AND
O
UTPUT
T
IMING OF
B
ELLCORE
O
N
-
HOOK
D
ATA
T
RANSMISSION
............................. 54
F
IGURE
6-25 I
NPUT AND
O
UTPUT
T
IMING OF
B
ELLCORE
O
FF
-
HOOK
D
ATA
T
RANSMISSION
............................55
F
IGURE
6-26 I
NPUT AND
O
UTPUT
T
IMING OF
BT I
DLE
S
TATE
(O
N
-
HOOK
) D
ATA
T
RANSMISSION
.................. 56
F
IGURE
6-27 I
NPUT AND
O
UTPUT
T
IMING OF
BT L
OOP
S
TATE
(O
FF
-
HOOK
) D
ATA
T
RANSMISSION
............... 57
F
IGURE
6-28 I
NPUT AND
O
UTPUT
T
IMING OF
CCA C
ALLER
D
ISPLAY
S
ERVICE
D
ATA
T
RANSMISSION
.......... 58
PRELIMINARY W925E/C240
8-bit CID Microcontroller
-3-
Release Date : 2002/5/13
Revision : A3
1 GENERAL DESCRIPTION
The W925E/C240 is an all-in-1 single 8-bit micro-controller with widely used Calling Identity
Delivery (CID) function. The 8-bit CPU core is based on the 8051 family; therefore, all the
instructions are compatible to the 8051 series. The CID part consists FSK decoder, DTMF
receiver, CPE* Alert Signal (CAS) detector and Ring detector. Also built-in DTMF generator and
FSK generator with baud rate 1200 bps (bits/sec). Using W925E/C240 can easily implement the
CID adjunct box and the feature phone or Short Message Service (SMS) phone with CID function.
The main features are listed in the next section.
2 FEATURES
APPLICATION: The SMS phone with CID function and CID adjunct box.
CPU: 8-bit micro-controller is similar to the 8051 family.
- Operating voltage:
C: 2.2 to 5.5 volt.
CID: 3.0 to 5.5 volt.
Dual-clock operation:
- Main oscillator: 3.58MHz crystal for CID and DTMF function. And built-in RC oscillator.
- Sub oscillator: 32768Hz crystal.
- Main and sub oscillators are enable/disable by bit control individually.
ROM: 256K bytes internal flash EEPROM/MASK ROM type.
- Up 128K bytes for program ROM.
- Total 256K bytes for look-up table ROM.
- Separate 256K into 4 pages, each page is 64K addressable.
RAM:
- 256 bytes on chip scratch-pad RAM.
- 8K bytes on chip RAM for MOVX instruction.
CID
- Compatible with Bellcore TR-NWT-000030 & SR-TSV-002476, British Telecom(BT)
SIN227, U.K. Cable Communication Association(CCA) specification.
- FSK modulator/demodulator: for Bell 202 and ITU-T V.23 FSK with 1200 baud rate.
- CAS detector: for dual tones of Bellcore CAS and BT Idle State and Loop State Dual
Tone Alert Signal (DTAS).
- DTMF generator/receiver; DTMF receiver can be programmed as a tone detector.
- Ring detector: for line reversal for BT, ring burst for CCA or ring signal for Bellcore.
- Two independent OP amps with adjustable gain for Tip/Ring and Telephone Hybrid
connections.
I/O: 40 I/O pins.
- P0: Bit and byte addressable. I/O mode can be bit controlled. Open drain type.
- P1~P3: Bit and byte addressable. Pull high and I/O mode can be bit controlled.
- P4: Byte addressable . Pull high and I/O mode can be bit controlled.
note: "CPE*" Customer Premises Equipment
PRELIMINARY W925E/C240
8-bit CID Microcontroller
-4-
Release Date : 2002/5/13
Revision : A3
Power mode:
- Normal mode: Normal operation.
- Dual-clock slow operation mode: System is operated by the sub-oscillator (Fosc=Fs
and Fm is stopped)
- Idle mode: CPU hold. The clock to the CPU is halted, but the interrupt, timer and
watchdog timer block work normally but CID function is disabled.
- Power down mode: All activity is completely stopped and power consumption is less
than 1
A.
Timer: 2 13/16-bit timers, or 8-bit auto-reload timers, that are Timer0 and Timer1.
Watchdog timer: WDT can be programmed by the user to serve as a system monitor.
Interrupt: 11 interrupt sources with two levels of priority.
- 4 interrupts from INT0, INT1, INT2 and INT3.
- 2 interrupts from Timer0, Timer1.
- 1 interrupt from Serial port.
- 1 interrupt from CID.
- 1 interrupt from 13/14-bit Divider.
- 1 interrupt from Comparator.
- 1 interrupt from Watch Dog Timer.
Divider: 13/14 bit divider, clock source from sub-oscillator, therefore, DIVF set every 0.25/0.5
second.
Comparator:
- Comparator: 1 analog inputs from VNEG pin, 2 reference input pins, one is from VPOS
pin and another is from internal regulator output.
Serial port:
- An 8-bit serial transceiver with SCLK and SDATA.
.
Package:
- 100pin QFP
PRELIMINARY W925E/C240
8-bit CID Microcontroller
-5-
Release Date : 2002/5/13
Revision : A3
3 PIN CONFIGURATION
Figure 3-1 shows the pin assignment. The package type is 100pin QFP.
W925E/C240
BUZ
79
EA/DATA
80
TEST/MODE
78
P17
77
P16
76
P15
75
P14
74
P13
73
P12
72
P11
71
P10
70
P27
69
P26
68
P25
67
P24
66
P23
65
P22
64
P21
63
P20
62
P37
61
P36
60
P35
59
P34
58
P33
57
P32
56
P31
55
P30
54
P47
53
P46
52
P45
51
P44/VPOS
50
P43
49
P42/VNEG
48
P41
47
P40
46
DTMF/FSK
45
NC
42
NC
41
NC
30
NC
29
NC
28
NC
27
NC
26
NC
25
NC
24
NC
23
NC
22
NC
21
NC
20
NC
19
NC
18
NC
17
NC
16
NC
15
NC
14
NC
13
NC
12
NC
11
NC
10
NC
9
NC
8
NC
7
NC
6
NC
5
NC
4
NC
3
NC
2
NC
1
NC
100
NC
99
NC
98
NC
97
NC
96
INP2
40
INN2
39
GCFB2
38
VAS
37
VAD
36
GCFB1
35
INN1
34
INP1
33
VREF
32
CAP
31
RNGDI
44
RNGRC
43
P07
95
P06
94
P05
93
P04
92
P03
91
P02
90
P01
89
P00
88
VSS
87
XOUT1
86
XIN1
85
RESET/VPP
84
VDD
83
XIN2
82
XOUT2
81
Figure 3-1 W925E/C240 Pin Configuration
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