W986432DH
512K
4 BANKS
32 BITS SDRAM
Publication Release Date: July 30, 2002
- 1 - Revision A5
Table of Contents-
1. GENERAL DESCRIPTION ..................................................................................................................3
2. FEATURES ..........................................................................................................................................3
3. AVAILABLE PART NUMBER...............................................................................................................3
4. PIN CONFIGURATION ........................................................................................................................4
5. PIN DESCRIPTION..............................................................................................................................5
6. BLOCK DIAGRAM ...............................................................................................................................6
7. FUNCTIONAL DESCRIPTION ............................................................................................................7
Power Up and Initialization................................................................................................................7
Programming Mode Register............................................................................................................7
Bank Activate Command ..................................................................................................................7
Read and Write Access Modes ........................................................................................................7
Burst Read Command ......................................................................................................................8
Burst Command................................................................................................................................8
Read Interrupted by a Read..............................................................................................................8
Read Interrupted by a Write..............................................................................................................8
Write Interrupted by a Write..............................................................................................................8
Write Interrupted by a Read..............................................................................................................8
Burst Stop Command .......................................................................................................................8
Addressing Sequence of Sequential Mode.......................................................................................9
Addressing Sequence of Interleave Mode ........................................................................................9
Auto-precharge Command .............................................................................................................10
Precharge Command......................................................................................................................10
Self Refresh Command ..................................................................................................................10
Power Down Mode..........................................................................................................................10
No Operation Command.................................................................................................................11
Deselect Command ........................................................................................................................11
Clock Suspend Mode......................................................................................................................11
8. TABLE OF OPERATING MODES .....................................................................................................12
9. SIMPLIFIED STATE DIAGRAM.........................................................................................................13
10. DC CHARACTERISTICS .................................................................................................................14
Absolute Maximum Rating..............................................................................................................14
11. RECOMMENDED DC OPERATING CONDITIONS ........................................................................14
12. CAPACITANCE................................................................................................................................14
13. DC CHARACTERISTICS .................................................................................................................15
W986432DH
- 2 -
14. AC CHARACTERISTICS .................................................................................................................16
15. TIMING WAVEFORMS....................................................................................................................19
Command Input Timing ..................................................................................................................19
Timing Waveforms, continued
.................................................................................................................20
Read Timing ...................................................................................................................................20
Timing Waveforms, continued
.................................................................................................................21
Control Timing of Input Data...........................................................................................................21
Timing Waveforms, continued
.................................................................................................................22
Control Timing of Output Data ........................................................................................................22
Timing Waveforms, continued
.................................................................................................................23
Mode Register Set Cycle ................................................................................................................23
16. OPERATING TIMING EXAMPLE ....................................................................................................24
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ........................................................24
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge)...............................25
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ........................................................26
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge)...............................27
Interleaved Bank Write (Burst Length = 8) .....................................................................................28
Interleaved Bank Write (Burst Length = 8, Autoprecharge)............................................................29
Page Mode Read (Burst Length = 4, CAS Latency = 3) .................................................................30
Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) .......................................................31
Autoprecharge Read (Burst Length = 4, CAS Latency = 3)............................................................32
Autoprecharge Write (Burst Length = 4).........................................................................................33
Autorefresh Cycle ...........................................................................................................................34
Self-refresh Cycle ...........................................................................................................................35
Bust Read and Single Write (Burst Length = 4, CAS Latency = 3).................................................36
Power-down Mode ..........................................................................................................................37
Auto-precharge Timing (Write Cycle) .............................................................................................38
Auto-precharge Timing (Read Cycle) .............................................................................................39
Timing Chart of Read to Write Cycle ..............................................................................................40
Timing Chart of Write to Read Cycle ..............................................................................................41
Timing Chart of Burst Stop Cycle (Burst Stop Command) .............................................................42
Timing Chart of Burst Stop Cycle (Precharge Command)..............................................................43
CKE/DQM Input Timing (Write Cycle) ............................................................................................44
CKE/DQM Input Timing (Read Cycle) ............................................................................................45
Self Refresh/Power Down Mode Exit Timing..................................................................................46
17. PACKAGE DIMENSION ..................................................................................................................47
86L TSOP (II)-400 mil.....................................................................................................................47
18. VERSION HISTORY ........................................................................................................................48
W986432DH
Publication Release Date: July 30, 2002
- 3 - Revision A5
1. GENERAL DESCRIPTION
W986432DH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words x 4 banks x 32 bits. Using pipelined architecture and 0.175
m process technology,
W986432DH delivers a data bandwidth of up to 800M bytes per second (-5). For different application,
W986432DH is sorted into the following speed grades: -5, -6, -7. The -5 parts can run up to 200
MHz/CL3. The -6 parts can run up to 166 MHz/CL3. The -7 parts can run up to 143 MHz/CL3. For
handheld device application, we also provide low power option, the grade of -7L, with Self Refresh
Current under 400
A and work well at 2.7V during Self Refresh Mode. For special application, we
provide extended temperature option the grade of -6I can work well in wide temperature from -25
C to
85
C.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W986432DH is ideal for main memory in
high performance applications.
2. FEATURES
3.3V
0.3V power supply
524288 words
x 4 banks x 32 bits organization
Self Refresh Current: Standard and Low Power
CAS latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Sequential and Interleave burst
Burst read, single write operation
Byte data controlled by DQM
Power-down Mode
Auto-precharge and controlled precharge
4K refresh cycles/64 mS
Interface: LVTTL
Packaged in 86-pin TSOP II, 400 mil - 0.50
3. AVAILABLE PART NUMBER
PART NUMBER
SPEED (CL = 3)
SELF REFRESH
CURRENT (MAX.)
OPERATING
TEMPERATURE
W986432DH-5
200 MHz
1 mA
0
C
-
70
C
W986432DH-6
166 MHz
1 mA
0
C
-
70
C
W986432DH-6I
166 MHz
400
A
-25
C
-
85
C
W986432DH-7
143 MHz
1 mA
0
C
-
70
C
W986432DH-7L
143 MHz
400
A
0
C
-
70
C
W986432DH
- 4 -
4. PIN CONFIGURATION
86
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
37
38
39
40
41
42
43
28
29
30
31
32
33
34
35
36
50
49
48
47
46
45
44
58
57
56
55
54
53
52
51
85
V
ss
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
CC
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
CC
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
VCC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
VSSQ
DQ7
NC
VCC
DQM0
WE
CAS
RAS
CS
NC
BS0
BS1
A10/AP
A0
A1
A2
DQM2
V
CC
NC
DQ16
V
SS
Q
DQ17
DQ18
V
CC
Q
DQ19
DQ20
V
SS
Q
DQ21
DQ22
V
CC
Q
DQ23
V
CC
W986432DH
Publication Release Date: July 30, 2002
- 5 - Revision A5
5. PIN DESCRIPTION
PIN NUMBER
PIN NAME
FUNCTION
DESCRIPTION
24, 25, 26, 27, 60,
61, 62, 63, 64, 65, 66
A0
-
A10
Address
Multiplexed pins for row and column address.
Row address: A0
-
A10. Column address:
A0
-
A7. A10 is sampled during a precharge
command to determine if all banks are to be
precharged or bank selected by BS0, BS1.
22, 23
BS0, BS1
Bank Select
Select bank to activate during row address
latch time, or bank to read/write during
address latch time.
2, 4, 5, 7, 8, 10, 11, 13, 31,
33, 34, 36, 37, 39, 40, 42, 45,
47, 48, 50, 51, 53, 54, 56, 74,
76, 77, 79, 80, 82, 83, 85
DQ0
-
DQ31
Data Input/
Output
Multiplexed pins for data output and input.
20
CS
Chip Select
Disable or enable the command decoder.
When command decoder is disabled, new
command is ignored and previous operation
continues.
19
RAS
Row Address
Strobe
Command input. When sampled at the rising
edge of the clock RAS , CAS and WE
define the operation to be executed.
18
CAS
Column
Address Strobe Referred to RAS
17
WE
Write Enable Referred to RAS
16, 28, 59, 71
DQM0
-
DQM3
Input/Output
Mask
The output buffer is placed at Hi-Z (with
latency of 2) when DQM is sampled high in
read cycle. In write cycle, sampling DQM high
will block the write operation with zero latency.
68
CLK
Clock Inputs
System clock used to sample inputs on the
rising edge of clock.
67
CKE
Clock Enable
CKE controls the clock activation and
deactivation. When CKE is low, Power Down
mode, Suspend mode, or Self Refresh mode
is entered.
1, 15, 29, 43
V
CC
Power (+3.3V)
Power for input buffers and logic circuit inside
DRAM.
44, 58, 72, 86
V
SS
Ground
Ground for input buffers and logic circuit
inside DRAM.
3, 9, 35, 41, 49, 55, 75, 81
V
CCQ
Power (+3.3V)
for I/O Buffer
Separated power from V
CC
, to improve DQ
noise immunity.
6, 12, 32, 38, 46, 52, 78, 84
V
SSQ
Ground for I/O
Buffer
Separated ground from V
SS
, to improve DQ
noise immunity.
14, 21, 30, 57, 69, 70, 73
NC
No Connection No connection
W986432DH
- 6 -
6. BLOCK DIAGRAM
DQ0
DQ31
DQM0~3
CLK
CKE
A10
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #2
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #0
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #3
DATA CONTROL
CIRCUIT
DQ
BUFFER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #1
NOTE:
The cell array configuration is 2048 * 256 * 32
ROW DECODER
ROW DECODER
ROW DECODER
ROW DECODER
A0
A9
BS0
BS1
CS
RAS
CAS
WE
W986432DH
Publication Release Date: July 30, 2002
- 7 - Revision A5
7. FUNCTIONAL DESCRIPTION
Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and initialization
sequence need to be followed to guarantee the device being preconditioned to each user specific
needs.
During power up, all V
CC
and V
CCQ
pins must be ramp up simultaneously to the specified voltage
when the input signals are held in the "NOP" state. The power up voltage must not exceed V
CC
+0.3V
on any of the input pins or V
CC
supplies. After power up, an initial pause of 200
S is required followed
by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus
during power up, it is required that the DQM and CKE pins be held high during the initial pause period.
Once all banks have been precharged, the Mode Register Set Command must be issued to initialize
the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after
programming the Mode Register to ensure proper subsequent operation.
Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation. All
banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data
during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A
new command may be issued following the mode register set command once a delay equal to t
RSC
has
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (t
RCD
). Once a bank has been activated it must be precharged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t
RC
).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank to Bank delay time (t
RRD
). The maximum time that each bank can be held active is
specified as T
RAS
(max.).
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting
RAS high and CAS low at the clock rising edge after minimum of t
RCD
delay. WE pin voltage
level defines whether the access cycle is a read operation ( WE high), or a write operation ( WE
low). The address inputs determine the starting column address. Reading or writing to a different row
within an activated bank requires the bank be precharged and a new Bank Activate command be
issued. When more than one bank is activated, interleaved bank Read or Write operations are
possible. By using the programmed burst length and alternating the access and precharge operations
between multiple banks, seamless data access operation among many different pages can be
realized. Read or Write Commands can also be issued to the same bank or between active banks on
every clock cycle.
W986432DH
- 8 -
Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding
RAS and WE high at the rising edge of the clock. The address inputs determine the starting
column address for the burst. The Mode Register sets type of burst (sequential or interleave) and
the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next
page explain the address sequence of interleave mode and sequence mode.
Burst Command
The Burst Write command is initiated by applying logic low level to CS , CAS and WE while
holding RAS high at the rising edge of the clock. The address inputs determine the starting column
address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle
that the Write Command is issued. The remaining data inputs must be supplied on each subsequent
rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes
will be ignored.
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS latency from the
interrupting Read Command the is satisfied.
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data will
be written into the device until the programmed burst length is satisfied.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open
for future Read or Write Commands to the same page of the active bank, if the burst length is full
page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop
Command is defined by having RAS and CAS high with CS and WE low at the rising
edge of the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS
Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued during a
full page burst write operation, then any residual data from the burst write cycle will be ignored.
W986432DH
Publication Release Date: July 30, 2002
- 9 - Revision A5
Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to the
device. The disturb address is varied by the Burst Length as shown in Table 1.
Table 1. Address Sequence of Sequential Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
n
BL = 2 (disturb address is A0)
Data 1
n + 1
No address carry from A0 to A1
Data 2
n + 2
BL = 4 (disturb addresses are A0 and A1)
Data 3
n + 3
No address carry from A1 to A2
Data 4
n + 4
Data 5
n + 5
BL = 8 (disturb addresses are A0, A1 and A2)
Data 6
n + 6
No address carry from A2 to A3
Data 7
n + 7
Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit in
the sequence shown in Table 2.
Table 2. Address Sequence of Interleave Mode
DATA
ACCESS ADDRESS
BUST LENGTH
Data 0
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 2
Data 1
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 4
Data 3
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 4
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 8
Data 5
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 6
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 7
A8 A7 A6 A5 A4 A3 A2 A1 A0
W986432DH
- 10 -
Auto-precharge Command
If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is
entered. During auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by CAS latency.
A Read or Write Command with auto-precharge cannot be interrupted before the entire burst operation
is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is prohibited
during a read or write cycle with auto-precharge. Once the precharge operation has started, the bank
cannot be reactivated until the Precharge time (t
RP
) has been satisfied. Issue of Auto-Precharge
command is illegal if the burst is set to full page length. If A10 is high when a Write Command is
issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the
precharge operation one clock delay from the last burst write cycle. This delay is referred to as write
t
DPL
. The bank undergoing auto-precharge cannot be reactivated until t
DPL
and t
RP
are satisfied. This is
referred to as t
DAL
, Data-in to Active delay (t
DAL
= t
WR
+ t
RP
). When using the Auto-precharge Command,
the interval between the Bank Activate Command and the beginning of the internal precharge
operation must satisfy t
RAS
(min).
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when CS , RAS and WE are low and CAS is high at the
rising edge of the clock. The Precharge Command can be used to precharge each bank separately or
all banks simultaneously. Three address bits, A10, BS0, and BS1 are used to define which bank(s) is
to be precharged when the command is issued. After the Precharge Command is issued, the
precharged bank must be reactivated before a new read or write access can be executed. The delay
between the Precharge Command and the Activate Command must be greater than or equal to the
Precharge time (t
RP
).
Self Refresh Command
The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE
high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will
exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the
device exits Self Refresh Operation and before the next command can be issued. This delay is equal
to the t
AC
cycle time plus the Self Refresh exit time.
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and
just after exiting the self refresh mode.
Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (t
REF
) of the
device.
W986432DH
Publication Release Date: July 30, 2002
- 11 - Revision A5
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on t
CK
. The input buffers need to be
enabled with CKE held high for a period equal to t
CKS
(min.) + t
CK
(min.).
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS , CAS , and WE held high at the rising
edge of the clock. A No Operation Command will not terminate a previous operation that is still
executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when CS is brought high, the RAS , CAS , and WE signals become don't
cares.
Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
W986432DH
- 12 -
8. TABLE OF OPERATING MODES
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 3 shows the truth table for the operation commands.
Table 3. Truth Table
(Note (1), (2))
COMMAND
DEVICE
STATE
CKEn-1 CKEn DQM BS0, 1 A10 A0
-
A9 CS RAS CAS
WE
Bank Active
Idle
H
x
x
v
v
V
L
L
H
H
Bank Precharge
Any
H
x
x
v
L
x
L
L
H
L
Precharge All
Any
H
x
x
x
H
x
L
L
H
L
Write
Active (3)
H
x
x
v
L
v
L
H
L
L
Write with Autoprecharge Active (3)
H
x
x
v
H
v
L
H
L
L
Read
Active (3)
H
x
x
v
L
v
L
H
L
H
Read with Autoprecharge Active (3)
H
x
x
v
H
v
L
H
L
H
Mode Register Set
Idle
H
x
x
v
v
v
L
L
L
L
No-Operation
Any
H
x
x
x
x
x
L
H
H
H
Burst Stop
Active (4)
H
x
x
x
x
x
L
H
H
L
Device Deselect
Any
H
x
x
x
x
x
H
x
x
x
Auto-Refresh
Idle
H
H
x
x
x
x
L
L
L
H
Self-Refresh Entry
Idle
H
L
x
x
x
x
L
L
L
H
Self Refresh Exit
Idle
(S.R)
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
H
x
H
x
x
Clock suspend Mode
Entry
Active
H
L
x
x
x
x
x
x
x
x
Power Down Mode Entry
Idle
Active (5)
H
H
L
L
x
x
x
x
x
x
x
x
H
L
x
H
x
H
X
H
Clock Suspend Mode
Exit
Active
L
H
x
x
x
x
x
x
x
X
Power Down Mode Exit
Any
(power
down)
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
H
x
H
X
H
Data write/Output Enable Active
H
x
L
x
x
x
x
x
x
x
Data Write/Output
Disable
Active
H
x
H
x
x
x
x
x
x
x
Notes:
(1) v = valid, x = Don't care, L = Low Level, H = High Level
(2) CKEn signal is input leve l when commands are provided.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
W986432DH
Publication Release Date: July 30, 2002
- 13 - Revision A5
9. SIMPLIFIED STATE DIAGRAM
Mode
Register
Set
IDLE
CBR
Refresh
Self
Refresh
ROW
ACTIVE
Power
Down
Precharge
POWER
ON
Active
Power
Down
WRITE
WRITE
SUSPEND
WRITEA
WRITEA
SUSPEND
READ
SUSPEND
READ
READA
SUSPEND
READA
Precharge
MRS
REF
ACT
CKE
CKE
CKE
CKE
CKE
CKE
CKE
CKE
CKE
CKE
SELF
SELF exit
CKE
CKE
Write with
Read
Write
Auto precharge
Auto precharge
Read with
Write
Write
Read
PRE(precharge termination)
PRE(precharge termination)
Read
BST
BST
PRE
Manual input
Automatic sequence
MRS = Mode Register Set
REF = Refresh
ACT = Active
PRE = Precharge
WRITEA = Write with Auto precharge
READA = Read with Auto precharge
W986432DH
- 14 -
10. DC CHARACTERISTICS
Absolute Maximum Rating
PARAMETER
SYM.
RATING
UNIT
NOTES
Input, Column Output Voltage
V
IN
, V
OUT
-0.3
-
V
CC
+0.3
V
1
Power Supply Voltage
V
CC,
V
CCQ
-0.3
-
4.6
V
1
Operating Temperature (-5/-6/-7/-7L)
T
OPR
0
-
70
C
1
Operating Temperature(6I)
T
OPR
-25
-
85
C
1
Storage Temperature
T
STG
-55
-
150
C
1
Soldering Temperature (10s)
T
SOLDER
260
C
1
Power Dissipation
P
D
1
W
1
Short Circuit Output Current
I
OUT
50
mA
1
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
11. RECOMMENDED DC OPERATING CONDITIONS
(T
A
= 0 to 70
C)
PARAMETER
SYM. MIN.
TYP.
MAX.
UNIT NOTES
Power Supply Voltage
V
CC
3.0
3.3
3.6
V
2
Supply voltage for W986432DH-7L
during self refresh mode
V
CC
2.7
3.3
3.6
V
2
Power Supply Voltage (for I/O Buffer)
V
CCQ
3.0
3.3
3.6
V
2
Input High Voltage
V
IH
2.0
-
V
CC
+0.3
V
2
Input Low Voltage
V
IL
-0.3
-
0.8
V
2
Note: V
IH
(max.) = V
CC
/V
CCQ
+1.2V for pulse width < 5 nS
V
IL
(min.) = V
SS
/V
SSQ
-1.2V for pulse width < 5 nS
12. CAPACITANCE
(V
CC
= 3.3V, T
A
= 25
C, f = 1 MHz)
PARAMETER
SYM.
MIN.
MAX. UNIT
Input Capacitance
(A0 to A11, BS0, BS1, CS , RAS , CAS , WE , CKE)
C
i1
2.5
4
pF
Input Capacitance (CLK)
C
CLK
2.5
4
pF
Input/Output Capacitance (DQ0
-
DQ15)
C
o
4
6.5
pF
Input Capacitance DQM
C
i2
3.0
5.5
pF
Note: These parameters are periodically sampled and not 100% tested
W986432DH
Publication Release Date: July 30, 2002
- 15 - Revision A5
13. DC CHARACTERISTICS
(V
CC
= 3.3V
0.3V, T
A
= 0
-
70
C for -5/-6/-7/-7L,T
A
= -25 to 85
C for -6I)
-5
-6/-6I
-7/-7L
PARAMETER
SYM.
MAX.
MAX.
MAX.
UNIT NOTES
Operating Current
t
CK
= min., t
RC
= min.
Active precharge command
cycling without burst operation
1 bank operation
I
CC1
110
90
80
3
Standby Current
t
CK
= min.,
CS
= V
IH
V
IH/L
= V
IH
(min.)/V
IL
(max.)
CKE = V
IH
I
CC2
45
35
30
3
Bank: inactive state
CKE = V
IL
(Power
Down mode)
I
CC2P
1
1
1
3
Standby Current
CLK = V
IL
,
CS
= V
IH
V
IH/L
= V
IH
(min.)/V
IL
(max.)
CKE = V
IH
I
CC2S
8
8
8
BANK: inactive state
CKE = V
IL
(Power
Down mode)
I
CC2PS
1
1
1
mA
No Operating Current
t
CK
= min.,
CS
= V
IH
(min.)
CKE = V
IH
I
CC3
70
60
55
BANK: active state (4 banks)
CKE = V
IL
(Power
Down mode)
I
CC3P
5
5
5
Burst Operating Current (t
CK
= min.)
Read/Write command cycling
I
CC4
190
165
145
3, 4
Auto Refresh Current (t
CK
= min.)
Auto refresh command cycling
I
CC5
125
120
110
3
Standard (-5/-6/-7)
I
CC6
1
1
1
Self Refresh Current
CKE = 0.2V
Self refresh mode
Low Power(-6I/,-7L)
I
CC6L
-
400
400
A
PARAMETER
SYMBOL
MIN.
MAX.
UNIT NOTES
Input Leakage Current
(0V
V
IN
V
CC
, all other pins not under test = 0V)
I
I
(L)
-5
5
A
Output Leakage Current
(Output disable, 0V
V
OUT
V
CCQ
)
V
O
(L)
-5
5
A
LVTTL Output
H
Level Voltage
(I
OUT
= -2 mA)
V
OH
2.4
-
V
LVTTL Output
"
L
Level Voltage
(I
OUT
= 2 mA)
V
OL
-
0.4
V
W986432DH
- 16 -
14. AC CHARACTERISTICS
(V
CC
= 3.3V
0.3V, V
SS
= 0V, T
A
= 0 to 70
C for -5/-6/-7/-7L,T
A
= -40 to 85
C for -6I) (Notes: 5, 6.)
-5
-6/-6I
-7/-7L
PARAMETER
SYM.
MIN. MAX. MIN. MAX. MIN. MAX.
UNIT NOTE
Ref/Active to Ref/Active Command Period
t
RC
54
60
65
nS
Active to precharge Command Period
t
RAS
40 100000 42 100000 45 100000
Active to Read/Write Command Delay Time
t
RCD
14
18
20
Read/Write(a) to Read/Write(b) Command
Period
t
CCD
1
1
1
Cycle
Precharge to Active(b) Command Period
t
RP
14
18
20
nS
Active(a) to Active(b) Command Period
t
RRD
10
12
14
7
7.5
8
Wreite Recovery Time CL* = 2
CL* = 3
t
WR
5
6
7
7
1000
7.5
1000
8
1000
CLK Cycle Time CL* = 2
CL* = 3
t
CK
5
1000
6
1000
7
1000
CLK High Level
t
CH
2
2
2
CLK Low Level
t
CL
2
2
2
5.5
5.5
6
Access Time from CLK CL* = 2
CL* = 3
t
AC
4.5
5
5.5
Output Data Hold Time
t
OH
1.5
2
2
Output Data High Impedance Time
t
HZ
1.5
5
2
6
2
7
Output Data Low Impedance Time
t
LZ
0
0
0
Power Down Mode Entry Time
t
SB
0
5
0
6
0
7
Transition Time of CLK (Rise and Fall)
t
T
0.5
10
0.5
10
0.5
10
Data-in-Set-up Time
t
DS
1.5.
1.5
1.5
Data-in Hold Time
t
DH
1
1
1
Address Set-up Time
t
AS
1.5
1.5
1.5
Address Hold Time
t
AH
1
1
1
CKE Set-up Time
t
CKS
1.5
1.5
1.5
CKE Hold Time
t
CKH
1
1
1
Command Set-up Time
t
CMS
1.5
1.5
1.5
Command Hold Time
t
CMH
1
1
1
Refresh Time
t
REF
64
64
64
mS
Mode Register Set Cycle Time
t
RSC
10
12
14
nS
Notes:
1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices.
2. All voltages are referenced to V
SS
.
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of t
CK
and t
RC
.
4. These parameters depend on the output loading conditions. Specified values are obtained with output open.
W986432DH
Publication Release Date: July 30, 2002
- 17 - Revision A5
5. Power up Sequence
(1) Power up must be performed in the following sequence.
(2) Power must be applied to V
CC
and V
CCQ
(simultaneously) while all input signals are held in the "NOP" state. The CLK
signals must be started at the same time.
(3) After power-up a pause of at least 200
S is required. It is required that DQM and CKE signals then be held "high"
(V
CC
levels) to ensure that the DQ output is impedance.
(4) All banks must be precharged.
(5) The Mode Register Set command must be asserted to initialize the Mode Register.
(6) A minimum of eight Auto Refresh dummy cycles is required to stabilize the internal circuitry of the device.
6. AC Testing Conditions
PARAMETER
CONDITIONS
Output Reference Level
1.4V
Output Load
See diagram below
Input Signal Levels (VIH/VIL)
2.4V/0.4V
Transition Time (Rise and Fall) of Input Signal
1 nS
Input Reference Level
1.4V
50 ohms
1.4 V
AC TEST LOAD
Z = 50 ohms
output
30pF
1. Transition times are measured between V
IH
and V
IL
.
2. t
HZ
defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.
3. These parameters account for the number of clock cycles and depend on the operating frequency of the clock,
as follows the number of clock cycles = specified value of timing/ clock period
(count fractions as whole number)
(1) t
CH
is the pulse width of CLK measured from the positive edge to the negative edge referenced to V
IH
(min.).
t
CL
is the pulse width of CLK measured from the negative edge to the positive edge referenced to V
IL
(max.).
W986432DH
- 18 -
(2) A.C Latency Characteristics
CKE to clock disable (CKE Latency)
1
Cycle
DQM to output to HI-Z (Read DQM Latency)
2
DQM to output to HI-Z (Write DQM Latency)
0
Write command to input data (Write Data Latency)
0
CS
to Command input (
CS
Latency)
0
CL = 2
2
Precharge to DQ Hi-Z Lead time
CL = 3
3
CL = 2
1
Precharge to Last Valid data out
CL = 3
2
CL = 2
2
Bust Stop Command to DQ Hi-Z Lead time
CL = 3
3
CL = 2
1
Bust Stop Command to Last Valid Data out
CL = 3
2
CL = 2
BL + t
RP
Cycle + nS
Read with Auto-precharge Command to Active/Ref
Command
CL = 3
BL + t
RP
CL = 2
BL + t
RP
Write with Auto-precharge Command to Active/Ref
Command
CL = 3
BL + t
RP
W986432DH
Publication Release Date: July 30, 2002
- 19 - Revision A5
15. TIMING WAVEFORMS
Command Input Timing
t
CK
CLK
A0-A10
BS0, 1
V
IH
V
IL
t
CMH
t
CMS
t
CH
t
CL
t
T
t
T
t
CKS
t
CKH
t
CKH
t
CKS
t
CKS
t
CKH
CS
RAS
CAS
WE
CKE
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
AS
t
AH
W986432DH
- 20 -
Timing Waveforms, continued
Read Timing
Read CAS Latency
t
AC
t
LZ
t
AC
t
OH
t
HZ
t
OH
Burst Length
Read Command
CLK
CS
RAS
CAS
WE
A0-A10
BS0, 1
DQ
Valid
Data-Out
Valid
Data-Out
W986432DH
Publication Release Date: July 30, 2002
- 21 - Revision A5
Timing Waveforms, continued
Control Timing of Input Data
*DQM2,3="L"
CLK
(Word Mask)
t
CMH
t
CMS
t
CMH
t
CMS
DQM0
t
CMS
t
CMH
t
CMH
DQM1
DQ0 -DQ7
DQ16 -DQ23
DQ8-DQ15
DQ24-DQ31
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
t
DS
t
DH
Valid
Data-in
Valid
Data-in
t
DH
Valid
Data-in
t
DH
t
DS
t
DH
t
DS
Valid
Data-in
Valid
Data-in
t
DH
Valid
Data-in
t
DH
Valid
Data-in
t
DS
t
DH
t
DS
t
DH
t
DS
Valid
Data-in
Valid
Data-in
t
DH
Valid
Data-in
t
DH
Valid
Data-in
t
DS
t
DH
t
DS
t
DH
t
DH
t
DH
t
DS
t
DS
t
DS
t
DS
DQ0 -DQ7
CLK
CKE
t
CKH
t
CKS
t
CKH
t
CKS
t
DS
t
DH
t
DS
t
DH
t
DH
t
DS
t
DS
t
DH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
DQ24 -DQ31
DQ16 -DQ23
DQ8 -DQ15
(Clock Mask)
t
DS
t
DH
t
DS
t
DH
t
DH
t
DS
t
DS
t
DH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
t
DS
t
DH
t
DS
t
DH
t
DH
t
DS
t
DS
t
DH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
t
DS
t
DH
t
DS
t
DH
t
DH
t
DS
t
DS
t
DH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
t
DS
t
DS
t
DS
Valid
Data-in
Valid
Data-in
Valid
Data-in
t
CMS
W986432DH
- 22 -
Timing Waveforms, continued
Control Timing of Output Data
DQ0 -DQ7
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
t
OH
t
AC
t
OH
t
AC
t
OH
t
HZ
t
LZ
t
AC
t
OH
t
AC
OPEN
CLK
(Output Enable)
DQM0
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
DQM1
t
OH
t
AC
t
AC
t
HZ
t
AC
t
AC
Valid
Data-Out
Valid
Data-Out
t
OH
t
AC
t
OH
t
AC
t
OH
t
AC
t
OH
DQ8 -DQ15
t
AC
t
HZ
t
LZ
OPEN
DQ24 -DQ31
DQ16 -DQ23
Valid
Data-Out
Valid
Data-Out
t
OH
t
AC
t
OH
t
AC
t
OH
t
HZ
t
AC
t
OH
t
AC
t
OH
Valid
Data-Out
Valid
Data-Out
t
OH
t
OH
t
LZ
t
OH
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
t
OH
t
AC
t
OH
t
AC
t
OH
t
AC
t
OH
t
AC
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
DQ16 -DQ23
t
OH
t
AC
t
OH
t
AC
t
OH
t
AC
t
OH
t
AC
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
DQ24 -DQ31
t
CKH
t
CKS
t
CKH
t
CKS
t
OH
t
AC
t
OH
t
AC
t
OH
t
AC
t
OH
t
AC
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
DQ0 -DQ7
CKE
CLK
t
OH
t
AC
t
OH
t
AC
t
OH
t
AC
t
OH
t
AC
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
DQ8 -DQ15
(Clock Mask)
*DQM2,3="L"
W986432DH
Publication Release Date: July 30, 2002
- 23 - Revision A5
Timing Waveforms, continued
Mode Register Set Cycle
A0
A1
A2
A3
A4
A5
A6
Burst Length
Addressing Mode
CAS Latency
(Test Mode)
A8
Reserved
A0
A7
A0
A9
A0
Write Mode
A10
BS0
A0
A11
A0
BS1
"0"
"0"
A0
A3
A0
Addressing Mode
A0
0
A0
Sequential
A0
1
A0
Interleave
A0
A9
Single Write Mode
A0
0
A0
Burst read and Burst write
A0
1
A0
Burst read and single write
A0
A0
A2 A1 A0
A0
0 0 0
A0
0 0 1
A0
0 1 0
A0
0 1 1
A0
1 0 0
A0
1 0 1
A0
1 1 0
A0
1 1 1
A0
Burst Length
A0
Sequential
A0
Interleave
1
A0
1
A0
2
A0
2
A0
4
A0
4
A0
8
A0
8
A0
Reserved
A0
Reserved
A0
Full Page
A0
CAS Latency
A0
Reserved
A0
Reserved
2
A0
3
Reserved
A0
A6 A5 A4
A0
0 0 0
A0
0 1 0
A0
0 1 1
A0
1 0 0
A0
0 0 1
t
RSC
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
AS
t
AH
CLK
CS
RAS
CAS
WE
A0-A10
BS0,1
Register
set data
next
command
A0
Reserved
"0"
"0"
"0"
"0"
W986432DH
- 24 -
16. OPERATING TIMING EXAMPLE
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CS
t
RC
t
RC
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RP
t
RAS
t
RAS
t
RCD
t
RCD
t
RCD
t
RCD
t
AC
t
AC
t
AC
t
AC
t
RRD
t
RRD
t
RRD
t
RRD
Active
Read
Active
Read
Active
Active
Active
Read
Read
Precharge
Precharge
Precharge
RAa
RBb
RAc
RBd
RAe
RAa
CAw
RBb
CBx
RAc
CAy
RBd
CBz
RAe
aw0
aw1
aw2
aw3
bx0
bx1
bx2
bx3
cy0
cy1
cy2
cy3
Bank #0
Idle
Bank #1
Bank #2
Bank #3
RAS
CAS
BS1
BS0
W986432DH
Publication Release Date: July 30, 2002
- 25 - Revision A5
Operating Timing Example, continued
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
CLK
CKE
DQM
A0-A9
A10
BS1
WE
CAS
RAS
CS
BS0
t
RC
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RAS
t
RP
t
RAS
t
RCD
t
RCD
t
RCD
t
AC
t
AC
t
AC
t
AC
t
RRD
t
RRD
t
RRD
t
RRD
Active
Read
Active
Read
Active
Active
Active
Read
Read
t
RC
RAa
RAc
RBd
RAe
DQ
aw0
aw1
aw2
aw3
bx0
bx1
bx2
bx3
cy0
cy1
cy2
cy3
dz0
* AP is the internal precharge start timing
Bank #0
Idle
Bank #1
Bank #2
Bank #3
AP*
AP*
RAa
CAw
RBb
CBx
RAc
CAy
RBd
RAe
CBz
RBb
AP*
t
RCD
W986432DH
- 26 -
Operating Timing Example, continued
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RAS
t
RCD
t
RCD
t
RCD
t
RRD
t
RRD
RAa
RAa
CAx
RBb
RBb
CBy
RAc
RAc
CAz
ax0
ax1
ax2
ax3
ax4
ax5
ax6
by0
by1
by4
by5
by6
by7
CZ0
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9
A10
BS1
WE
CAS
RAS
CS
Active
Read
Precharge
Active
Read
Precharge
Active
t
AC
t
AC
Read
Precharge
t
AC
Bank #0
Idle
Bank #1
Bank #2
Bank #3
BS0
W986432DH
Publication Release Date: July 30, 2002
- 27 - Revision A5
Operating Timing Example, continued
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge)
A0-A9
Bank #0
Idle
Bank #1
Bank #2
Bank #3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
t
RC
t
RAS
t
RP
t
RAS
t
RCD
t
RCD
t
RCD
t
RRD
t
RRD
ax0
ax1
ax2
ax3
ax4
ax5
ax6
ax7
by0
by1
by4
by5
by6
CZ0
RAa
RAa
CAx
RBb
RBb
CBy
(CLK = 100 MHz)
RAc
RAc
CAz
* AP is the internal precharge start timing
Active
Read
Active
Active
Read
t
CAC
t
CAC
t
CAC
CLK
DQ
CKE
DQM
A10
WE
CAS
RAS
CS
Read
AP*
AP*
BS1
BS0
W986432DH
- 28 -
Operating Timing Example, continued
Interleaved Bank Write (Burst Length = 8)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
t
RC
t
RAS
t
RP
t
RAS
t
RCD
t
RCD
t
RCD
t
RRD
t
RRD
RAa
RAa
CAx
RBb
RBb
CBy
RAc
RAc
CAz
ax0
ax1
by4
by5
by6
by7
CZ0
CZ1
CZ2
(CLK = 100 MHz)
Write
Precharge
Active
Active
Write
Precharge
Active
Write
CLK
DQ
CKE
DQM
A0-A9
A10
BS1
WE
CAS
RAS
CS
Idle
Bank #0
Bank #1
Bank #2
Bank #3
BS0
ax4
ax5
ax6
ax7
by0
by1
by2
by3
W986432DH
Publication Release Date: July 30, 2002
- 29 - Revision A5
Operating Timing Example, continued
Interleaved Bank Write (Burst Length = 8, Autoprecharge)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
t
RC
t
RAS
t
RP
t
RAS
t
RCD
t
RCD
t
RCD
t
RRD
t
RRD
RAa
RAa
CAx
RBb
RBb
CBy
RAb
RAc
ax0
ax1
ax4
ax5
ax6
ax7
by0
by1
by2
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
CAz
(CLK = 100 MHz)
* AP is the internal precharge start timing
CLK
DQ
CKE
DQM
A0-A9
A10
BS1
WE
CAS
RAS
CS
Active
Write
Write
Active
Bank #0
Idle
Bank #1
Bank #2
Bank #3
AP*
Active
Write
AP*
BS0
W986432DH
- 30 -
Operating Timing Example, continued
Page Mode Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
t
CCD
t
CCD
t
CCD
t
RAS
t
RAS
t
RCD
t
RCD
t
RRD
RAa
RAa
CAI
RBb
RBb
CBx
CAy
CAm
CBz
a0
a1
a2
a3
bx0
bx1
Ay0
Ay1
Ay2
am0
am1
am2
bz0
bz1
bz2
bz3
(CLK = 100 MHz)
* AP is the internal precharge start timing
CLK
DQ
CKE
DQM
A0-A9
A10
BS1
WE
CAS
RAS
CS
Active
Read
Active
Read
Read
Read
Read
Precharge
t
AC
t
AC
t
AC
t
AC
t
AC
Bank #0
Idle
Bank #1
Bank #2
Bank #3
AP*
BS0
W986432DH
Publication Release Date: July 30, 2002
- 31 - Revision A5
Operating Timing Example, continued
Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
t
RAS
t
RCD
t
WR
RAa
RAa
CAx
CAy
ax0
ax1
ax2
ax3
ax4
ax5
ay1
ay0
ay2
ay4
ay3
Q Q
Q
Q
Q
Q
D
D
D
D
D
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9
A10
BS1
WE
CAS
RAS
CS
Active
Read
Write
Precharge
t
AC
Bank #0
Idle
Bank #1
Bank #2
Bank #3
BS0
W986432DH
- 32 -
Operating Timing Example, continued
Autoprecharge Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
BS1
t
RC
t
RAS
t
RP
t
RAS
t
RCD
t
RCD
t
AC
t
AC
Active
Read
AP*
Active
Read
AP*
RAa
RAb
RAa
CAw
RAb
CAx
aw0
aw1
aw2
aw3
* AP is the internal precharge start timing
Bank #0
Idle
Bank #1
Bank #2
Bank #3
BS0
bx0
bx2
bx1
bx3
W986432DH
Publication Release Date: July 30, 2002
- 33 - Revision A5
Operating Timing Example, continued
Autoprecharge Write (Burst Length = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
BS1
t
RC
t
RC
t
RP
t
RAS
t
RP
RAa
t
RCD
t
RCD
RAb
RAc
RAa
RAb
CAx
RAc
bx0
bx1
bx2
bx3
Active
Active
Write
AP*
Active
Write
AP*
* AP is the internal precharge start timing
Bank #0
Idle
Bank #1
Bank #2
Bank #3
t
RAS
BS0
CAw
aw0
aw1
aw2
aw3
W986432DH
- 34 -
Operating Timing Example, continued
Autorefresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
All Banks
Prechage
Auto
Refresh
Auto Refresh (Arbitrary Cycle)
t
RC
t
RP
t
RC
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
BS0,1
W986432DH
Publication Release Date: July 30, 2002
- 35 - Revision A5
Operating Timing Example, continued
Self-refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9
A10
BS0,1
WE
CAS
RAS
CS
t
CKS
t
SB
t
CKS
t
CKS
All Banks
Precharge
Self Refresh
Entry
Arbitrary Cycle
t
RP
Self Refresh Cycle
t
RC
No Operation Cycle
W986432DH
- 36 -
Operating Timing Example, continued
Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
(CLK = 100 MHz)
Q
Q
Q
Q
D
D
D
Q
Q
Q
Q
Read
Read
Single Write
Active
Bank #0
Idle
Bank #1
Bank #2
Bank #3
CS
RAS
CAS
WE
BS1
A10
A0-A9
DQM
CKE
DQ
t
RCD
RBa
RBa
CBv
CBw
CBx
CBy
CBz
av0
av1
av2
av3
aw0
ax0
ay0
az0
az1
az2
az3
t
AC
t
AC
BS0
W986432DH
Publication Release Date: July 30, 2002
- 37 - Revision A5
Operating Timing Example, continued
Power-down Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
RAa
CAa
RAa
CAx
RAa
RAa
ax0
ax1
ax2
ax3
t
SB
t
CKS
t
CKS
t
CKS
t
SB
t
CKS
Active Standby
Power Down mode
Precharge Standby
Power Down mode
Active
NOP
Precharge
NOPActive
Note: The PowerDown Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
CLK
DQ
CKE
DQM
A0-A9
A10
BS
WE
CAS
RAS
CS
Read
W986432DH
- 38 -
Operating Timing Example, continued
Auto-precharge Timing (Write Cycle)
D0
Write
Act
AP
0
11
10
9
8
7
6
5
4
3
2
1
D0
D0
D0
D0
AP
Act
D1
AP
Act
D1
D1
D2
D2
D3
D3
D4
D5
D6
D7
AP
Act
AP
Act
AP
Act
D1
D0
AP
Act
D1
D2
D3
AP
Act
D0
D1
D2
D3
D4
D5
D6
D7
Write
Write
Write
Write
Write
Write
Write
D0
(1) CAS
Latency = 2
(2) CAS
Latency = 3
Write
Act
AP
When the Auto precharge command is asserted, the period from Bank Activate
command to the start of internal precgarging must be at least tRAS (min.)
represents the Write with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
Note:
t
RP
t
WR
t
RP
t
WR
t
RP
t
WR
t
RP
t
WR
t
RP
t
WR
t
RP
t
WR
t
RP
t
WR
t
RP
t
WR
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
W986432DH
Publication Release Date: July 30, 2002
- 39 - Revision A5
Operating Timing Example, continued
Auto-precharge Timing (Read Cycle)
Read
AP
0
11
10
9
8
7
6
5
4
3
2
1
Q0
Q0
Read
AP
Act
Q1
Read
AP
Act
Q1
Q2
AP
Act
Read
Act
Q0
Q3
(1) CAS
Latency=2
Read
Act
AP
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least t
RAS
(min).
represents the Read with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
Note:
t
RP
t
RP
t
RP
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
t
RP
Q0
Read
AP
Act
Q0
Read
AP
Act
Q1
Q0
Read
AP
Act
Q1
Q2
Q3
Read
AP
Act
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
(2) CAS
Latency=3
t
RP
t
RP
t
RP
t
RP
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
W986432DH
- 40 -
Operating Timing Example, continued
Timing Chart of Read to Write Cycle
Note: The Output data must be masked by DQM to avoid I/O conflict.
Read
Write
11
10
9
8
7
6
5
4
3
2
1
Read
Read
Read
Write
Write
D0
D1
D2
D3
Write
DQ
DQ
( a ) Command
0
DQ
DQ
DQM
( b ) Command
DQM
( b ) Command
DQM
DQM
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
(1) CAS Latency=2
( a ) Command
(2) CAS Latency=3
In the case of Burst Length = 4
W986432DH
Publication Release Date: July 30, 2002
- 41 - Revision A5
Operating Timing Example, continued
Timing Chart of Write to Read Cycle
0
11
10
9
8
7
6
5
4
3
2
1
In the case of Burst Length = 4
Q0
Read
Q1
Q2
Q3
Read
Write
Write
D0
D1
DQ
DQ
( a ) Command
( b ) Command
DQM
DQM
(2) CAS Latency = 3
Q0
Q1
Q2
Q3
D0
Read
Write
Read
Write
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
( a ) Command
DQ
DQ
DQM
( b ) Command
DQM
(1) CAS Latency = 2
D0
D0
D1
W986432DH
- 42 -
Operating Timing Example, continued
Timing Chart of Burst Stop Cycle (Burst Stop Command)
Read
BST
0
11
10
9
8
7
6
5
4
3
2
1
DQ
DQ
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Read
BST
( a ) CAS latency =2
Command
( b ) CAS latency = 3
Command
(3) Read cycle
Q4
Q4
DQ
D0
D1
D2
D3
Write
BST
Command
(2) Write cycle
D4
Note:
represents the Burst stop command
BST
W986432DH
Publication Release Date: July 30, 2002
- 43 - Revision A5
Operating Timing Example, continued
Timing Chart of Burst Stop Cycle (Precharge Command)
In the case of Burst Lenght = 8
Note: represents the Precharge command
PRCG
Read
PRCG
0
11
10
9
8
7
6
5
4
3
2
1
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Read
PRCG
Q4
Q4
( a )CAS latency =2
( b )CAS latency = 3
DQ
DQ
(1) Read cycle
(2) Write cycle
Commad
Commad
Write
PRCG
D0
D1
D2
D3
D0
D1
D2
D3
Write
PRCG
D4
D4
( b ) CAS latency = 3
DQ
( a ) CAS latency =2
DQM
DQM
DQ
t
WR
t
WR
Commad
Commad
W986432DH
- 44 -
Operating Timing Example, continued
CKE/DQM Input Timing (Write Cycle)
7
6
5
4
3
2
1
CKE MASK
( 1 )
D1
D6
D5
D3
D2
CLK cycle No.
External
Internal
CKE
DQM
DQ
7
6
5
4
3
2
1
( 2 )
D1
D6
D5
D3
D2
CLK cycle No.
External
Internal
CKE
DQM
DQ
7
6
5
4
3
2
1
( 3 )
D1
D6
D5
D4
D3
D2
CLK cycle No.
External
CKE
DQM
DQ
DQM MASK
DQM MASK
CKE MASK
CKE MASK
Internal
CLK
CLK
CLK
W986432DH
Publication Release Date: July 30, 2002
- 45 - Revision A5
Operating Timing Example, continued
CKE/DQM Input Timing (Read Cycle)
7
6
5
4
3
2
1
( 1 )
Q1
Q6
Q4
Q3
Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ
Open
Open
7
6
5
4
3
2
1
Q1
Q6
Q3
Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ
Open
( 2 )
7
6
5
4
3
2
1
Q1
Q6
Q3
Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ
Q5
Q4
( 3 )
Q4
CLK
CLK
CLK
W986432DH
- 46 -
Operating Timing Example, continued
Self Refresh/Power Down Mode Exit Timing
Asynchronous Control
Input Buffer turn on time (Power down mode exit time) is specified by t
CKS
(min.) + t
CK
(min.)
Command
NOP
CLK
CKE
Command
A ) t
CK
< t
CKS
(min.) + t
CK
(min.)
Input Buffer Enable
Command
CLK
CKE
Command
B) t
CK
>= t
CKS
(min.) + t
CK
(min.)
Input Buffer Enable
Note:
Command
NOP
All Input Buffer (Include CLK Buffer) are turned off in the Power Down mode
and Self Refresh mode
Represents the No-Operation command
Represents one command
t
CK
t
CK
t
CKS
(min)+t
CK
(min)
t
CKS
(min)+t
CK
(min)
W986432DH
Publication Release Date: July 30, 2002
- 47 - Revision A5
17. PACKAGE DIMENSION
86L TSOP (II)-400 mil
SEATING PLANE
E
D
A2
A1
A
b
ZD
1
43
86
44
e
H
E
Y
L
C
L1
q
ZD
0.61
0.024
0.002
0.007
MAX.
MIN.
NOM.
A2
b
A
A1
0.17
1.00
0.05
0.27
1.20
0.15
SYM.
DIMENSION
(MM)
MAX.
MIN.
NOM.
e
0.50
0.020
0.016
L
0.40
0.50
0.60
0.020
0.024
0.396
E
10.06
10.16
10.26
0.400
0.404
0.871
D
22.22
22.12
22.62
0.875
0.905
0.039
0.011
0.047
0.006
DIMENSION
(INCH)
L1
0.80
0.032
c
0.12
0.005
0.455
11.76
11.56
11.96
0.463
0.471
H
E
Y
0.10
0.004
Controlling Dimension: Millimeters
0.21
0.008
W986432DH
- 48 -
18. VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A3
Auguest 2001
-
Preliminary datasheet
A4
Apr. 11, 2002
12
Change CI/O capacitance value
A5
July 30, 2002
5
Change CLK pin
number
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
Winbond Electronics Corporation America
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
Winbond Electronics (H.K.) Ltd.
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
FAX: 852-27552064
Unit 9-15, 22F, Millennium City,
TEL: 852-27513100
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Winbond Electronics (Shanghai) Ltd.
200336 China
FAX: 86-21-62365998
27F, 2299 Yan An W. Rd. Shanghai,
TEL: 86-21-62365999
Winbond Electronics Corporation Japan
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
FAX: 81-45-4781800
7F Daini-ueno BLDG, 3-7-18
TEL: 81-45-4781881
9F, No.480, Rueiguang Rd.,
Neihu Chiu, Taipei, 114,
Taiwan, R.O.C.
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