Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A
04/12/06

IS24C01B IS24C02B

ISSI

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.

1K-bit/2K-bit
2-WIRE SERIAL CMOS EEPROM

APRIL 2006

DESCRIPTION

The IS24C01B and IS24C02B are electrically
erasable PROM devices that use the standard 2-
wire interface for communications. The IS24C01B
and IS24C02B contain a memory array of 1K-bits
(128 x 8) and 2K-bits (256 x 8), respectively. Each
device is organized into 8 byte pages for page
write mode.

This EEPROM operates in a wide voltage range of
1.8V to 5.5V to be compatible with most application
voltages. ISSI designed this device family to be a
practical, low-power 2-wire EEPROM solution.
The devices are available in 8-pin PDIP, 8-pin
SOIC, 8-pad DFN, and 8-pin TSSOP packages.

The IS24C01B/02B maintains compatibility with
the popular 2-wire bus protocol, so it is easy to
use in applications implementing this bus type.
The simple bus consists of the Serial Clock wire
(SCL) and the Serial Data wire (SDA). Using the
bus, a Master device such as a microcontroller is
usually connected to one or more Slave devices
such as this device. The bit stream over the SDA
line includes a series of bytes, which identifies a
particular Slave device, an instruction, an address
within that Slave device, and a series of data, if
appropriate. The IS24C01B/02B has a
Write Protect pin (WP) to allow blocking of any
write instruction transmitted over the bus.

FEATURES

· Two-Wire Serial Interface, I

compatible

Bi-directional data transfer protocol

· Wide Voltage Operation

Vcc = 1.8V to 5.5V

· 400 KHz (2.5V) and 1 MHz (5.0V) compatibility

· Low Power CMOS Technology

Standby Current less than 6 µA (5.0V)

Read Current less than 2 mA (5.0V)

Write Current less than 3 mA (5.0V)

· Hardware Data Protection

Write Protect Pin

· Sequential Read Feature

· Filtered Inputs for Noise Suppression

· Self time write cycle with auto clear

5 ms max. @ 2.5V

· Organization:

IS24C01B 128x8 (128 bytes)
IS24C02B 256x8 (256 bytes)

· 8 Byte Page Write Buffer

· High Reliability

Endurance: 1,000,000 Cycles

Data Retention: 100 Years

· Industrial and Automotive temperature ranges

· 8-pin PDIP, 8-pin SOIC, 8-pad DFN, and 8-pin

TSSOP packages

· Lead-free available

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A
04/12/06

IS24C01B

IS24C02B

ISSI

SCL
This input clock pin is used to synchronize the data transfer
to and from the device.

SDA
The SDA is a Bi-directional pin used to transfer addresses and
data into and out of the device. The SDA pin is an open drain
output and can be wire-Or'ed with other open drain or open
collector outputs. The SDA bus

requires a pullup resistor to

Vcc.

PIN CONFIGURATION

8-Pin DIP, SOIC, TSSOP

GND

VCC

SCL

SDA

PIN DESCRIPTIONS

A0-A2

Address Inputs

SDA

Serial Address/Data I/O

SCL

Serial Clock Input

Write Protect Input

Vcc

Power Supply

GND

Ground

A0, A1, A2
The A0, A1 and A2 are the device address inputs. The
IS24C01B/02B uses the A0, A1, and A2 for hardware addressing
and a total of 8 devices may be used on a single bus system.
When the A0, A1, or A2 inputs are left floating, the input
internally defaults to zero.

WP
WP is the Write Protect pin. If the WP pin is tied to V

on the

EEPROM, the entire array becomes Write Protected (Read
only). When WP is tied to GND or left floating normal read/
write operations are allowed to the device.

8-pad DFN

GND

VCC

SCL

SDA

(Top View)

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A

04/12/06

IS24C01B

IS24C02B

ISSI

DEVICE OPERATION

IS24C01B/02B features serial communication and supports
a bi-directional 2-wire bus transmission protocol called I

2-WIRE BUS

The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device that
sends data onto the SDA bus as a transmitter, and the
receiving devices as receivers. The bus is controlled by
Master device that generates the SCL, controls the bus
access, and generates the Stop and Start conditions. The
IS24C01B/02B is the Slave device on the bus.

The Bus Protocol:

Data transfer may be initiated only when the bus is not busy

During a data transfer, the SDA line must remain stable

whenever the SCL line is high. Any changes in the SDA
line while the SCL line is high will be interpreted as a Start
or Stop condition.

The state of the SDA line represents valid data after a Start
condition. The SDA line must be stable for the duration of the
High period of the clock signal. The data on the SDA line may
be changed during the Low period of the clock signal. There
is one clock pulse per bit of data. Each data transfer is
initiated with a Start condition and terminated with a Stop
condition.

Start Condition

The Start condition precedes all commands to the device and
is defined as a High to Low transition of SDA when SCL is High.
The EEPROM monitors the SDA and SCL lines and will not
respond until the Start condition is met.

Stop Condition

The Stop condition is defined as a Low to High transition
of SDA when SCL is High. All operations must end with
a Stop condition.

Acknowledge (ACK)

After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.

Reset

The

IS24C01B/02B

contains a reset function in case

the 2-wire bus transmission is accidentally interrupted
(eg. a power loss), or needs to be terminated mid-
stream. The reset is caused when the Master device
creates a Start condition. To do this, it may be
necessary for the Master device to monitor the SDA
line while cycling the SCL up to nine times. (For each
clock signal transition to High, the Master checks for a
High level on SDA.)

Standby Mode

Power consumption is reduced in standby mode. The
IS24C01B/02B will enter standby mode: a) At Power-up,
and remain in it until SCL or SDA toggles; b) Following
the Stop signal if a no write operation is initiated; or c)
Following any internal write operation.

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A
04/12/06

IS24C01B

IS24C02B

ISSI

Page Write

The IS24C01B/02B is capable of 8-byte Page-Write
operation. A Page-Write is initiated in the same manner as
a Byte Write, but instead of terminating the internal Write
cycle after the first data word is transferred, the Master
device can transmit up to 7 more bytes. After the receipt of
each data word, the EEPROM responds immediately with an
ACK on SDA line, and the three lower order data word
address bits are internally incremented by one, while the
higher order bits of the data word address remain constant.
If a byte address is incremented from the last byte of a
page, it returns to the first byte of that page. If the Master
device should transmit more than 8 bytes prior to issuing the
Stop condition, the address counter will "roll over," and the
previously written data will be overwritten. Once all 8 bytes
are received and the Stop condition has been sent by the
Master, the internal programming cycle begins. At this point,
all received data is written to the IS24C01B/02B in a single
Write cycle. All inputs are disabled until completion of the
internal Write cycle.

Acknowledge (ACK) Polling

The disabling of the inputs can be used to take advantage of
the typical Write cycle time. Once the Stop condition is
issued to indicate the end of the host's Write operation, the
IS24C01B/02B initiates the internal Write cycle. ACK polling
can be initiated immediately. This involves issuing the
Start condition followed by the Slave address for a Write
operation. If the EEPROM is still busy with the Write
operation, no ACK will be returned. If the IS24C01B/02B
has completed the Write operation, an ACK will be returned
and the host can then proceed with the next Read or Write
operation.

WRITE OPERATION

Byte Write

In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/

set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends the byte address that is to be
written into the address pointer of the IS24C01B/02B. After
receiving another ACK from the Slave, the Master device
transmits the data byte to be written into the address
memory location. The IS24C01B/02B acknowledges once
more and the Master generates the Stop condition, at
which time the device begins its internal programming
cycle. While this internal cycle is in progress, the device
will not respond to any request from the Master device.

DEVICE ADDRESSING

The Master begins a transmission by sending a Start
condition. The Master then sends the address of the
particular Slave devices it is requesting. The Slave device
(Fig. 5) address is 8 bits.

The four most significant bits of the Slave device address
are fixed as 1010 for the IS24C01B/02B.

The next three bits of the Slave address are specific for
each of the EEPROM. The bit values enable access to
multiple memory blocks or multiple devices.

The IS24C01B/02B uses the three bits A0, A1, and A2 in
a comparison with the hard-wired input values on the A0,
A1, and A2 pins. Up to eight units may share the 2-wire
bus.

The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a Write
operation is selected.

After the Master transmits the Start condition and Slave
address byte (Fig. 5), the appropriate 2-wire Slave
(eg.IS24C02B) will respond with ACK on the SDA line. The
Slave will pull down the SDA on the ninth clock cycle,
signaling that it received the eight bits of data. The selected
EEPROM then prepares for a Read or Write operation by
monitoring the bus.

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