Integrated Silicon Solution, Inc. -- 1-800-379-4774

Advanced Information

Rev. 00E

06/13/06

IS25C128
IS25C256

ISSI

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.

128K-bit/ 256K-bit SPI SERIAL
ELECTRICALLY ERASABLE PROM

FEATURES

· Serial Peripheral Interface (SPI) Compatible

-- Supports SPI Modes 0 (0,0) and 3 (1,1)

· Low power CMOS

-- Active current less than 3.0 mA (2.5V)
-- Standby current less than 20 µA (2.5V)

· Low-voltage Operation

-- Vcc = 1.8V to 5.5V

· Block Write Protection

-- Protect 1/4, 1/2, or Entire Array

· 64 byte page write mode

-- Partial page writes allowed

· 2.1 MHz Clock Rate (5V)
· Self timed write cycles

-- 5ms max @ 2.5V

· High-reliability

-- Endurance: 1,000,000 cycles per byte
-- Data retention: 100 years

· 8-pin JEDEC SOIC, 8-pin EIAJ SOIC, and 8-pin PDIP

packages available

· Industrial and Automotive temperature ranges
· Lead-free available

Advanced Information

JULY 2006

DESCRIPTION

The IS25C128 and IS25C256 are electrically erasable
PROM devices that use the Serial Peripheral Interface
(SPI) for communications. The IS25C128 is 128Kbit
(16K x 8) and the IS25C256 is 256Kbit (32K x 8). The
IS25C128/256 EEPROMs are offered in a wide
operating voltage range of 1.8V to 5.5V for compatibility
with most application voltages. ISSI designed the
IS25C128/256 to be an efficient SPI EEPROM solution.
The devices are packaged in 8-pin JEDEC SOIC, 8-pin
EIAJ SOIC, and 8-pin PDIP.

The functional features of the IS25C128/256 allow them
to be among the most advanced serial non-volatile
memories available. Each device has a Chip-Select
(

) pin, and a 3-wire interface of Serial Data In (SI),

Serial Data Out (SO), and Serial Clock (SCK). While
the 3-wire interface of the IS25C128/256 provides for
high-speed access, a

HOLD

pin allows the memories to

ignore the interface in a suspended state; later the

HOLD

pin re-activates communication without re-

initializing the serial sequence. A Status Register
facilitates a flexible write protection mechanism, and a
device-ready bit (

RDY

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Advanced Information

Rev. 00E

06/13/06

IS25C128
IS25C256

ISSI

Write Protect (

): The purpose of this input signal is

to initiate Hardware Write Protection mode. This mode
prevents the Block Protection bits and the WPEN bit in
the Status Register from being altered. To cause
Hardware Write Protection,

must be Low at the same

time WPEN is 1.

may be hardwired to Vcc or GND.

HOLD (

HOLD

): This input signal is used to suspend the

device in the middle of a serial sequence and temporarily
ignore further communication on the bus (SI, SO, SCK).
Together with Chip Select, the

HOLD

signal allows

multiple slaves to share the bus.

The

HOLD

signal

transitions must occur only when SCK is Low, and be
held stable during SCK transitions. (See Figure 8 for
Hold timing) To disable this feature,

HOLD

may be

hardwired to Vcc.

PIN DESCRIPTIONS

Chip Select

SCK

Serial Data Clock

Serial Data Input

Serial Data Output

GND

Ground

Power

Write Protect

HOLD

Suspends Serial Input

PIN DESCRIPTIONS

Serial Clock (SCK): This timing signal provides syn-
chronization between the microcontroller and IS25C128/
256. Op-Codes, byte addresses, and data are latched
on SI with a rising edge of the SCK. Data on SO is
refreshed on the falling edge of SCK for SPI modes (0,0)
and (1,1).

Serial Data Input (SI): This is the input pin for all data
that the IS25C128/256 is required to receive.

Serial Data Output (SO): This is the output pin for all
data transmitted from the IS25C128/256.

PIN CONFIGURATION

8-Pin DIP and SOIC

Chip Select (

): The

pin activates the device.

Upon power-up,

should follow Vcc. When the device

is to be enabled for instruction input, the signal requires
a High-to-Low transition. While

is stable Low, the

master and slave will communicate via SCK, SI, and SO
signals. Upon completion of communication,

must

be driven High. At this moment, the slave device may
start its internal write cycle. When

is high, the

device enters a power-saving standby mode, unless an
internal write operation is underway. During this mode,
the SO pin becomes high impedance.

GND

VCC
HOLD
SCK

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Advanced Information

Rev. 00E

06/13/06

IS25C128
IS25C256

ISSI

SERIAL INTERFACE DESCRIPTION

MASTER: The device that provides a clock signal.

SLAVE: The IS25C128/256 is a slave because the clock
signal is an input.

TRANSMITTER/RECEIVER: The IS25C128/256 has both
data input (SI) and data output (SO).

MSB: The most significant bit. It is always the first bit
transmitted or received.

OP-CODE: The first byte transmitted to the slave follow-
ing CS transition to LOW. If the OP-CODE is a valid
member of the IS25C128/256 instruction set (Table 3),
then it is decoded appropriately. If the OP-CODE is not
valid, and the SO pin remains in high impedance.

BLOCK DIAGRAM

STATUS

16K x 8/32K x 8

MEMORY ARRAY

HOLD

CLOCK

OUTPUT

BUFFER

SCK

DATA

MODE

DECODE

LOGIC

GND

VCC

ADDRESS

DECODER

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Advanced Information

Rev. 00E

06/13/06

IS25C128
IS25C256

ISSI

STATUS REGISTER

Table 1. Status Register Format

Bit 7

Bit 6 Bit 5 Bit 4

Bit 3 Bit 2

Bit1 Bit 0

WPEN

BP1

BP0

WEN

RDY

The status register contains 8-bits for write protection
control and write status. (See Table 1). It is the only
region of memory other than the main array that is
accessible by the user.

The Status Register is Read-Only if either: a) Hardware
Write Protection is enabled or b) WEN is set to 0. If
neither is true, it can be modified by a valid instruction.

Ready (

RDY

), Bit 0: When

RDY

= 1, it indicates that

the device is busy with a write cycle.

RDY

= 0 indi-

cates that the device is ready for an instruction. If

RDY

= 1, the only command that will be handled by the
device is Read Status Register.

Don't Care, Bits 4-6: Each of these bits can receive
either 0 or 1, but values will not be retained. When
these bits are read from the register, they are always 0.

Write Protect Enable (WPEN), Bit 7: This bit can be
used in conjunction with

pin to enable Hardware

Write Protection, which causes the Status Register to
be read-only. The memory array is not protected by this
mode. Hardware Write Protection requires that

= 0

and WPEN = 1; it is disabled otherwise. Note: WPEN
cannot be changed from 1 to 0 if the

pin is already

set to Low. (See Table 4 for data protection relationship)

Notes:

1. X

= Don't care bit.

During internal write cycles, bits 0 to 7 are temporarily 1's.

Block Protect (BP1, BP0), Bits 2-3: Together, these
bits represent one of four block protection configurations
implemented for the memory array. (See Table 2 for
details.)
BP0 and BP1 are non-volatile cells similar to regular
array cells, and factory programmed to 0. The block of
memory defined by these bits is always protected,
regardless of the setting of WPEN,

, or WEN.

Table 2. Block Protection

Status

Register

Bits

Array Addresses Protected

Level

BP1

BP0

IS25C128

IS25C256

None

1(1/4)

3000h

6000h

-3FFFh

-7FFFh

2(1/2)

2000h

4000h

-3FFFh

-7FFFh

3(All)

0000h

-3FFFh

-7FFFh

Write Enable (WEN), Bit 1: This bit represents the
status of device write protection. If WEN = 0, the Status
Register and the entire array is protected from modifica-
tion, regardless of the setting of WPEN,

pin, or block

protection. The only way to set WEN to 1 is via the
Write Enable command (WREN). WEN is reset to 0
upon power-up.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Advanced Information

Rev. 00E

06/13/06

IS25C128
IS25C256

ISSI

WRITE ENABLE (WREN)
When Vcc is initially applied, the device powers up with
both status register and entire array in a write-disabled
state. Upon completion of Write Disable (WRDI), Write
Status Register (WRSR), or Write Data to Array
(WRITE), the device resets the WEN bit in the Status
Register to 0. Prior to any data modification, a WREN
instruction is necessary to set WEN to 1. (See Figure 2
for timing).

WRITE DISABLE (WRDI)
The device can be completely protected from modifica-
tion by resetting WEN to 0 through the WRDI instruc-
tion. (See Figure 3 for timing).

READ STATUS REGISTER (RDSR)

The Read Status instruction tells the user the status of
Write Protect Enable, the Block Protection setting (see
Table 2), the Write Enable state, and the

RDY

status.

RDSR is the only instruction accepted when a write
cycle is underway. It is recommended that the status of
Write Enable and

RDY

be checked, especially prior to

an attempted modification of data. The 8 bits of the
Status Register can be repeatedly output on SO after
the initial Op-code. (See Figure 4 for timing).

Table 3. Instruction Set

Name

Op-code

Operation

Address

Data(SI)

Data (SO)

WREN

0000 X110

Set Write Enable Latch

WRDI

0000 X100

Reset Write Enable Latch

RDSR

0000 X101

Read Status Register

D7-D0,...

WRSR

0000 X001

Write Status Register

D7-D0

READ

0000 X011

Read Data from Array

A15-A0

D7-D0,...

WRITE

0000 X010

Write Data to Array

A15-A0

D7-D0,...

DEVICE OPERATION

he operations of the IS25C128/256 are controlled by a set of instructions that are clocked-in serially SI pin. (See

Table 3). To begin an instruction, the chip select (

)

should be dropped Low. Subsequently, each Low-to-High

transition of the clock (SK) will latch a stable value on the SI pin. After the 8-bit op-code, it may be appropriate to
continue to input an address or data to SI, or to output data from SO. During data output, values appear on the falling
edge of SK. All bits are transferred with MSB first. Upon the last bit of communication, but prior to any following Low-
to-High transition of SK,

should be raised High to end the transaction. The device then would enter Standby Mode

if no internal programming were underway.

Notes:

1. X = Don't care bit. For consistency, it is best to use "0".

2. Some address bits are don't care. See Table 5.
3. If the bits clocked-in for an op-code are invalid, SO remains high impedance, and upon CS going High there is no affect. A

valid op-code with an invalid number of bits clocked-in for address or data will cause an attempt to modify the array or

Status Register to be ignored.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Advanced Information

Rev. 00E

06/13/06

IS25C128
IS25C256

ISSI

Table 5. Address Key

Name

IS25C128

IS25C256

13-

14-

Don't

15-

Care Bits

WRITE STATUS REGISTER (WRSR)

This instruction lets the user choose a Block Protection
setting, and set or reset the WPEN bit. The values of
the other data bits incorporated into WRSR can be 0 or
1, and are not stored in the Status Register. WRSR will
be ignored unless both the following are true: a) WEN =
1, due to a prior WREN instruction; and b) Hardware
Write Protection is not enabled. (See Table 4 for de-
tails). Except for the

RDY

status, the values in the

Status Register remain unchanged until the moment
when the write cycle is complete and the register is
updated. Note: WPEN can be changed from 1 to 0 only
if

is already set High. Once completed, WEN is

reset for complete chip write protection. (See Figure 5
for timing).

READ DATA (READ)
This instruction begins with the op-code and the 16-bit
address, and causes the selected data byte to be
shifted out on SO. Following this first data byte, addi-
tional sequential bytes are output. If the data byte in the
highest address is output, the address rolls-over to the
lowest address in the array, and the output could loop
indefinitely. At any time, a rising

signal completes

the operation. (See Figure 6 for timing).

WRITE DATA (WRITE)
The WRITE instruction begins with the op-code, the 16-
bit address of the first byte to be modified, and the first
data byte. Additional data bytes may be written sequen-
tially to the array after the first byte. Each WRITE
instruction can affect the contents of a 64 byte page, but
no more. The page begins at address XXXXXXXX
XX000000, and ends with XXXXXXXX XX111111. If the last
byte of the page is input, the address rolls over to the
beginning of the same page. More than 64 data bytes
can be input during the same instruction, but upon a
completed write cycle, a page would only contain the
last 64 bytes.

The region of the array defined within Block Protection
cannot be modified as long as that block configuration is
selected. The region of the array outside the Block
Protection can only be modified if Write Enable (WEN) is
set to 1. Therefore, it may be necessary that a WREN
instruction occur prior to WRITE. Hardware Write
Protection has no affect on the memory array. Once
Write is completed, WEN is reset for complete chip
write protection. (See Figure 7 for timing).

Table 4. Write Protection

WPEN

Hardware Write

WEN

Inside Block

Outside Block

Status Register

Protection

(WPEN, BP1, BP0)

Not Enabled

Read-only

Not Enabled

Read-only

Unprotected

Enabled

Read-only

Enabled

Read-only

Unprotected

Read-only

Not Enabled

Read-only

Not Enabled

Read-only

Unprotected

Note:

= Don't care bit.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Advanced Information

Rev. 00E

06/13/06

IS25C128
IS25C256

ISSI

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

Supply Voltage

-0.5 to + 6.5

Voltage on Any Pin

0.5 to Vcc + 0.5

BIAS

Temperature Under Bias

55 to +125

°C

STG

Storage Temperature

65 to +150

°C

OUT

Output Current

Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-

nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions outside those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

OPERATING RANGE (IS25C256-2 and IS25C128-2)

Range

Ambient Temperature

Industrial

40°C to +85°C

1.8V to 5.5V

Note:
1. ISSI offers Industrial grade for Commercial applications (0

C to +70

C).

CAPACITANCE

(1,2)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

Notes:
1. Tested initially and after any design or process changes that may affect these parameters and not 100%

tested.

2. Test conditions: T

= 25°C, f = 1 MHz, Vcc = 5.0V.

OPERATING RANGE (IS25C256-3 and IS25C128-3)

Range

Ambient Temperature

Automotive

40°C to +125°C

2.5V to 5.5V

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Advanced Information

Rev. 00E

06/13/06

IS25C128
IS25C256

ISSI

DC ELECTRICAL CHARACTERISTICS

= 40°C to +85°C for Industrial, T

= 40°C to +125°C for Automotive.

Symbol Parameter

Test Conditions

Min.

Max.

Unit

Output LOW Voltage

= 5V, I

= 3 mA

0.4

Output LOW Voltage

= 2.5V, I

= 1.5 mA

0.4

Output LOW Voltage

= 1.8V, I

= 0.15 mA

0.2

Output HIGH Voltage

= 5V, I

= -3 mA

0.8

Output HIGH Voltage

= 2.5V, I

= -0.4mA

0.8

Output HIGH Voltage

= 1.8V, I

= -0.1mA

0.8

Input HIGH Voltage

0.7

+ 1

Input LOW Voltage

-1.0

0.3

Input Leakage Current

= 0V

-3

µA

Output Leakage Current

OUT

= 0V

CS = V

-3

µA

POWER SUPPLY CHARACTERISTICS

= 40°C to +85°C for Industrial.

Symbol Parameter

Test Conditions

Min.

Max.

Unit

Vcc Operating Current

Read/Write at 2.1 MHz (Vcc = 5V)

5.0

Vcc Operating Current

Read/Write at 2.1 MHz (Vcc = 2.5V)

3.0

Vcc Operating Current

Read/Write at 500 KHz (Vcc = 1.8V)

2.0

Standby Current

Vcc = 5.0V, V

= V

or GND

µA

CS = Vcc

Standby Current

Vcc = 2.5V, V

= V

or GND

µA

CS = Vcc

Standby Current

Vcc = 1.8V, V

= V

or GND

µA

CS = Vcc

POWER SUPPLY CHARACTERISTICS

= 40°C to +125°C for Automotive.

Symbol Parameter

Test Conditions

Min.

Max.

Unit

Vcc Operating Current

Read/Write at 2.1 MHz (Vcc = 5V)

6.0

Vcc Operating Current

Read/Write at 2.1 MHz (Vcc = 2.5V)

3.0

Standby Current

Vcc = 5.0V, V

= V

or GND

µA

CS = Vcc

Standby Current

Vcc =2.5V, V

= V

or GND

µA

CS = Vcc

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Advanced Information

Rev. 00E

06/13/06

IS25C128
IS25C256

ISSI

AC Characteristics

= 40°C to +85°C for Industrial.

1.8V

Vcc < 2.5V 2.5V Vcc 5.5V

Symbol

Parameter

Min

Max

Min

Max

Units

SCK

SCK Clock Frequency

0.5

2.1

MHz

Input Rise Time

µs

Input Fall Time

µs

SCK High Time

800

200

SCK Low Time

800

200

CS High Time

200

100

CSS

CS Setup Time

200

CSH

CS Hold Time

200

Data In Setup Time

Data In Hold Time

Hold Setup Time

100

Hold

Hold

Time

100

Output Valid

150

Output Hold Time

Hold to Output Low Z

100

Hold to Output High Z

250

100

DIS

Output Disable Time

250

100

Write Cycle Time

= 100pF

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Advanced Information

Rev. 00E

06/13/06

IS25C128
IS25C256

ISSI

AC Characteristics

= 40°C to +125°C for Automotive.

2.5V

Vcc 5.5V

Symbol

Parameter

Min

Max

Units

SCK

SCK Clock Frequency

2.1

MHz

Input Rise Time

µs

Input Fall Time

µs

SCK High Time

200

SCK Low Time

200

CS High Time

100

CSS

CS Setup Time

CSH

CS Hold Time

Data In Setup Time

Data In Hold Time

Hold Setup Time

Hold

Hold

Time

Output Valid

Output Hold Time

Hold to Output Low Z

Hold to Output High Z

100

DIS

Output Disable Time

100

Write Cycle Time

= 100pF

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Advanced Information

Rev. 00E

06/13/06

IS25C128
IS25C256

ISSI

ORDERING INFORMATION

Industrial Range: 40°C to +85°C

Voltage

Range

Part Number

Package

1.8V

IS25C128-2GI

Small Outline (JEDEC STD)

to 5.5V

IS25C128-2GLI

Small Outline (JEDEC STD), Lead-free

IS25C128-2PI

300-mil Plastic DIP

IS25C128-2PLI

300-mil Plastic DIP, Lead-free

IS25C128-2WI

Small Outline (EIAJ STD)

IS25C128-2WLI

Small Outline (EIAJ STD), Lead-free

1.8V

IS25C256-2GI

Small Outline (JEDEC STD)

to 5.5V

IS25C256-2GLI

Small Outline (JEDEC STD), Lead-free

IS25C256-2PI

300-mil Plastic DIP

IS25C256-2PLI

300-mil Plastic DIP, Lead-free

IS25C256-2WI

Small Outline (EIAJ STD)

IS25C256-2WLI

Small Outline (EIAJ STD), Lead-free

ORDERING INFORMATION

Automotive Range: 40°C to +125°C

Voltage

Range

Part Number

Package

2.5V

IS25C128-3GA3

Small Outline (JEDEC STD)

to 5.5V

IS25C128-3GLA3

Small Outline (JEDEC STD), Lead-free

IS25C128-3PA3

300-mil Plastic DIP

IS25C128-3PLA3

300-mil Plastic DIP, Lead-free

IS25C128-3WA3

Small Outline (EIAJ STD)

IS25C128-3WLA3

Small Outline (EIAJ STD), Lead-free

2.5V

IS25C256-3GA3

Small Outline (JEDEC STD)

to 5.5V

IS25C256-3GLA3

Small Outline (JEDEC STD), Lead-free

IS25C256-3PA3

300-mil Plastic DIP

IS25C256-3PLA3

300-mil Plastic DIP, Lead-free

IS25C256-3WA3

Small Outline (EIAJ STD)

IS25C256-3WLA3

Small Outline (EIAJ STD), Lead-free

PACKAGING INFORMATION

ISSI

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. D
02/14/03

Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.

300-mil Plastic DIP
Package Code: N,P

SEATING PLANE

FOR

32-PIN ONLY

MILLIMETERS

INCHES

Sym. Min.

Max.

Min.

Max.

N0.
Leads

3.68

4.57

0.145

0.180

0.38

0.015

0.36

0.56

0.014

0.022

1.14

1.52

0.045

0.060

0.81

1.17

0.032

0.046

0.20

0.33

0.008

0.013

9.12

9.53

0.359

0.375

7.62

8.26

0.300

0.325

6.20

6.60

0.244

0.260

8.13

9.65

0.320

0.380

2.54 BSC

0.100 BSC

3.18

0.125

0.64

0.762

0.025

0.030

Notes:
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and

should

be measured from the bottom of the package

4. Formed leads shall be planar with respect to one another within 0.004

inches at the seating plane.

PACKAGING INFORMATION

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. C
10/03/01

150-mil Plastic SOP
Package Code: G, GR

SEATING PLANE

Notes:
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and

should be

measured from the bottom of the package

4. Formed leads shall be planar with respect to one another within 0.004 inches at the

seating plane.

150-mil Plastic SOP (G, GR)

Symbol

Min

Max

Min

Max

Ref. Std.

Inches

No. Leads

0.068

1.73

0.004

0.009

0.1

0.23

0.013

0.020

0.33

0.51

0.007

0.010

0.18

0.25

0.189

0.197

4.8

0.150

0.157

3.81

3.99

0.228

0.245

5.79

6.22

0.050 BSC

1.27 BSC

0.020

0.035

0.51

0.89

PACKAGING INFORMATION

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. A
10/20/05

200-mil Plastic SOP
Package Code: W

Notes:
1. Controlling dimension: mm, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions

and

should be measured from the bottom of the package

200-mil Plastic SOP (W)

Symbol

Min

Max

Min

Max

Ref. Std.

Inches

No. Leads

0.085

2.16

0.004

0.009

0.10

0.23

0.014

0.018

0.35

0.45

0.006

0.014

0.15

0.35

0.203

0.211

5.15

5.35

0.204

0.213

5.18

5.40

0.303

0.325

7.70

8.26

0.050 BSC

1.27 BSC

0.020

0.033

0.51

0.85

SEATING PLANE

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