Integrated Silicon Solution, Inc. -- 1-800-379-4774
1
Rev. A
03/03/00
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. Copyright 2000, Integrated Silicon Solution, Inc.
IS41C16105
IS41LV16105
ISSI
FEATURES
TTL compatible inputs and outputs; tristate I/O
Refresh Interval:
-- 1,024 cycles/16 ms
Refresh Mode:
--
RAS-Only, CAS-before-RAS (CBR), and Hidden
JEDEC standard pinout
Single power supply:
-- 5V 10% (IS41C16105)
-- 3.3V 10% (IS41LV16105)
Byte Write and Byte Read operation via two
CAS
Extended Temperature Range -30
o
C to 85
o
C
Industrail Temperature Range -40
o
C to 85
o
C
DESCRIPTION
The
ISSI
IS41C16105 and IS41LV16105 are 1,048,576 x
16-bit high-performance CMOS Dynamic Random Access Memo-
ries. Fast Page Mode allows 1,024 random accesses within a single
row with access cycle time as short as 20 ns per 16-bit word. The
Byte Write control, of upper and lower byte, makes the IS41C16105
ideal for use in 16-, 32-bit wide data bus systems.
These features make the IS41C16105 and IS41LV16105 ideally
suited for high-bandwidth graphics, digital signal processing, high-
performance computing systems, and peripheral applications.
The IS41C16105 and IS41LV16105 are packaged in a
42-pin 400-mil SOJ and 400-mil 44- (50-) pin TSOP (Type II).
1M x 16 (16-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
KEY TIMING PARAMETERS
Parameter
-50
-60
Unit
Max.
RAS Access Time (t
RAC
)
50
60
ns
Max.
CAS Access Time (t
CAC
)
13
15
ns
Max. Column Address Access Time (t
AA
)
25
30
ns
Min. Fast Page Mode Cycle Time (t
PC
)
20
25
ns
Min. Read/Write Cycle Time (t
RC
)
84
104
ns
PIN CONFIGURATIONS
44(50)-Pin TSOP (Type II)
42-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A9
Address Inputs
I/O0-15
Data Inputs/Outputs
WE
Write Enable
OE
Output Enable
RAS
Row Address Strobe
UCAS
Upper Column Address Strobe
LCAS
Lower Column Address Strobe
Vcc
Power
GND
Ground
NC
No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
FEBRUARY 2000
Integrated Silicon Solution, Inc. -- 1-800-379-4774
3
Rev. A
03/03/00
IS41C16105
IS41LV16105
ISSI
TRUTH TABLE
Function
RAS
LCAS
UCAS
WE
OE
Address t
R
/t
C
I/O
Standby
H
H
H
X
X
X
High-Z
Read: Word
L
L
L
H
L
ROW/COL
D
OUT
Read: Lower Byte
L
L
H
H
L
ROW/COL
Lower Byte, D
OUT
Upper Byte, High-Z
Read: Upper Byte
L
H
L
H
L
ROW/COL
Lower Byte, High-Z
Upper Byte, D
OUT
Write: Word (Early Write)
L
L
L
L
X
ROW/COL
D
IN
Write: Lower Byte (Early Write)
L
L
H
L
X
ROW/COL
Lower Byte, D
IN
Upper Byte, High-Z
Write: Upper Byte (Early Write)
L
H
L
L
X
ROW/COL
Lower Byte, High-Z
Upper Byte, D
IN
Read-Write
(1,2)
L
L
L
H
L
L
H
ROW/COL
D
OUT
, D
IN
Hidden Refresh
Read
(2)
L
HL
L
L
H
L
ROW/COL
D
OUT
Write
(1,3)
L
HL
L
L
L
X
ROW/COL
D
OUT
RAS-Only Refresh
L
H
H
X
X
ROW/NA
High-Z
CBR Refresh
(4)
H
L
L
L
X
X
X
High-Z
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either
LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either
LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two
CAS signals must be active (LCAS or UCAS).
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A
03/03/00
IS41C16105
IS41LV16105
ISSI
Functional Description
The IS41C16105 and IS41LV16105 is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 16 address bits. These are entered
ten bits (A0-A9) at a time. The row address is latched by
the Row Address Strobe (
RAS). The column address is
latched by the Column Address Strobe (
CAS). RAS is
used to latch the first nine bits and
CAS is used the latter
nine bits.
The IS41C16105 and IS41LV16105 has two
CAS con-
trols,
LCAS and UCAS. The LCAS and UCAS inputs
internally generates a
CAS signal functioning in an iden-
tical manner to the single
CAS input on the other 1M x 16
DRAMs. The key difference is that each
CAS controls its
corresponding I/O tristate logic (in conjunction with
OE
and
WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
The IS41C16105 and IS41LV16105
CAS function is deter-
mined by the first
CAS (LCAS or UCAS) transitioning
LOW and the last transitioning back HIGH. The two
CAS
controls give the IS41C16105 and IS41LV16105 both
BYTE READ and BYTE WRITE cycle capabilities.
Memory Cycle
A memory cycle is initiated by bring
RAS LOW and it is
terminated by returning both
RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS or OE,
whichever occurs last, while holding
WE HIGH. The
column address must be held for a minimum time speci-
fied by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
,
t
CAC
and t
OEA
are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of
CAS or WE, whichever
occurs last.
Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1,024 row addresses (A0
through A9) with
RAS at least once every 16 ms. Any
read, write, read-modify-write or
RAS-only cycle re-
freshes the addressed row.
2. Using a
CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding
CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the V
CC
supply, an initial pause of
200 s is required followed by a minimum of eight
initialization cycles (any combination of cycles contain-
ing a
RAS signal).
During power-on, it is recommended that
RAS track with
V
CC
or be held at a valid V
IH
to avoid current surges.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
5
Rev. A
03/03/00
IS41C16105
IS41LV16105
ISSI
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameters
Rating
Unit
V
T
Voltage on Any Pin Relative to GND
5V
1.0 to +7.0
V
3.3V
0.5 to +4.6
V
CC
Supply Voltage
5V
1.0 to +7.0
V
3.3V
0.5 to +4.6
I
OUT
Output Current
50
mA
P
D
Power Dissipation
1
W
T
A
Commercial Operation Temperature
0 to +70
C
Extended Temperature
30 to +85
C
Industrail Temperature
40 to +85
C
T
STG
Storage Temperature
55 to +125
C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
5V
4.5
5.0
5.5
V
3.3V
3.0
3.3
3.6
V
IH
Input High Voltage
5V
2.4
--
V
CC
+ 1.0
V
3.3V
2.0
--
V
CC
+ 0.3
V
IL
Input Low Voltage
5V
1.0
--
0.8
V
3.3V
0.3
--
0.8
T
A
Commercial Ambient Temperature
0
--
70
C
Extended Ambient Temperature
30
--
85
C
Industrail Ambient Temperature
40
--
85
C
CAPACITANCE
(1,2)
Symbol
Parameter
Max.
Unit
C
IN
1
Input Capacitance: A0-A9
5
pF
C
IN
2
Input Capacitance:
RAS, UCAS, LCAS, WE, OE
7
pF
C
IO
Data Input/Output Capacitance: I/O0-I/O15
7
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz,
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