IS41C4100
IS41LV4100

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

PRELIMINARY INFORMATION

Rev. 00A

09/10/01

This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

1Meg x 4 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE

FEATURES

· TTL compatible inputs and outputs

· Refresh Interval: 1024 cycles/16 ms

· Refresh Mode :

RAS

-Only,

CAS

-before-

RAS

(CBR), and Hidden

· JEDEC standard pinout

· Single power supply

5V ± 10% (IS41C4100)

3.3V ± 10% (IS41LV4100)

· Industrail Temperature Range -40

C to 85

DESCRIPTION

The

ISSI

IS41C4100 and IS41LV4100 are 1,048,576 x 4-bit

high-performance CMOS Dynamic Random Access
Memory. Both products offer accelerated cycle access
EDO Page Mode. EDO Page Mode allows 512 random
accesses within a single row with access cycle time as
short as 10ns per 4-bit word.

These features make the IS41C4100 and IS41LV4100 ideally
suited for high band-width graphics, digital signal processing,
high-performance computing systems, and peripheral applications.

The IS41C4100 and IS41LV4100 are available in a 20-pin,
300-mil SOJ package.

KEY TIMING PARAMETERS

Parameter

-35

-60

Unit

Max.

RAS

Access Time (t

RAC

)

Max.

CAS

Access Time (t

CAC

)

Max. Column Address Access Time (t

)

Min. Fast Page Mode Cycle Time (t

)

Min. Read/Write Cycle Time (t

)

110

PIN DESCRIPTIONS

A0-A9

Address Inputs

I/O0-I/O3

Data Inputs/Outputs

Write Enable

Output Enable

RAS

Row Address Strobe

CAS

Column Address Strobe

Power

GND

Ground

No Connection

PIN CONFIGURATION

20-Pin SOJ

I/O0

I/O1

RAS

Vcc

GND

I/O3

I/O2

CAS
OE

PRELIMINARY INFORMATION

SEPTEMBER 2001

IS41C4100
IS41LV4100

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

PRELIMINARY INFORMATION

Rev. 00A

09/10/01

TRUTH TABLE

Function

RAS

CAS

Address t

I/O

Standby

High-Z

Read: Word

ROW/COL

OUT

Read: Lower Byte

ROW/COL

Lower Byte, D

OUT

Upper Byte, High-Z

Read: Upper Byte

ROW/COL

Lower Byte, High-Z
Upper Byte, D

OUT

Write: Word (Early Write)

ROW/COL

Write: Lower Byte (Early Write)

ROW/COL

Lower Byte, D

Upper Byte, High-Z

Write: Upper Byte (Early Write)

ROW/COL

Lower Byte, High-Z
Upper Byte, D

Read-Write

(1,2)

ROW/COL

OUT

, D

EDO Page-Mode Read

(2)

1st Cycle:

ROW/COL

OUT

2nd Cycle:

NA/COL D

OUT

Any Cycle:

NA/NA

OUT

EDO Page-Mode Write

(1)

1st Cycle:

ROW/COL, D

2nd Cycle:

NA/COL D

EDO Page-Mode

1st Cycle:

ROW/COL

OUT

, D

Read-Write

(1,2)

2nd Cycle:

NA/COL D

OUT

, D

Hidden Refresh

Read

ROW/COL

OUT

Write

ROW/COL

OUT

RAS

-Only Refresh

ROW/NA

High-Z

CBR Refresh

(3)

High-Z

Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either

LCAS

UCAS

active).

2. These READ cycles may also be BYTE READ cycles (either

LCAS

UCAS

active).

3. At least one of the two

CAS

signals must be active (

LCAS

UCAS

IS41C4100
IS41LV4100

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

PRELIMINARY INFORMATION

Rev. 00A

09/10/01

Functional Description

The IS41C4100 and IS41LV4100 is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 19 address bits. The first ten
address bits (A0-A9) are entered as row address and
latter nine bits nine address bits (A0-A8) are entered as
column address. The row address is latched by the Row
Address Strobe (

RAS

). The column address is latched by

the Column Address Strobe (

CAS

RAS

is used to latch

the first nine bits and

CAS

is used the latter nine bits.

Memory Cycle

A memory cycle is initiated by bring

RAS

LOW and it is

terminated by returning both

RAS

and

CAS

HIGH. To

ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t

RAS

time has expired. A new

cycle must not be initiated until the minimum precharge
time t

, t

has elapsed.

Read Cycle

A read cycle is initiated by the falling edge of

CAS

whichever occurs last, while holding

HIGH. The

column address must be held for a minimum time speci-
fied by t

. Data Out becomes valid only when t

RAC

, t

CAC

and t

OEA

are all satisfied. As a result, the access time

is dependent on the timing relationships between these
parameters.

Write Cycle

A write cycle is initiated by the falling edge of

CAS

and

, whichever occurs last. The input data must be valid

at or before the falling edge of

CAS

, whichever

occurs last.

Refresh Cycle

To retain data, 1024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.

1. By clocking each of the 1024 row addresses (A0

through A9) with

RAS

at least once every 16 ms. Any

read, write, read-modify-write or

RAS

-only cycle re-

freshes the addressed row.

2. Using a

CAS

-before-

RAS

refresh cycle.

CAS

-before-

RAS

refresh is activated by the falling edge of

RAS

while holding

CAS

LOW. In

CAS

-before-

RAS

refresh

cycle, an internal 10-bit counter provides the row
addresses and the external address inputs are ig-
nored.

CAS

-before-

RAS

is a refresh-only mode and no data

access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.

Extended Data Out Page Mode

EDO page mode operation permits all 512 columns within
a selected row to be randomly accessed at a high data
rate.

In EDO page mode read cycle, the data-out is held to the
next

CAS

cycle's falling edge, instead of the rising edge.

For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the

CAS

cycle time becomes shorter. There-

fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the

CAS

cycle time becomes shorter.

In EDO page mode, due to the extended data function, the

CAS

cycle time can be shorter than in the fast page mode

if the timing margin is the same.

The EDO page mode allows both read and write opera-
tions during one

RAS

cycle, but the performance is

equivalent to that of the fast page mode in that case.

Power-On

After application of the V

supply, an initial pause of

200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a

RAS

signal).

During power-on, it is recommended that

RAS

track with

or be held at a valid V

to avoid current surges.

IS41C4100
IS41LV4100

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

PRELIMINARY INFORMATION

Rev. 00A

09/10/01

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameters

Rating

Unit

Voltage on Any Pin Relative to GND

1.0 to +7.0

3.3V

-0.5 to 4.6

Supply Voltage

1.0 to +7.0

3.3V

-0.5 to 4.6

OUT

Output Current

Power Dissipation

Commercial Operation Temperature

0 to +70

°C

Industrail Temperature

40 to +85

°C

STG

Storage Temperature

55 to +125

°C

Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

CAPACITANCE

(1,2)

Symbol

Parameter

Max.

Unit

Input Capacitance: A0-A9

Input Capacitance:

RAS

CAS

Data Input/Output Capacitance: I/O0-I/O3

Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T

= 25°C, f = 1 MHz,

RECOMMENDED OPERATING CONDITIONS

(Voltages are referenced to GND.)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

4.5

5.0

5.5

3.3V

3.0

3.3

3.6

Input High Voltage

2.4

+ 1.0

3.3V

2.0

+ 0.3

Input Low Voltage

1.0

0.8

3.3V

0.3

0.8

Commercial Ambient Temperature

°C

Industrail Ambient Temperature

°C

IS41C4100
IS41LV4100

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

PRELIMINARY INFORMATION

Rev. 00A

09/10/01

ELECTRICAL CHARACTERISTICS

(1)

(Recommended Operation Conditions unless otherwise noted.)

Symbol Parameter

Test Condition

Speed

Min.

Max.

Unit

Input Leakage Current

Any input 0V

Vcc

µA

Other inputs not under test = 0V

Output Leakage Current

Output is disabled (Hi-Z)

µA

OUT

Vcc

Output High Voltage Level

= 2.5 mA

2.4

Output Low Voltage Level

= +2.1 mA

0.4

Stand-by Current: TTL

RAS

CAS

Commercial

Industrial

Commercial

Industrial

Stand-by Current: CMOS

RAS

CAS

0.2V

0.5

Operating Current:

RAS

CAS

-35

100

Random Read/Write

(2,3,4)

Address Cycling, t

= t

(min.)

-60

Average Power Supply Current

Operating Current:

RAS

= V

CAS

-35

120

EDO Page Mode

(2,3,4)

Cycling t

= t

(min.)

-60

Average Power Supply Current

Refresh Current:

RAS

Cycling,

CAS

-35

100

RAS

-Only

(2,3)

= t

(min.)

-60

Average Power Supply Current

Refresh Current:

RAS

CAS

Cycling

-35

100

CBR

(2,3,5)

= t

(min.)

-60

Average Power Supply Current

Notes:
1. An initial pause of 200 µs is required after power-up followed by eight

RAS

refresh cycles (

RAS

-Only or CBR) before proper device

operation is assured. The eight

RAS

cycles wake-up should be repeated any time the t

REF

refresh requirement is exceeded.

2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.

IS41C4100
IS41LV4100

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

PRELIMINARY INFORMATION

Rev. 00A

09/10/01

AC CHARACTERISTICS

(1,2,3,4,5,6)

(Recommended Operating Conditions unless otherwise noted.)

-35

-60

Symbol

Parameter

Min.

Max.

Min.

Max.

Units

Random READ or WRITE Cycle Time

110

RAC

Access Time from

RAS

(6, 7)

CAC

Access Time from

CAS

(6, 8, 15)

Access Time from Column-Address

(6)

RAS

Pulse Width

10K

RAS

Precharge Time

CAS

Pulse Width

(26)

10K

CAS

Precharge Time

(9, 25)

CSH

CAS

Hold Time

(21)

RCD

RAS

CAS

Delay Time

(10, 20)

ASR

Row-Address Setup Time

RAH

Row-Address Hold Time

ASC

Column-Address Setup Time

(20)

CAH

Column-Address Hold Time

(20)

Column-Address Hold Time

(referenced to

RAS

)

RAD

RAS

to Column-Address Delay Time

(11)

RAL

Column-Address to

RAS

Lead Time

RPC

RAS

CAS

Precharge Time

RSH

RAS

Hold Time

(27)

115

CLZ

CAS

to Output in Low-Z

(15, 29)

CRP

CAS

RAS

Precharge Time

(21)

Output Disable Time

(19, 28, 29)

/ t

OEA

Output Enable Time

(15, 16)

OEHC

HIGH Hold Time from

CAS

HIGH

OEP

HIGH Pulse Width

OES

LOW to

CAS

HIGH Setup Time

RCS

Read Command Setup Time

(17, 20)

RRH

Read Command Hold Time

(referenced to

RAS

)

(12)

RCH

Read Command Hold Time

(referenced to

CAS

)

(12, 17, 21)

WCH

Write Command Hold Time

(17, 27)

WCR

Write Command Hold Time

(referenced to

RAS

)

(17)

IS41C4100
IS41LV4100

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

PRELIMINARY INFORMATION

Rev. 00A

09/10/01

AC CHARACTERISTICS (Continued)

(1,2,3,4,5,6)

(Recommended Operating Conditions unless otherwise noted.)

-35

-60

Symbol

Parameter

Min.

Max.

Min.

Max.

Units

Write Command Pulse Width

(17)

WPZ

Pulse Widths to Disable Outputs

RWL

Write Command to

RAS

Lead Time

(17)

CWL

Write Command to

CAS

Lead Time

(17, 21)

WCS

Write Command Setup Time

(14, 17, 20)

DHR

Data-in Hold Time (referenced to

RAS

)

Precharge during WRITE Cycle

OEH

Hold Time from

during

READ-MODIFY-WRITE cycle

(18)

Data-In Setup Time

(15, 22)

Data-In Hold Time

(15, 22)

RWC

READ-MODIFY-WRITE Cycle Time

140

RWD

RAS

Delay Time during

READ-MODIFY-WRITE Cycle

(14)

CWD

CAS

Delay Time

(14, 20)

AWD

Column-Address to

Delay Time

(14)

EDO Page Mode READ or WRITE

Cycle Time

(24)

RASP

RAS

Pulse Width in EDO Page Mode

100K

CPA

Access Time from

CAS

Precharge

(15)

PRWC

EDO Page Mode READ-WRITE

Cycle Time

(24)

COH

DOH

Data Output Hold after

CAS

LOW

OFF

Output Buffer Turn-Off Delay from

CAS

RAS

(13,15,19, 29)

WHZ

Output Disable Delay from

CLCH

Last

CAS

going LOW to First

CAS

returning HIGH

(23)

CSR

CAS

Setup Time (CBR REFRESH)

(30, 20)

CHR

CAS

Hold Time (CBR REFRESH)

(30, 21)

ORD

Setup Time prior to

RAS

during

HIDDEN REFRESH Cycle

REF

Refresh Period (1024 Cycles)

Transition Time (Rise or Fall)

(2, 3)

IS41C4100
IS41LV4100

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

PRELIMINARY INFORMATION

Rev. 00A

09/10/01

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight

RAS

refresh cycle (

RAS

-Only or CBR) before proper device

operation is assured. The eight

RAS

cycles wake-up should be repeated any time the t

REF

refresh requirement is exceeded.

2. V

(MIN) and V

(MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V

and V

(or between V

and V

) and assume to be 1 ns for all inputs.

3. In addition to meeting the transition rate specification, all input signals must transit between V

and V

(or between V

and V

) in

a monotonic manner.

4. If

CAS

and

RAS

= V

, data output is High-Z.

5. If

CAS

= V

, data output may contain data from the last valid READ cycle.

6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that t

RCD

- t

RCD

(MAX). If t

RCD

is greater than the maximum recommended value shown in this table, t

RAC

will increase by

the amount that t

RCD

exceeds the value shown.

8. Assumes that t

RCD

· t

RCD

(MAX).

9. If

CAS

is LOW at the falling edge of

RAS

, data out will be maintained from the previous cycle. To initiate a new cycle and clear the

data output buffer,

CAS

and

RAS

must be pulsed for t

10. Operation with the t

RCD

(MAX) limit ensures that t

RAC

(MAX) can be met. t

RCD

(MAX) is specified as a reference point only; if t

RCD

is greater than the specified t

RCD

(MAX) limit, access time is controlled exclusively by t

CAC

11. Operation within the t

RAD

(MAX) limit ensures that t

RCD

(MAX) can be met. t

RAD

(MAX) is specified as a reference point only; if t

RAD

is greater than the specified t

RAD

(MAX) limit, access time is controlled exclusively by t

12. Either t

RCH

or t

RRH

must be satisfied for a READ cycle.

13. t

OFF

(MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to V

or V

14. t

WCS

, t

RWD

, t

AWD

and t

CWD

are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If t

WCS

(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If t

RWD

(MIN), t

AWD

· t

AWD

(MIN) and t

CWD

· t

CWD

(MIN), the cycle is a READ-WRITE cycle and the data output will contain data read

from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until

CAS

and

RAS

back to V

) is indeterminate.

held HIGH and

taken LOW after

CAS

goes LOW result in a LATE WRITE (

-controlled)

cycle.

15. Output parameter (I/O) is referenced to corresponding

CAS

input, I/O0-I/O7 by

LCAS

and I/O8-I/O15 by

UCAS

16. During a READ cycle, if

is LOW then taken HIGH before

CAS

goes HIGH, I/O goes open. If

is tied permanently LOW, a

LATE WRITE or READ-MODIFY-WRITE is not possible.

17. Write command is defined as

going low.

18. LATE WRITE and READ-MODIFY-WRITE cycles must have both t

and t

OEH

met (

HIGH during WRITE cycle) in order to

ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if

CAS

remains LOW and

is taken back to LOW after t

OEH

is met.

19. The I/Os are in open during READ cycles once t

or t

OFF

occur.

20. The first

CAS

edge to transition LOW.

21. The last

CAS

edge to transition HIGH.

22. These parameters are referenced to

CAS

leading edge in EARLY WRITE cycles and

leading edge in LATE WRITE or

READ-MODIFY-WRITE cycles.

23. Last falling

CAS

edge to first rising

CAS

edge.

24. Last rising

CAS

edge to next cycle's last rising

CAS

edge.

25. Last rising

CAS

edge to first falling

CAS

edge.

26. Each

CAS

must meet minimum pulse width.

27. Last

CAS

to go LOW.

28. I/Os controlled, regardless

UCAS

and

LCAS

29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.

IS41C4100
IS41LV4100

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

PRELIMINARY INFORMATION

Rev. 00A

09/10/01

EDO-PAGE-MODE READ CYCLE

Note:
1. t

can be measured from falling edge of

CAS

to falling edge of

CAS

, or from rising edge of

CAS

to rising edge of

CAS

. Both

measurements must meet the t

specifications.

RASP

ADDRESS

CAS

RAS

Row

CAS,

CLCH

CRP

RCD

CSH

CAS,

CLCH

CAH

CAS,

CLCH

RAL

RSH

(1)

ASR

RAH

RAD

Column

CAH

Column

ASC

I/O

Open

Valid Data

CPA

CAC

RAC

COH

CLZ

OEP

OES

OEHC

Valid Data

RCH

RRH

CPA

CAC

OFF

CLZ

Valid Data

ASC

RCS

Don't Care

IS41C4100
IS41LV4100

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

PRELIMINARY INFORMATION

Rev. 00A

09/10/01

EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)

Note:
1. t

can be measured from falling edge of

CAS

to falling edge of

CAS

, or from rising edge of

CAS

to rising edge of

CAS

. Both

measurements must meet the t

specifications.

RASP

ADDRESS

CAS

RAS

Row

CRP

RCD

CSH

CAH

CAS,

CLCH

RAL

RSH

RAH

RAD

ASR

Column

CAH

Column

ASC

CAS,

CLCH

CAS,

CLCH

I/O

ASC

RWD

RCS

CWL

AWD

CWD

CAC

CLZ

AWD

CWD

CWL

AWD

CWD

CWL

RWL

Open

OUT

OEH

CPA

CAC

CLZ

OUT

CAC

CLZ

OUT

CPA

RAC

/ t

PRWC

(1)

Don't Care

IS41C4100
IS41LV4100

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

PRELIMINARY INFORMATION

Rev. 00A

09/10/01

ORDERING INFORMATION : 5V

Commercial Range: 0

C to 70

Speed (ns) Order Part No.

Package

IS41C4100-35J

20-pin, 300-mil SOJ

IS41C4100-60J

20-pin, 300-mil SOJ

ORDERING INFORMATION : 5V

Industrail Range: -40

C to 85

Speed (ns) Order Part No.

Package

IS41C4100-60JI

20-pin, 300-mil SOJ

ORDERING INFORMATION : 3.3V

Commercial Range: 0

C to 70

Speed (ns) Order Part No.

Package

IS41LV4100-35J

20-pin, 300-mil SOJ

IS41LV4100-60J

20-pin, 300-mil SOJ

ORDERING INFORMATION : 3.3V

Industrail Range: -40

C to 85

Speed (ns) Order Part No.

Package

IS41LV4100-60JI

20-pin, 300-mil SOJ

ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: 1-800-379-4774

Fax: (408) 588-0806

E-mail: sales@issi.com

www.issi.com

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