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IS41C16100
IS41LV16100

ISSI

Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.

FEATURES

· TTL compatible inputs and outputs; tristate I/O

· Refresh Interval:

-- Auto refresh Mode: 1,024 cycles /16 ms
--

RAS

-Only,

CAS

-before-

RAS

(CBR), and Hidden

-- Self refresh Mode - 1,024 cycles / 128ms

· JEDEC standard pinout

· Single power supply:

-- 5V ± 10% (IS41C16100)
-- 3.3V ± 10% (IS41LV16100)

· Byte Write and Byte Read operation via two

CAS

· Industrail Temperature Range -40

C to 85

DESCRIPTION

The

ISSI

IS41C16100 and IS41LV16100 are 1,048,576 x 16-bit

high-performance CMOS Dynamic Random Access Memories.
These devices offer an accelerated cycle access called EDO Page
Mode. EDO Page Mode allows 1,024 random accesses within a
single row with access cycle time as short as 20 ns per 16-bit word.
The Byte Write control, of upper and lower byte, makes the
IS41C16100 ideal for use in 16-bit and 32-bit wide data bus systems.

These features make the IS41C16100and IS41LV16100 ideally suited
for high-bandwidth graphics, digital signal processing, high-
performance computing systems, and peripheral applications.

The IS41C16100 and IS41LV16100 are packaged in a 42-pin 400-
mil SOJ and 400-mil 50- (44-) pin TSOP (Type II). The lead-free 400-
mil 50- (44-) option is available too.

1M x 16 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE

KEY TIMING PARAMETERS

Parameter

-50

-60

Unit

Max.

RAS

Access Time (t

RAC

)

Max.

CAS

Access Time (t

CAC

)

Max. Column Address Access Time (t

)

Min. EDO Page Mode Cycle Time (t

)

Min. Read/Write Cycle Time (t

)

104

PIN CONFIGURATIONS

50(44)-Pin TSOP (Type II)

42-Pin SOJ

VCC

I/O0

I/O1

I/O2

I/O3

VCC

I/O4

I/O5

I/O6

I/O7

RAS

VCC

GND

I/O15

I/O14

I/O13

I/O12

GND

I/O11

I/O10

I/O9

I/O8

LCAS

UCAS

GND

PIN DESCRIPTIONS

A0-A9

Address Inputs

I/O0-15

Data Inputs/Outputs

Write Enable

Output Enable

RAS

Row Address Strobe

UCAS

Upper Column Address Strobe

LCAS

Lower Column Address Strobe

Vcc

Power

GND

Ground

No Connection

April 2003

VCC

I/O0

I/O1

I/O2

I/O3

VCC

I/O4

I/O5

I/O6

I/O7

RAS

VCC

GND

I/O15

I/O14

I/O13

I/O12

GND

I/O11

I/O10

I/O9

I/O8

LCAS

UCAS

GND

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ISSI

TRUTH TABLE

Function

RAS

LCAS

LCAS UCAS

UCAS

Address t

I/O

Standby

High-Z

Read: Word

ROW/COL

OUT

Read: Lower Byte

ROW/COL

Lower Byte, D

OUT

Upper Byte, High-Z

Read: Upper Byte

ROW/COL

Lower Byte, High-Z
Upper Byte, D

OUT

Write: Word (Early Write)

ROW/COL

Write: Lower Byte (Early Write)

ROW/COL

Lower Byte, D

Upper Byte, High-Z

Write: Upper Byte (Early Write)

ROW/COL

Lower Byte, High-Z
Upper Byte, D

Read-Write

(1,2)

ROW/COL

OUT

, D

EDO Page-Mode Read

(2)

1st Cycle:

ROW/COL

OUT

2nd Cycle:

NA/COL

OUT

Any Cycle:

NA/NA

OUT

EDO Page-Mode Write

(1)

1st Cycle:

ROW/COL

2nd Cycle:

NA/COL

EDO Page-Mode

(1,2)

1st Cycle:

ROW/COL

OUT

, D

Read-Write

2nd Cycle:

NA/COL

OUT

, D

Hidden Refresh

Read

(2)

ROW/COL

OUT

Write

(1,3)

ROW/COL

OUT

RAS

-Only Refresh

ROW/NA

High-Z

CBR Refresh

(4)

High-Z

Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either

LCAS

UCAS

active).

2. These READ cycles may also be BYTE READ cycles (either

LCAS

UCAS

active).

3. EARLY WRITE only.
4. At least one of the two

CAS

signals must be active (

LCAS

UCAS

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ISSI

Functional Description

The IS41C16100 and IS41LV16100 is a CMOS DRAM
optimized for high-speed bandwidth, low power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 16 address bits. These are entered
ten bits (A0-A9) at time. The row address is latched by
the Row Address Strobe (

RAS

). The column address is

latched by the Column Address Strobe (

CAS

RAS

is used

to latch the first nine bits and

CAS

is used to latch the latter nine bits.

The IS41C16100 and IS41LV16100 has two

CAS

con-

trols,

LCAS

and

UCAS

. The

LCAS

and

UCAS

inputs internally

generates a

CAS

signal functioning in an identical manner to the

single

CAS

input on the other 1M x 16 DRAMs. The key differ-

ence is that each

CAS

controls its corresponding I/O

tristate logic (in conjunction with

and

RAS

LCAS

controls I/O0 through I/O7 and

UCAS

controls I/O8 through I/O15.

The IS41C16100 and IS41LV16100

CAS

function is

determined by the first

CAS

(

LCAS

UCAS

) transitioning

LOW and the last transitioning back HIGH. The two

CAS

controls give the IS41C16100 and IS41LV16100 both
BYTE READ and BYTE WRITE cycle capabilities.

Memory Cycle

A memory cycle is initiated by bring

RAS

LOW and it is

terminated by returning both

RAS

and

CAS

HIGH. To

ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t

RAS

time has expired. A new

cycle must not be initiated until the minimum precharge
time t

, t

has elapsed.

Read Cycle

A read cycle is initiated by the falling edge of

CAS

whichever occurs last, while holding

HIGH. The column

address must be held for a minimum time specified by t

Data Out becomes valid only when t

RAC

, t

CAC

and t

OEA

are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.

Write Cycle

A write cycle is initiated by the falling edge of

CAS

and

whichever occurs last. The input data must be valid at or
before the falling edge of

CAS

, whichever occurs first.

Auto Refresh Cycle

To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.

1. By clocking each of the 1,024 row addresses (A0 through A9)

with

RAS

at least once every 128 ms. Any read, write, read-

modify-write or

RAS

-only cycle refreshes the addressed row.

2. Using a

CAS

-before-

RAS

refresh cycle.

CAS

-before-

RAS

refresh is activated by the falling edge of

RAS

while holding

CAS

LOW. In

CAS

-before-

RAS

refresh

cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.

CAS

-before-

RAS

is a refresh-only mode and no data

access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.

Self Refresh Cycle

The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 128 ms.
i.e., 125 µs per row when using distributed CBR refreshes.
The feature also allows the user the choice of a fully
static, low power data retention mode. The optional Self
Refresh feature is initiated by performing a CBR Refresh
cycle and holding

RAS

LOW for the specified t

RAS

The Self Refresh mode is terminated by driving

RAS

HIGH for a minimum time of t

. This delay allows for the

completion of any internal refresh cycles that may be in
process at the time of the

RAS

LOW-to-HIGH transition.

If the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting Self Refresh.

However, if the DRAM controller utilizes a

RAS

-only or

burst refresh sequence, all 1,024 rows must be refreshed
within the average internal refresh rate, prior to the
resumption of normal operation.

Extended Data Out Page Mode

EDO page mode operation permits all 1,024 columns within
a selected row to be randomly accessed at a high data rate.

In EDO page mode read cycle, the data-out is held to the
next

CAS

cycle's falling edge, instead of the rising edge.

For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the

CAS

cycle time becomes shorter. There-

fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the

CAS

cycle time becomes shorter.

In EDO page mode, due to the extended data function, the

CAS

cycle time can be shorter than in the fast page mode

if the timing margin is the same.

The EDO page mode allows both read and write opera-
tions during one

RAS

cycle, but the performance is

equivalent to that of the fast page mode in that case.

Power-On

After application of the V

supply, an initial pause of

200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles contain-
ing a

RAS

signal).

During power-on, it is recommended that

RAS

track with

or be held at a valid V

to avoid current surges.

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ISSI

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameters

Rating

Unit

Voltage on Any Pin Relative to GND

1.0 to +7.0

3.3V

0.5 to +4.6

Supply Voltage

1.0 to +7.0

3.3V

0.5 to +4.6

OUT

Output Current

Power Dissipation

Commercial Operation Temperature

0 to +70

°C

Industrial Operationg Temperature

-40 to +85

°C

STG

Storage Temperature

55 to +125

°C

Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltages are referenced to GND.)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

4.5

5.0

5.5

3.3V

3.0

3.3

3.6

Input High Voltage

2.4

+ 1.0

3.3V

2.0

+ 0.3

Input Low Voltage

1.0

0.8

3.3V

0.3

0.8

Commercial Ambient Temperature

°C

Industrial Ambient Temperature

°C

CAPACITANCE

(1,2)

Symbol

Parameter

Max.

Unit

Input Capacitance: A0-A9

Input Capacitance:

RAS

UCAS

LCAS

Data Input/Output Capacitance: I/O0-I/O15

Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T

= 25°C, f = 1 MHz.

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ISSI

ELECTRICAL CHARACTERISTICS

(1)

(Recommended Operating Conditions unless otherwise noted.)

Symbol

Parameter

Test Condition

Speed

Min.

Max.

Unit

Input Leakage Current

Any input 0V

Vcc

µA

Other inputs not under test = 0V

Output Leakage Current

Output is disabled (Hi-Z)

µA

OUT

Vcc

Output High Voltage Level

= 5.0 mA (5V)

2.4

= 2.0 mA (3.3V)

Output Low Voltage Level

= 4.2 mA (5V)

0.4

= 2.0 mA (3.3V)

Standby Current: TTL

RAS

LCAS

UCAS

Commerical

3.3V

Industrial

3.3V

Standby Current: CMOS

RAS

LCAS

UCAS

0.2V

3.3V

Operating Current:

RAS

LCAS

UCAS

-50

160

Random Read/Write

(2,3,4)

Address Cycling, t

= t

(min.)

-60

145

Average Power Supply Current

Operating Current:

RAS

= V

LCAS

UCAS

-50

EDO Page Mode

(2,3,4)

Cycling t

= t

(min.)

-60

Average Power Supply Current

Refresh Current:

RAS

Cycling,

LCAS

UCAS

-50

160

RAS

-Only

(2,3)

= t

(min.)

-60

145

Average Power Supply Current

Refresh Current:

RAS

LCAS

UCAS

Cycling

-50

160

CBR

(2,3,5)

= t

(min.)

-60

145

Average Power Supply Current

Notes:
1. An initial pause of 200 µs is required after power-up followed by eight

RAS

refresh cycles (

RAS

-Only or CBR) before proper device

operation is assured. The eight

RAS

cycles wake-up should be repeated any time the t

REF

refresh requirement is exceeded.

2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.

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ISSI

AC CHARACTERISTICS

(1,2,3,4,5,6)

(Recommended Operating Conditions unless otherwise noted.)

-50

-60

Symbol

Parameter

Min.

Max.

Min.

Max.

Units

Random READ or WRITE Cycle Time

104

RAC

Access Time from

RAS

(6, 7)

CAC

Access Time from

CAS

(6, 8, 15)

Access Time from Column-Address

(6)

RAS

Pulse Width

10K

RAS

Precharge Time

CAS

Pulse Width

(26)

10K

CAS

Precharge Time

(9, 25)

CSH

CAS

Hold Time

(21)

RCD

RAS

CAS

Delay Time

(10, 20)

ASR

Row-Address Setup Time

RAH

Row-Address Hold Time

ASC

Column-Address Setup Time

(20)

CAH

Column-Address Hold Time

(20)

Column-Address Hold Time

(referenced to

RAS

)

RAD

RAS

to Column-Address Delay Time

(11)

RAL

Column-Address to

RAS

Lead Time

RPC

RAS

CAS

Precharge Time

RSH

RAS

Hold Time

(27)

RHCP

RAS

Hold Time from

CAS

Precharge

CLZ

CAS

to Output in Low-Z

(15, 29)

CRP

CAS

RAS

Precharge Time

(21)

Output Disable Time

(19, 28, 29)

Output Enable Time

(15, 16)

OED

Output Enable Data Delay (Write)

OEHC

HIGH Hold Time from

CAS

HIGH

OEP

HIGH Pulse Width

OES

LOW to

CAS

HIGH Setup Time

RCS

Read Command Setup Time

(17, 20)

RRH

Read Command Hold Time

(referenced to

RAS

)

(12)

RCH

Read Command Hold Time

(referenced to

CAS

)

(12, 17, 21)

WCH

Write Command Hold Time

(17, 27)

WCR

Write Command Hold Time

(referenced to

RAS

)

(17)

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ISSI

AC CHARACTERISTICS (Continued)

(1,2,3,4,5,6)

(Recommended Operating Conditions unless otherwise noted.)

-50

-60

Symbol

Parameter

Min.

Max.

Min.

Max.

Units

Write Command Pulse Width

(17)

WPZ

Pulse Widths to Disable Outputs

RWL

Write Command to

RAS

Lead Time

(17)

CWL

Write Command to

CAS

Lead Time

(17, 21)

WCS

Write Command Setup Time

(14, 17, 20)

DHR

Data-in Hold Time (referenced to

RAS

)

ACH

Column-Address Setup Time to

CAS

Precharge during WRITE Cycle

OEH

Hold Time from

during

READ-MODIFY-WRITE cycle

(18)

Data-In Setup Time

(15, 22)

Data-In Hold Time

(15, 22)

RWC

READ-MODIFY-WRITE Cycle Time

108

133

RWD

RAS

Delay Time during

READ-MODIFY-WRITE Cycle

(14)

CWD

CAS

Delay Time

(14, 20)

AWD

Column-Address to

Delay Time

(14)

EDO Page Mode READ or WRITE

Cycle Time

(24)

RASP

RAS

Pulse Width in EDO Page Mode

100K

CPA

Access Time from

CAS

Precharge

(15)

PRWC

EDO Page Mode READ-WRITE

Cycle Time

(24)

COH

Data Output Hold after

CAS

LOW

OFF

Output Buffer Turn-Off Delay from

1.6

CAS

RAS

(13,15,19, 29)

WHZ

Output Disable Delay from

CLCH

Last

CAS

going LOW to First

CAS

returning HIGH

(23)

CSR

CAS

Setup Time (CBR REFRESH)

(30, 20)

CHR

CAS

Hold Time (CBR REFRESH)

(30, 21)

ORD

Setup Time prior to

RAS

during

HIDDEN REFRESH Cycle

REF

Auto Refresh Period (1,024 Cycles)

REF

Self Refresh Period (1,024 Cycles)

128

Transition Time (Rise or Fall)

(2, 3)

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ISSI

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight

RAS

refresh cycle (

RAS

-Only or CBR) before proper device

operation is assured. The eight

RAS

cycles wake-up should be repeated any time the t

REF

refresh requirement is exceeded.

2. V

(MIN) and V

(MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V

and

(or between V

and V

) and assume to be 1 ns for all inputs.

3. In addition to meeting the transition rate specification, all input signals must transit between V

and V

(or between V

and V

) in a

monotonic manner.

4. If

CAS

and

RAS

= V

, data output is High-Z.

5. If

CAS

= V

, data output may contain data from the last valid READ cycle.

6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that t

RCD

- t

RCD

(MAX). If t

RCD

is greater than the maximum recommended value shown in this table, t

RAC

will increase by the

amount that t

RCD

exceeds the value shown.

8. Assumes that t

RCD

· t

RCD

(MAX).

9. If

CAS

is LOW at the falling edge of

RAS

, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data

output buffer,

CAS

and

RAS

must be pulsed for t

10. Operation with the t

RCD

(MAX) limit ensures that t

RAC

(MAX) can be met. t

RCD

(MAX) is specified as a reference point only; if t

RCD

greater than the specified t

RCD

(MAX) limit, access time is controlled exclusively by t

CAC

11. Operation within the t

RAD

(MAX) limit ensures that t

RCD

(MAX) can be met. t

RAD

(MAX) is specified as a reference point only; if t

RAD

greater than the specified t

RAD

(MAX) limit, access time is controlled exclusively by t

12. Either t

RCH

or t

RRH

must be satisfied for a READ cycle.

13. t

OFF

(MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to V

or V

14. t

WCS

, t

RWD

, t

AWD

and t

CWD

are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If t

WCS

· t

WCS

(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If t

RWD

· t

RWD

(MIN),

AWD

· t

AWD

(MIN) and t

CWD

· t

CWD

(MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected

cell. If neither of the above conditions is met, the state of I/O (at access time and until

CAS

and

RAS

go back to V

) is

indeterminate.

held HIGH and

taken LOW after

CAS

goes LOW result in a LATE WRITE (

-controlled) cycle.

15. Output parameter (I/O) is referenced to corresponding

CAS

input, I/O0-I/O7 by

LCAS

and I/O8-I/O15 by

UCAS

16. During a READ cycle, if

is LOW then taken HIGH before

CAS

goes HIGH, I/O goes open. If

is tied permanently LOW, a LATE

WRITE or READ-MODIFY-WRITE is not possible.

17. Write command is defined as

going low.

18. LATE WRITE and READ-MODIFY-WRITE cycles must have both t

and t

OEH

met (

HIGH during WRITE cycle) in order to ensure

that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if

CAS

remains LOW and

is taken back to LOW after t

OEH

is met.

19. The I/Os are in open during READ cycles once t

or t

OFF

occur.

20. The first

CAS

edge to transition LOW.

21. The last

CAS

edge to transition HIGH.

22. These parameters are referenced to

CAS

leading edge in EARLY WRITE cycles and

leading edge in LATE WRITE or READ-

MODIFY-WRITE cycles.

23. Last falling

CAS

edge to first rising

CAS

edge.

24. Last rising

CAS

edge to next cycle's last rising

CAS

edge.

25. Last rising

CAS

edge to first falling

CAS

edge.

26. Each

CAS

must meet minimum pulse width.

27. Last

CAS

to go LOW.

28. I/Os controlled, regardless

UCAS

and

LCAS

29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.

AC TEST CONDITIONS

Output load: Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)

One TTL Load and 50 pF (Vcc = 3.3V ±10%)

Input timing reference levels: V

= 2.4V, V

= 0.8V (Vcc = 5.0V ±10%);

= 2.0V, V

= 0.8V (Vcc = 3.3V ±10%)

Output timing reference levels: V

= 2.0V, V

= 0.8V (Vcc = 5V ±10%, 3.3V ±10%)

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ISSI

EDO-PAGE-MODE READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY WRITE Cycles)

Note:
1. t

can be measured from falling edge of

CAS

to falling edge of

CAS

, or from rising edge of

CAS

to rising edge of

CAS

. Both

measurements must meet the t

specifications.

Don't Care

Undefined

RASP

ADDRESS

UCAS/LCAS

RAS

Row

CRP

RCD

CSH

CAH

CAS,

CLCH

RAL

RSH

RAH

RAD

ASR

Column

CAH

Column

ASC

CAS,

CLCH

CAS,

CLCH

I/O

ASC

RWD

RCS

CWL

AWD

CWD

CAC

CLZ

AWD

CWD

CWL

AWD

CWD

CWL

RWL

Open

OUT

OEH

CPA

CAC

CLZ

OUT

CAC

CLZ

OUT

CPA

RAC

/ t

PRWC

(1)

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