Integrated Silicon Solution, Inc. -- 1-800-379-4774
1
Rev. 00A
10/07/04
ISSI
Copyright 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
FEATURES
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Burst sequence control using MODE input
Three chip enable option for simple depth
expansion and address pipelining
Common data inputs and data outputs
Auto Power-down during deselect
Single cycle deselect
Snooze MODE for reduced-power standby
Power Supply
LPS: V
DD
3.3V + 5%, V
DDQ
3.3V/2.5V + 5%
VPS: V
DD
2.5V + 5%, V
DDQ
2.5V + 5%
JEDEC 100-Pin TQFP, 119-ball PBGA, and
165-ball PBGA packages
Automotive temperature available
Lead Free available
DESCRIPTION
The
ISSI
IS61(64)LPS12832A, IS61(64)LPS/VPS12836A
and IS61(64)LPS/VPS25618A are high-speed, low-power
synchronous static RAMs designed to provide burstable,
high-performance memory for communication and network-
ing applications. The IS61(64)LPS12832A is organized as
131,072 words by 32 bits. The IS61(64)LPS/VPS12836A
is organized as 131,072 words by 36 bits. The IS61(64)LPS/
VPS25618A is organized as 262,144 words by 18 bits.
Fabricated with
ISSI
's advanced CMOS technology, the
device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single mono-
lithic circuit. All synchronous inputs pass through regis-
ters controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (
BWE
) input combined with one or more
individual byte write signals (
BWx
). In addition, Global
Write (
GW
) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
128K x 32, 128K x 36, 256K x 18
4 Mb SYNCHRONOUS PIPELINED,
SINGLE CYCLE DESELECT STATIC RAM
PRELIMINARY INFORMATION
FEBRUARY 2005
FAST ACCESS TIME
Symbol
Parameter
250
200
Units
t
KQ
Clock Access Time
2.6
3.1
ns
t
KC
Cycle Time
4
5
ns
Frequency
250
200
MHz
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
BLOCK DIAGRAM
17/18
BINARY
COUNTER
GW
CLR
CE
CLK
Q0
Q1
MODE
A0'
A0
A1
A1'
CLK
ADV
ADSC
ADSP
15/16
17/18
ADDRESS
REGISTER
CE
D
CLK
Q
DQ(a-d)
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
CE
D
CLK
Q
ENABLE
DELAY
REGISTER
D
CLK
Q
BWE
BW(a-d)
x18: a,b
x32/x36: a-d
CE
CE2
CE2
128Kx32;
128Kx36;
256Kx18
MEMORY ARRAY
32, 36,
or 18
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
OE
2/4/8
OE
DQa - DQd
32, 36,
or 18
32, 36,
or 18
A
Integrated Silicon Solution, Inc. -- 1-800-379-4774
3
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
BOTTOM VIEW
BOTTOM VIEW
165-PIN BGA
165-Ball, 13x15 mm BGA
1mm Ball Pitch, 11x15 Ball Array
119-PIN BGA
119-Ball, 14x22 mm BGA
1mm Ball Pitch, 7x17 Ball Array
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
119 BGA PACKAGE PIN CONFIGURATION
128K
X
36
(TOP VIEW)
PIN DESCRIPTIONS
1
2
3
4
5
6
7
A
V
DDQ
A
A
ADSP
A
A
V
DDQ
B
NC
CE2
A
ADSC
A
CE2
NC
C
NC
A
A
V
DD
A
A
NC
D
DQc
DQPc
Vss
NC
Vss
DQPb
DQb
E
DQc
DQc
Vss
CE
Vss
DQb
DQb
F
V
DDQ
DQc
Vss
OE
Vss
DQb
V
DDQ
G
DQc
DQc
BWc
ADV
BWb
DQb
DQb
H
DQc
DQc
Vss
GW
Vss
DQb
DQb
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
K
DQd
DQd
Vss
CLK
Vss
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
V
DDQ
DQd
Vss
BWE
Vss
DQa
V
DDQ
N
DQd
DQd
Vss
A
1
*
Vss
DQa
DQa
P
DQd
DQPd
Vss
A
0
*
Vss
DQPa
DQa
R
NC
A
MODE
V
DD
NC
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
V
DDQ
NC
NC
NC
NC
NC
V
DDQ
Symbol
Pin Name
A
Address Inputs
A0, A1
Synchronous Burst Address Inputs
ADV
Synchronous Burst Address
Advance
ADSP
Address Status Processor
ADSC
Address Status Controller
GW
Global Write Enable
CLK
Synchronous Clock
CE
, CE2,
CE2
Synchronous Chip Select
BW
x (x=a-d)
Synchronous Byte Write Controls
BWE
Byte Write Enable
Symbol
Pin Name
OE
Output Enable
ZZ
Power Sleep Mode
MODE
Burst Sequence Selection
NC
No Connect
DQa-DQd
Data Inputs/Outputs
DQPa-Pd
Output Power Supply
V
DD
Power Supply
V
DDQ
Output Power Supply
Vss
Ground
Note: * A
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
5
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
119 BGA PACKAGE PIN CONFIGURATION
256K
X
18
(TOP VIEW)
PIN DESCRIPTIONS
Note: * A
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
1
2
3
4
5
6
7
A
V
DDQ
A
A
ADSP
A
A
V
DDQ
B
NC
CE2
A
ADSC
A
CE2
NC
C
NC
A
A
V
DD
A
A
NC
D
DQb
NC
Vss
NC
Vss
DQPa
NC
E
NC
DQb
Vss
CE
Vss
NC
DQa
F
V
DDQ
NC
Vss
OE
Vss
DQa
V
DDQ
G
NC
DQb
BWb
ADV
Vss
NC
DQa
H
DQb
NC
Vss
GW
Vss
DQa
NC
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
K
NC
DQb
Vss
CLK
Vss
NC
DQa
L
DQb
NC
Vss
NC
BWa
DQa
NC
M
V
DDQ
DQb
Vss
BWE
Vss
NC
V
DDQ
N
DQb
NC
Vss
A
1
*
Vss
DQa
NC
P
NC
DQPb
Vss
A
0
*
Vss
NC
DQa
R
NC
A
MODE
V
DD
NC
A
NC
T
NC
A
A
NC
A
A
ZZ
U
V
DDQ
NC
NC
NC
NC
NC
V
DDQ
Symbol
Pin Name
A
Address Inputs
A0, A1
Synchronous Burst Address Inputs
ADV
Synchronous Burst Address
Advance
ADSP
Address Status Processor
ADSC
Address Status Controller
GW
Global Write Enable
CLK
Synchronous Clock
CE
, CE2,
CE2
Synchronous Chip Select
BW
x (x=a,b)
Synchronous Byte Write Controls
BWE
Byte Write Enable
Symbol
Pin Name
OE
Output Enable
ZZ
Power Sleep Mode
MODE
Burst Sequence Selection
NC
No Connect
DQa-DQb
Data Inputs/Outputs
DQPa-Pb
Output Power Supply
V
DD
Power Supply
V
DDQ
Output Power Supply
Vss
Ground
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
PIN DESCRIPTIONS
165 PBGA PACKAGE PIN CONFIGURATION
128K
X
36 (TOP VIEW)
Note: * A
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE
BWc
BWb
CE2
BWE
ADSC
ADV
A
NC
B
NC
A
CE2
BWd
BWa
CLK
GW
OE
ADSP
A
NC
C
DQPc
NC
V
DDQ
Vss
Vss
Vss
Vss
Vss
V
DDQ
NC
DQPb
D
DQc
DQc
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQb
DQb
E
DQc
DQc
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQb
DQb
F
DQc
DQc
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQb
DQb
G
DQc
DQc
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQb
DQb
H
NC
NC
NC
V
DD
Vss
Vss
Vss
V
DD
NC
NC
ZZ
J
DQd
DQd
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQa
DQa
K
DQd
DQd
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQa
DQa
L
DQd
DQd
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQa
DQa
M
DQd
DQd
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQa
DQa
N
DQPd
NC
V
DDQ
Vss
NC
NC
NC
Vss
V
DDQ
NC DQPa
P
NC
NC
A
A
NC
A
1
*
NC
A
A
A
NC
R
MODE
NC
A
A
NC
A
0
*
NC
A
A
A
A
Symbol
Pin Name
A
Address Inputs
A0, A1
Synchronous Burst Address Inputs
ADV
Synchronous Burst Address
Advance
ADSP
Address Status Processor
ADSC
Address Status Controller
GW
Global Write Enable
CLK
Synchronous Clock
CE
,
CE2
,
CE2
Synchronous Chip Select
BW
x (x=a,b,c,d) Synchronous Byte Write
Controls
Symbol
Pin Name
BWE
Byte Write Enable
OE
Output Enable
ZZ
Power Sleep Mode
MODE
Burst Sequence Selection
NC
No Connect
DQx
Data Inputs/Outputs
DQPx
Data Inputs/Outputs
V
DD
3.3V/2.5V Power Supply
V
DDQ
Isolated Output Power Supply
3.3V
/2.5V
Vss
Ground
Integrated Silicon Solution, Inc. -- 1-800-379-4774
7
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
Note: * A
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
165 PBGA PACKAGE PIN CONFIGURATION
256K
X
18 (TOP VIEW)
PIN DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE
BWb
NC
CE2
BWE
ADSC
ADV
A
A
B
NC
A
CE2
NC
BWa
CLK
GW
OE
ADSP
A
NC
C
NC
NC
V
DDQ
Vss
Vss
Vss
Vss
Vss
V
DDQ
NC
DQPa
D
NC
DQb
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
NC
DQa
E
NC
DQb
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
NC
DQa
F
NC
DQb
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
NC
DQa
G
NC
DQb
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
NC
DQa
H
NC
NC
NC
V
DD
Vss
Vss
Vss
V
DD
NC
NC
ZZ
J
DQb
NC
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQa
NC
K
DQb
NC
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQa
NC
L
DQb
NC
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQa
NC
M
DQb
NC
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQa
NC
N
DQPb
NC
V
DDQ
Vss
NC
NC
NC
Vss
V
DDQ
NC
NC
P
NC
NC
A
A
NC
A
1
*
NC
A
A
A
NC
R
MODE
NC
A
A
NC
A
0
*
NC
A
A
A
A
Symbol
Pin Name
A
Address Inputs
A0, A1
Synchronous Burst Address Inputs
ADV
Synchronous Burst Address
Advance
ADSP
Address Status Processor
ADSC
Address Status Controller
GW
Global Write Enable
CLK
Synchronous Clock
CE
,
CE2
,
CE2
Synchronous Chip Select
BW
x (x=a,b)
Synchronous Byte Write
Controls
Symbol
Pin Name
BWE
Byte Write Enable
OE
Output Enable
ZZ
Power Sleep Mode
MODE
Burst Sequence Selection
NC
No Connect
DQx
Data Inputs/Outputs
DQPx
Data Inputs/Outputs
V
DD
3.3V/2.5V Power Supply
V
DDQ
Isolated Output Power Supply
3.3V/2.5V
Vss
Ground
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
46 47 48 49 50
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A
Synchronous Address Inputs
ADSC
Synchronous Controller Address
Status
ADSP
Synchronous Processor Address
Status
ADV
Synchronous Burst Address Advance
BWa
-
BWd
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
CE
,
CE2
,
CE2 Synchronous Chip Enable
CLK
Synchronous Clock
DQa-DQd
Synchronous Data Input/Output
DQPa-DQPd
Parity Data Input/Output
GW
Synchronous Global Write Enable
MODE
Burst Sequence Mode Selection
OE
Output Enable
V
DD
3.3V/2.5V Power Supply
V
DDQ
Isolated Output Buffer Supply:
3.3V/2.5V
Vss
Ground
ZZ
Snooze Enable
PIN CONFIGURATION
(3 Chip-Enable option)
100-PIN TQFP (128K X 32)
100-PIN TQFP (128K X 36)
(3 Chip-Enable option)
NC
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
NC
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
46 47 48 49 50
Integrated Silicon Solution, Inc. -- 1-800-379-4774
9
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
PIN CONFIGURATION
(3 Chip-Enable Option)
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A
Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
Synchronous Processor Address Status
ADV
Synchronous Burst Address Advance
BWa
-
BWb
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
CE
, CE2,
CE2
Synchronous Chip Enable
CLK
Synchronous Clock
DQa-DQb
Synchronous Data Input/Output
DQPa-DQPb
Parity Data I/O; DQPa is parity for
DQa1-8; DQPb is parity for DQb1-8
GW
Synchronous Global Write Enable
MODE
Burst Sequence Mode Selection
OE
Output Enable
V
DD
3.3V/2.5V Power Supply
V
DDQ
Isolated Output Buffer Supply:
3.3V/2.5V
Vss
Ground
ZZ
Snooze Enable
100-PIN TQFP (256K X 18)
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
CE
CE2
NC
NC
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
46 47 48 49 50
10
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
PARTIAL TRUTH TABLE
Function
GW
GW
GW
GW
GW
BWE
BWE
BWE
BWE
BWE
BWa
BWa
BWa
BWa
BWa
BWb
BWb
BWb
BWb
BWb
BWc
BWc
BWc
BWc
BWc
BWd
BWd
BWd
BWd
BWd
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte 1
H
L
L
H
H
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
TRUTH TABLE
(1-8)
OPERATION
ADDRESS
CE
CE
CE
CE
CE CE2
CE2
CE2
CE2
CE2
CE2
ZZ
ADSP
ADSP
ADSP
ADSP
ADSP
ADSC
ADSC
ADSC
ADSC
ADSC ADV
ADV
ADV
ADV
ADV
WRITE
WRITE
WRITE
WRITE
WRITE OE
OE
OE
OE
OE
CLK
DQ
Deselect Cycle, Power-Down
None
H
X
X
L
X
L
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
X
L
L
L
X
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
H
X
L
L
X
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
X
L
L
H
L
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
H
X
L
H
L
X
X
X
L-H
High-Z
Snooze Mode, Power-Down
None
X
X
X
H
X
X
X
X
X
X
High-Z
Read Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
H
L-H
High-Z
Write Cycle, Begin Burst
External
L
L
H
L
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
High-Z
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
High-Z
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
High-Z
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
NOTE:
1. X means "Don't Care." H means logic HIGH. L means logic LOW.
2. For
WRITE
, L means one or more byte write enable signals (
BWa-d
) and
BWE
are LOW or
GW
is LOW.
WRITE
= H for all
BWx
,
BWE
,
GW
HIGH.
3.
BWa
enables WRITEs to DQa's and DQPa.
BWb
enables WRITEs to DQb's and DQPb.
BWc
enables WRITEs to DQc's and
DQPc.
BWd
enables WRITEs to DQd's and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are
available on the x36 version.
4. All inputs except
OE
and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation,
OE
must be HIGH before the input data setup time and held HIGH during the
input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8.
ADSP
LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and
BWE
LOW or
GW
LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
11
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
INTERLEAVED BURST ADDRESS TABLE (MODE = V
DD
or No Connect)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A1 A0
A1 A0
A1 A0
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
1,0
0,1
A1', A0' = 1,1
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
T
STG
Storage Temperature
55 to +150
C
P
D
Power Dissipation
1.6
W
I
OUT
Output Current (per I/O)
100
mA
V
IN
, V
OUT
Voltage Relative to Vss for I/O Pins
0.5 to V
DDQ
+ 0.5
V
V
IN
Voltage Relative to Vss for
0.5 to V
DD
+ 0.5
V
for Address and Control Inputs
V
DD
Voltage on V
DD
Supply Relative to Vss
0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or
electric fields; however, precautions may be taken to avoid application of any voltage higher than
maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
12
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
OPERATING RANGE (IS61/64LPSXXXXX)
Range
Ambient Temperature
V
DD
V
DDQ
Commercial
0C to +70C
3.3V + 5%
3.3V / 2.5V + 5%
Industrial
40C to +85C
3.3V + 5%
3.3V / 2.5V + 5%
Automotive
40C to +125C
3.3V + 5%
3.3V / 2.5V + 5%
OPERATING RANGE (IS61/64VPSXXXXX)
Range
Ambient Temperature
V
DD
V
DDQ
Commercial
0C to +70C
2.5V + 5%
2.5V + 5%
Industrial
40C to +85C
2.5V + 5%
2.5V + 5%
Automotive
40C to +125C
2.5V + 5%
2.5V + 5%
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
3.3V
2.5V
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
I
OH
= 4.0 mA (3.3V)
2.4
--
2.0
--
V
I
OH
= 1.0 mA (2.5V)
V
OL
Output LOW Voltage
I
OL
= 8.0 mA (3.3V)
--
0.4
--
0.4
V
I
OL
= 1.0 mA (2.5V)
V
IH
Input HIGH Voltage
2.0
V
DD
+ 0.3
1.7
V
DD
+ 0.3
V
V
IL
Input LOW Voltage
-0.3
0.8
-0.3
0.7
V
I
LI
Input Leakage Current
Vss
V
IN
V
DD
(1)
-5
5
-5
5
A
I
LO
Output Leakage Current Vss
V
OUT
V
DDQ
,
-5
5
-5
5
A
OE
= V
IH
Integrated Silicon Solution, Inc. -- 1-800-379-4774
13
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-250
-200
MAX
MAX
Symbol Parameter
Test Conditions
Temp. range
x18
x32/x36
x18
x32/x36
Unit
I
CC
AC Operating
Device Selected,
Com.
225
225
200
200
mA
Supply Current
OE
= V
IH
, ZZ
V
IL
,
Ind.
250
250
210
210
All Inputs
0.2V or
Auto.
275
275
225
225
V
DD
0.2V,
Cycle Time
t
KC
min.
I
SB
Standby Current
Device Deselected,
Com.
90
90
90
90
mA
TTL Input
V
DD
= Max.,
Ind.
100
100
100
100
All Inputs
V
IL
or
V
IH
,
Auto.
120
120
120
120
ZZ
V
IL
, f = Max.
I
SBI
Standby Current
Device Deselected,
Com.
70
70
70
70
mA
CMOS Input
V
DD
= Max.,
Ind.
75
75
75
75
V
IN
V
SS
+ 0.2V or
Auto.
90
90
90
90
V
DD
0.2V
typ.
(2)
40
40
f = 0
I
SB
2
Sleep Mode
ZZ>V
IH
Com.
30
30
30
30
mA
Ind.
35
35
35
35
Auto.
45
45
45
45
typ.
(2)
25
25
Note:
1. MODE pin has an internal pullup and should be tied to V
DD
or V
SS
. It exhibits 100A maximum leakage current when tied to
V
SS
+ 0.2V or
V
DD
0.2V.
2. Typical values are measured at V
DD
= 3.3V, T
A
= 25
o
C and not 100% tested.
14
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Input/Output Capacitance
V
OUT
= 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz, V
DD
= 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
1.5 ns
Input and Output Timing
1.5V
and Reference Level
Output Load
See Figures 1 and 2
AC TEST LOADS
Figure 2
317
5 pF
Including
jig and
scope
351
OUTPUT
3.3V
Figure 1
Output
Z
O
= 50
1.5V
50
Integrated Silicon Solution, Inc. -- 1-800-379-4774
15
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
2.5V I/O AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 2.5V
Input Rise and Fall Times
1.5 ns
Input and Output Timing
1.25V
and Reference Level
Output Load
See Figures 3 and 4
2.5 I/O OUTPUT LOAD EQUIVALENT
Figure 4
1,667
5 pF
Including
jig and
scope
1,538
OUTPUT
2.5V
Figure 3
Output
Z
O
= 50
1.25V
50
16
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-250
-200
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
f
MAX
Clock Frequency
--
250
--
200
MHz
t
KC
Cycle Time
4.0
--
5
--
ns
t
KH
Clock High Time
1.7
--
2
--
ns
t
KL
Clock Low Time
1.7
--
2
--
ns
t
KQ
Clock Access Time
--
2.6
--
3.1
ns
t
KQX
(2)
Clock High to Output Invalid
0.8
--
1.5
--
ns
t
KQLZ
(2,3)
Clock High to Output Low-Z
0.8
--
1
--
ns
t
KQHZ
(2,3)
Clock High to Output High-Z
--
2.6
--
3.0
ns
t
OEQ
Output Enable to Output Valid
--
2.8
--
3.1
ns
t
OELZ
(2,3)
Output Enable to Output Low-Z
0
--
0
--
ns
t
OEHZ
(2,3)
Output Disable to Output High-Z
--
2.6
--
3.0
ns
t
AS
Address Setup Time
1.2
--
1.4
--
ns
t
WS
Read/Write Setup Time
1.2
--
1.4
--
ns
t
CES
Chip Enable Setup Time
1.2
--
1.4
--
ns
t
AVS
Address Advance Setup Time
1.2
--
1.4
--
ns
t
DS
Data Setup Time
1.2
--
1.4
--
ns
t
AH
Address Hold Time
0.3
--
0.4
--
ns
t
WH
Write Hold Time
0.3
--
0.4
--
ns
t
CEH
Chip Enable Hold Time
0.3
--
0.4
--
ns
t
AVH
Address Advance Hold Time
0.3
--
0.4
--
ns
t
DH
Data Hold Time
0.3
--
0.4
--
ns
t
PDS
ZZ High to Power Down
--
2
--
2
cyc
t
PUS
ZZ Low to Power Down
--
2
--
2
cyc
Note:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
17
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
READ/WRITE CYCLE TIMING
Single Read
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BWx
BWE
GW
Address
ADV
ADSC
ADSP
CLK
RD1
RD2
1a
2c
2d
Unselected
Burst Read
t
KQX
t
KC
t
KL
t
KH
t
SS
t
SH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
RD3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
t
OEQ
t
OEQX
t
OELZ
t
KQLZ
t
KQ
t
OEHZ
t
KQHZ
ADSC initiate read
ADSP is blocked by CE inactive
t
AVH
t
AVS
Suspend Burst
Pipelined Read
2a
2b
18
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
WRITE CYCLE TIMING
Single Write
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BWx
BWE
GW
Address
ADV
ADSC
ADSP
CLK
WR1
WR2
Unselected
Burst Write
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
WR3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
ADSC initiate Write
ADSP is blocked by CE inactive
t
AVH
t
AVS
ADV must be inactive for ADSP Write
WR1
WR2
t
WS
t
WH
WR3
t
WS
t
WH
High-Z
High-Z
1a
3a
t
DS
t
DH
BW4-BW1 only are applied to first cycle of WR2
Write
2c
2d
2a
2b
Integrated Silicon Solution, Inc. -- 1-800-379-4774
19
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
SNOOZE MODE TIMING
Don't Care
Deselect or Read Only
Deselect or Read Only
t
RZZI
CLK
ZZ
Isupply
All Inputs
(except ZZ)
Outputs
(Q)
I
SB2
ZZ setup cycle
ZZ recovery cycle
Normal
operation
cycle
t
PDS
t
PUS
t
ZZI
High-Z
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
Max.
Unit
I
SB
2
Current during SNOOZE MODE
ZZ
Vih
--
60
mA
t
PDS
ZZ active to input ignored
--
2
cycle
t
PUS
ZZ inactive to input sampled
2
--
cycle
t
ZZI
ZZ active to SNOOZE current
--
2
cycle
t
RZZI
ZZ inactive to exit SNOOZE current
0
--
ns
20
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
ORDERING INFORMATION (3.3V core/2.5V-3.3V I/O)
Commercial Range: 0C to +70C
Configuration
Frequency
Order Part Number
Package
128Kx32
250
IS61LPS12832A-250TQ
100 TQFP
IS61LPS12832A-250B2
119 PBGA
IS61LPS12832A-250B3
165 PBGA
200
IS61LPS12832A-200TQ
100 TQFP
IS61LPS12832A-200B2
119 PBGA
IS61LPS12832A-200B3
165 PBGA
128Kx36
250
IS61LPS12836A-250TQ
100 TQFP
IS61LPS12836A-250B2
119 PBGA
IS61LPS12836A-250B3
165 PBGA
200
IS61LPS12836A-200TQ
100 TQFP
IS61LPS12836A-200B2
119 PBGA
IS61LPS12836A-200B3
165 PBGA
256Kx18
250
IS61LPS25618A-250TQ
100 TQFP
IS61LPS25618A-250B2
119 PBGA
IS61LPS25618A-250B3
165 PBGA
200
IS61LPS25618A-200TQ
100 TQFP
IS61LPS25618A-200B2
119 PBGA
IS61LPS25618A-200B3
165 PBGA
Integrated Silicon Solution, Inc. -- 1-800-379-4774
21
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
ORDERING INFORMATION (3.3V core/2.5V-3.3V I/O)
Industrial Range: -40C to +85C
Configuration
Frequency
Order Part Number
Package
128Kx32
250
IS61LPS12832A-250TQI
100 TQFP
IS61LPS12832A-250B2I
119 PBGA
IS61LPS12832A-250B3I
165 PBGA
200
IS61LPS12832A-200TQI
100 TQFP
IS61LPS12832A-200TQLI
100 TQFP, Lead-free
IS61LPS12832A-200B2I
119 PBGA
IS61LPS12832A-200B3I
165 PBGA
128Kx36
250
IS61LPS12836A-250TQI
100 TQFP
IS61LPS12836A-250B2I
119 PBGA
IS61LPS12836A-250B3I
165 PBGA
200
IS61LPS12836A-200TQI
100 TQFP
IS61LPS12836A-200TQLI
100 TQFP, Lead-free
IS61LPS12836A-200B2I
119 PBGA
IS61LPS12836A-200B3I
165 PBGA
256Kx18
250
IS61LPS25618A-250TQI
100 TQFP
IS61LPS25618A-250B2I
119 PBGA
IS61LPS25618A-250B3I
165 PBGA
200
IS61LPS25618A-200TQI
100 TQFP
IS61LPS25618A-200TQLI
100 TQFP, Lead-free
IS61LPS25618A-200B2I
119 PBGA
IS61LPS25618A-200B3I
165 PBGA
Automotive Range: -40C to +125C
Configuration
Frequency
Order Part Number
Package
128Kx32
200
IS64LPS12832A-200TQA3
100 TQFP
128Kx36
200
IS64LPS12836A-200TQA3
100 TQFP
256Kx18
200
IS64LPS25618A-200TQA3
100 TQFP
22
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
ORDERING INFORMATION (2.5V core/2.5V I/O)
Commercial Range: 0C to +70C
Configuration
Frequency
Order Part Number
Package
128Kx36
250
IS61VPS12836A-250TQ
100 TQFP
IS61VPS12836A-250B2
119 PBGA
IS61VPS12836A-250B3
165 PBGA
200
IS61VPS12836A-200TQ
100 TQFP
IS61VPS12836A-200B2
119 PBGA
IS61VPS12836A-200B3
165 PBGA
256Kx18
250
IS61VPS25618A-250TQ
100 TQFP
IS61VPS25618A-250B2
119 PBGA
IS61VPS25618A-250B3
165 PBGA
200
IS61VPS25618A-200TQ
100 TQFP
IS61VPS25618A-200B2
119 PBGA
IS61VPS25618A-200B3
165 PBGA
Integrated Silicon Solution, Inc. -- 1-800-379-4774
23
Rev. 00A
10/07/04
ISSI
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
Industrial Range: -40C to +85C
Configuration
Frequency
Order Part Number
Package
128Kx36
250
IS61VPS12836A-250TQI
100 TQFP
IS61VPS12836A-250B2I
119 PBGA
IS61VPS12836A-250B3I
165 PBGA
200
IS61VPS12836A-200TQI
100 TQFP
IS61VPS12836A-200B2I
119 PBGA
IS61VPS12836A-200B3I
165 PBGA
256Kx18
250
IS61VPS25618A-250TQI
100 TQFP
IS61VPS25618A-250B2I
119 PBGA
IS61VPS25618A-250B3I
165 PBGA
200
IS61VPS25618A-200TQI
100 TQFP
IS61VPS25618A-200B2I
119 PBGA
IS61VPS25618A-200B3I
165 PBGA
Automotive Range: -40C to +125C
Configuration
Frequency
Order Part Number
Package
128Kx32
200
IS64VPS12832A-200TQA3
100 TQFP
128Kx36
200
IS64VPS12836A-200TQA3
100 TQFP
256Kx18
200
IS64VPS25618A-200TQA3
100 TQFP
PACKAGING INFORMATION
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. B
02/12/03
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Plastic Ball Grid Array
Package Code: B (119-pin)
Notes:
1. Controlling dimension: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include mold flash protrusion and
should be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within
0.004 inches at the seating plane.
MILLIMETERS
INCHES
Sym.
Min.
Max.
Min.
Max.
N0.
Leads
119
A
--
2.41
--
0.095
A1
0.50
0.70
0.020
0.028
A2
0.80
1.00
0.032
0.039
A3
1.30
1.70
0.051
0.067
A4
0.56 BSC
0.022 BSC
b
0.60
0.90
0.024
0.035
D
21.80
22.20
0.858
0.874
D1
20.32 BSC
0.800 BSC
D2
19.40
19.60
0.764
0.772
E
13.80
14.20
0.543
0.559
E1
7.62 BSC
0.300 BSC
E2
11.90
12.10
0.469
0.476
e
1.27 BSC
0.050 BSC
E1
A1
D1
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
E2
E
A2
SEATING PLANE
e
D2
D
A
30
A3
A4
b (119X)
PACKAGING INFORMATION
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. A
06/11/03
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
11 10 9 8 7 6 5 4 3 2 1
A1 CORNER
BOTTOM VIEW
D D1
e
e
E1
E
1 2 3 4 5 6 7 8 9 10 11
A1 CORNER
TOP VIEW
A2
A
A1
b (165X)
Ball Grid Array
Package Code: B (165-pin)
Notes:
1. Controlling dimensions are in millimeters.
BGA - 13mm x 15mm
MILLIMETERS
INCHES
Sym.
Min.
Nom.
Max.
Min.
Nom.
Max.
N0.
Leads
165
165
A
--
--
1.20
--
--
0.047
A1
0.25
0.33
0.40
0.010
0.013
0.016
A2
--
0.79
--
--
0.031
--
D
14.90
15.00
15.10
0.587
0.591
0.594
D1
13.90
14.00
14.10
0.547
0.551
0.555
E
12.90
13.00
13.10
0.508
0.512
0.516
E1
9.90
10.00
10.10
0.390
0.394
0.398
e
--
1.00
--
--
0.039
--
b
0.40
0.45
0.50
0.016
0.018
0.020
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PACKAGING INFORMATION
ISSI
PK13197LQ Rev. D 05/08/03
TQFP (Thin Quad Flat Pack Package)
Package Code: TQ
Thin Quad Flat Pack (TQ)
Millimeters
Inches
Millimeters
Inches
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Ref. Std.
No. Leads (N)
100
128
A
--
1.60
--
0.063
--
1.60
--
0.063
A1
0.05
0.15
0.002
0.006
0.05
0.15
0.002
0.006
A2
1.35
1.45
0.053
0.057
1.35
1.45
0.053
0.057
b
0.22
0.38
0.009
0.015
0.17
0.27
0.007
0.011
D
21.90
22.10
0.862
0.870
21.80
22.20
0.858
0.874
D1
19.90
20.10
0.783
0.791
19.90
20.10
0.783
0.791
E
15.90
16.10
0.626
0.634
15.80
16.20
0.622
0.638
E1
13.90
14.10
0.547
0.555
13.90
14.10
0.547
0.555
e
0.65 BSC
0.026 BSC
0.50 BSC
0.020 BSC
L
0.45
0.75
0.018
0.030
0.45
0.75
0.018
0.030
L1
1.00 REF.
0.039 REF.
1.00 REF.
0.039 REF.
C
0
o
7
o
0
o
7
o
0
o
7
o
0
o
7
o
Notes:
1. All dimensioning and
tolerancing conforms to
ANSI Y14.5M-1982.
2. Dimensions D1 and E1 do
not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.
3. Controlling dimension:
millimeters.
D
D1
E
E1
1
N
A2
A
A1
e
b
SEATING
PLANE
C
L1
L
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