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IS61LSCS25672
IS61LSCS51236

ISSI

Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.

Bottom View

209-Ball, 14 mm x 22 mm BGA

1 mm Ball Pitch, 11 x 19 Ball Array

SIGMARAM FAMILY OVERVIEW

The IS61LSCS series

RAMs are built in compliance with

the SigmaRAM pinout standard for synchronous SRAMs.
The implementations are 18,874,368-bit (18Mb) SRAMs.
These are the first in a family of wide, very low voltage CMOS
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking
systems.

ISSI

RAMs are offered in a number of configurations that

emulate other synchronous SRAMs, such as Burst RAMs,
NBT RAMs, Late Write, or Double Data Rate (DDR) SRAMs.
The logical differences between the protocols employed by
these RAMs hinge mainly on various combinations of
address bursting, output data registering and write cueing.

RAMs allow a user to implement the interface protocol best

suited to the task at hand.

This specific product is Common I/O, SDR, Pipelined, and
in the family is identified as 1x1Lp.

ADVANCE INFORMATION

NOVEMBER 2002

RAM 256K X 72, 512K X 36

18MB SYNCHRONOUS SRAM

FEATURES

· JEDEC SigmaRam pinout and package standard

· Single 1.8V power supply (V

): 1.7V (min)

to 1.9V (max)

· Dedicated output supply voltage (V

DDQ

): 1.8V

or 1.5V typical

· LVCMOS-compatible I/O interface

· Common data I/O pins (DQs)

· Single Data Rate (SDR) data transfers

· Late Write Pipelined (PL) read operations

· Burst and non-burst read and write operations,

selectable via dedicated control pin (ADV)

· Internally controlled Linear Burst address

sequencing during burst operations

· Burst length of 2, 3, or 4, with automatic address

wrap

· Full read/write coherency

· Byte write capability

· Two cycle deselect

· Single-ended input clock (CLK)

· Data-referenced output clocks (CQ/,

)

· Selectable output driver impedance via dedicated

control pin (ZQ)

· Echo clock outputs track data output drivers

· Depth expansion capability (2 or 4 banks) via

programmable chip enables (E2, E3, EP2, EP3)

· JTAG boundary scan (subset of IEEE standard

1149.1)

· 209 Ball (11x19), 1mm pitch, 14mm x 22mm Ball

Grid Array (BGA) package

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FUNCTIONAL DESCRIPTION

Because SigmaRAM is a synchronous device, address,
data Inputs, and read/write control inputs are captured on
the rising edge of the input clock. Write cycles are
internally self-timed and initiated by the rising edge of the
clock input. This feature eliminates complex off-chip write
pulse generation required by asynchronous SRAMs and
simplifies input signal timing.

IS61LSCS25672 PINOUT

256K x 72 COMMON I/O--TOP VIEW

DQg

ADV

DQb

(16M)

(8M)

DQg

DQb

DQg

DQb

(128M)

DQg

GND

MCL

GND

DQb

DQPg

DQPc

DDQ

DQPf

DQPb

DQc

GND

DQf

DQc

DDQ

EP2

DDQ

DQf

DQc

GND

EP3

GND

DQf

DQc

DDQ

DQf

CQ2

CLK

GND

MCL

GND

CQ1

DQh

DDQ

DQa

DQh

GND

DQa

DQh

DDQ

MCH

DDQ

DQa

DQh

GND

MCL

GND

DQa

DQPd

DQPh

DDQ

DQPa

DQPe

DQd

GND

MCL

GND

DQe

DQd

DQe

(64M)

(32M)

DQd

DQe

DQd

TMS

TDI

TDO

TCK

DQe

11 x 19 Ball BGA--14 x 22 mm

Body--1 mm Ball Pitch

Single

data

rate

RAMs

incorporate

rising-edge-triggered

output

For

read

cycles,

RAM's

output

data

temporarily

stored

the

edge-triggered

output

during the

access

cycle

and

then

released

the

output

drivers

the next

rising

edge

clock.

IS61LSCS series

RAMs are implemented with ISSI's

high performance CMOS technology and are packaged in
a 209-Ball BGA.

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IS61LSCS51236 PINOUT

512K x 36 COMMON I/O--TOP VIEW

ADV

DQb

(16M)

DQb

(x36)

DQb

(128M)

GND

MCL

GND

DQb

DQPc

DDQ

DQPb

DQc

GND

DQc

DDQ

EP2

DDQ

DQc

GND

EP3

GND

DQc

DDQ

CQ2

CLK

GND

MCL

GND

CQ1

DDQ

DQa

GND

DQa

DDQ

MCH

DDQ

DQa

GND

MCL

GND

DQa

DQPd

DDQ

DQPa

DQd

GND

MCL

GND

DQd

(64M)

(32M)

DQd

TMS

TDI

TDO

TCK

11 x 19 Ball BGA--14 x 22 mm

Body--1 mm Ball Pitch

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PIN DESCRIPTION TABLE

Symbol

Pin Location

Description

Type

Comments

A3, A5, A7, A9, B7, U4,

Address

Input

U6, U8, V3, V4, V5, V6,

V7, V8, V9, W5, W6, W7

Address

Input

x36 version

ADV

Advance

Input

Active High

B3, C9

Byte Write Enable

Input

Active Low (all versions)

B8, C4

Byte Write Enable

Input

Active Low (x36 and x72 versions)

B4, B9, C3, C8

Byte Write Enable

Input

Active Low (x72 version only)

Clock

Input

Active High

K1, K11

Echo Clock

Output

Active High

K2, K10

Echo Clock

Output

Active Low

E2, F1, F2, G1, G2, H1,

Data I/O

Input/Output

x36, and x72 versions

H2, J1, J2, L10, L11,
M10, M11, N10, N11,

P10, P11, R10

A10, A11, B10, B11,

Data I/O

Input/Output

C10, C11, D10, D11,

E11, R1, T1, T2, U1, U2,

V1, V2, W1, W2

A1, A2, B1, B2, C1, C2,

Data I/O

Input/Output

x72 version only

D1, D2, E1, E10, F10,

F11, G10, G11, H10,

H11, J10, J11, L1, L2,

M1, M2, N1, N2, P1, P2,
R2, R11, T10, T11, U10,

U11, V10, V11, W10,

W11

Chip Enable

Input

Active Low

E2 & E3

A4, A8

Chip Enable

Input

Programmable Active High or Low

EP2 & EP3

G6, H6

Chip Enable Program Pin

Input

TCK

Test Clock

Input

Active High

TDI

Test Data In

Input

TDO

Test Data Out

Output

TMS

Test Mode Select

Input

M2, M3 & M4

L6, M6, J6

Mode Control Pins

Input

Must tie to High, High, Low

MCL

D6, K6, P6, T6

Must Connect Low

Input

MCH

Must Connect high

Input

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PIN DESCRIPTION TABLE

Symbol

Pin Location

Description

Type

Comments

C5, D4, D5, D7, D8, K4,

K8, K9, T4, T5, T7,

No Connect

Not connected to die (all versions)

T8, U3, U5, U7, U9

No Connect

Not connected to die (x72 version)

No Connect

Not connected to die (x72/x36 versions)

A1, A2, B1, B2, B4, B9,

C1, C2, C3, C8, D1, D2,
E1, E10, F10, F11, G10,

G11, H10, H11, J10, J11,

No Connect

Not connected to die (x36 version)

L1, L2, M1, M2, N1, N2,

P1, P2, R2, R11, T10,

T11, U10, U11, V10,

V11, W10, W11

Write

Input

Active Low

E5, E6, E7, G5, G7,

J5, J7, L5, L7, N5,

Core Power Supply

Input

1.8 V Nominal

N7, R5, R6, R7

E3, E4, E8, E9, J3, J4,

DDQ

J8, J9, L3, L4, L8,

Output Driver Power Supply

Input

1.8 V or 1.5 V Nominal

L9, N3, N4, N8, N9,

R3, R4, R8, R9
G3, G4, G8, G9

D3, D9, F3, F4, F5, F7,

F8, F9, H3, H4, H5, H7,

GND

H8, H9, K5, K7, M3, M4,

Ground

Input

M5, M7, M8, M9, P3, P4,

P5, P7, P8, P9, T3, T9

Output Impedance Control

Input

Low = Low Impedance [High Drive]

High = High Impedance [Low Drive]

Default = High

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ISSI

BACKGROUND

The central characteristics of the ISSI

RAMs are that

they are extremely fast and consume very little power.
Because both operating and interface power is low,

RAMs can be implemented in a wide (x72) configuration,

providing very high single package bandwidth (in excess
of 20 Gb/s in ordinary pipelined configuration) and very low
random access latency (~3 ns). The use of very low
voltage circuits in the core and 1.8V or 1.5V interface
voltages allow the speed, power and density performance
of

RAMs.

Although the SigmaRAM family pinouts have been de-
signed to support a number of different common read and
write protocol options, not all SigmaRAM implementa-
tions will support all possible protocols. The following
timing diagrams provide a quick comparison between

read and write protocols options available in the context
of the SigmaRAM standard. This data sheet covers the
single data rate (non-DDR), Pipelined Read SigmaRAM.

The character of the applications for fast synchronous
SRAMs in networking systems are extremely diverse.

RAMs have been developed to address the diverse

needs of the networking market in a manner that can be
supported with a unified development and manufacturing
infrastructure.

RAMs address each of the bus protocol

options commonly found in networking systems. This
allows the

RAM to find application in radical shrinks and

speed-ups of existing networking chip sets that were
designed for use with older SRAMs, like the NBT or Nt,
Late Write, or Double Data Rate SRAMs, as well as with
new chip sets and ASIC's that employ the Echo Clocks
and realize the full potential of the

RAMs.

LATE WRITE--PIPELINED READ (

1x1Lp). For reference only.

A B C D E F

R W R W R W

QA DB

QC DD

Address

Control

DOUBLE LATE WRITE--PIPELINED READ (

1x1Dp). For reference only.

A B C D E F

R X W R X W

QA DC

QD DF

Address

Control

COMMON I/O SigmaRAM FAMILY MODE COMPARISON--LATE WRITE VS. DOUBLE LATE WRITE

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READ OPERATIONS

Pipelined Read

Read operation is initiated when the following conditions
are satisfied at the rising edge of clock: All three chip
enables (

, E2, and E3) are active, the write enable input

signal (

) is deasserted high, and ADV is asserted low.

The address presented to the address inputs is latched into
the address register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the next
rising edge of clock the read data is allowed to propagate
through the output register and onto the output pins.

WRITE OPERATIONS

Write operation occurs when the following conditions are
satisfied at the rising edge of clock: All three chip enables
(

, E2, and E3) are active and the write enable input

signal (

) is asserted low.

Data is taken at the next rising edge of clock, as a Late
Write operation.

A B C D E F

R X W R X W

Address

Control

DC0

QA0 QA1

QD0 QD1

DF0

DC1

DOUBLE DATA RATE WRITE--DOUBLE DATA RATE READ (

1x2Lp). For reference only.

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SPECIAL FUNCTIONS

Burst Cycles

RAMs provide an on-chip burst address generator that

can be utilized, if desired, to further simplify burst read or
write implementations. The ADV control pin, when driven
high, commands the

RAM to advance the internal ad-

dress counter and use the counter generated address to
read or write the

RAM. The starting address for the first

cycle in a burst cycle series is loaded into the

RAM by

driving the ADV pin low, into Load mode.

Burst Order

The burst address counter wraps around to its initial state
after four addresses (the loaded address and three more)
have been accessed. SigmaRAMs always count in linear
burst order.

Linear Burst Order

A[1:0]

1st address

2nd address

3rd address

4th address

Note:

1. The burst counter wraps to initial state on the 5th rising edge

of clock.

SIGMA PIPELINED BURST READS WITH COUNTER WRAP-AROUND

CLK

Address

Read

Internal
Address

ADV

Continue

Bursting

QA2

QA3

QA0

QA1

Counter Wraps

Continue

Bursting

Continue

Bursting

Continue

Bursting

Continue

Bursting

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ECHO CLOCK CONTROL IN TWO BANKS OF SIGMA PIPELINED SRAMS

ECHO CLOCK

RAMs feature Echo Clocks, CQ1, CQ2,

CQ1

, and

CQ2

that track the performance of the output drivers. The Echo
Clocks are delayed copies of the main RAM clock, CLK.
Echo Clocks are designed to track changes in output
driver delays due to variance in die temperature and
supply voltage. The Echo Clocks are designed to fire with
the rest of the data output drivers. Sigma RAMs provide
both in-phase, or true, Echo Clock outputs (CQ1 and
CQ2) and inverted Echo Clock outputs (

CQ1

and

CQ2

It should be noted that deselection of the RAM via E2 and
E3 also deselects the Echo Clock output drivers. The
deselection of Echo Clock drivers is always pipelined to

the same degree as output data. Deselection of the RAM via

does not deactivate the Echo Clocks.

In some applications it may be appropriate to pause
between banks; to deselect both RAMs with E1 before
resuming read operations. An E1 deselect at a bank
switch will allow at least one clock to be issued from the
new bank before the first read cycle in the bank. Although
the following drawing illustrates a E1 read pause upon
switching from Bank 1 to Bank 2, a write to Bank 2 would
have the same effect, causing the RAM in Bank 2 to issue
at least one clock before it is needed.

A B C D E F

QA QC

QB QD

Read Read Read Read Read Read

CLK

Address

Bank 1

E2 Bank 2

DQ Bank 1

DQ Bank 2

CQ Bank 1

CQ Bank 2

CQ1+ CQ2

Note:

E1 does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.

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PIPELINED READ BANK SWITCH WITH E1 DESELECT

A XX C D E F

QC QD

Read No

Op Read Read Read Read

CLK

Address

Bank 1

E2 Bank 2

DQ Bank 1

DQ Bank 2

CQ Bank 1

CQ Bank 2

CQ1+ CQ2

Note:

does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.

OUTPUT DRIVER IMPEDANCE CONTROL

SigmaRAMs may be supplied with either selectable (high) impedance output drivers. The ZQ pin of SigmaRAMs supplied
with selectable impedance drivers, allows selection between

RAM nominal drive strength (ZQ low) for multi-drop bus

applications and low drive strength (ZQ floating or high) point-to-point applications. The impedance of the data and clock
output drivers in these devices can be controlled via the static input ZQ. When ZQ is tied "low", output driver impedance
is set to ~25

. When ZQ is tied "high" or left unconnected, output driver impedance is set to ~50

See the DC Electrical

Characteristics section for further information. The SRAM requires 32K cycles of power-up time after V

reaches its

operating range.

OUTPUT DRIVER CHARACTERISTICS -

TBD

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PROGRAMMABLE ENABLES

SRAMs feature two user-programmable chip enable inputs,
E2 and E3. The sense of the inputs, whether they function
as active low or active high inputs, is determined by the
state of the programming inputs, EP2 and EP3. For
example, if EP2 is held at V

, E2 functions as an active

high enable. If EP2 is held to GND , E2 functions as an
active low chip enable input.

BANK ENABLE TRUTH TABLE

EP2

EP3

Bank 0

GND

Active Low

Bank 1

GND

Active Low

Active High

Bank 2

GND

Active High

Active Low

Bank 3

Active High

EXAMPLE FOUR BANK DEPTH EXPANSION SCHEMATIC

Programmability of E2 and E3 allows four banks of depth
expansion to be accomplished with no additional logic. By
programming the enable inputs of four SRAMs in binary
sequence (00, 01, 10, 11) and driving the enable inputs
with two address inputs, four SRAMs can be made to look
like one larger RAM to the system.

A
E3
E2

CLK

DQ
CQ

A
E3
E2

CLK

DQ
CQ

-A

n-2

n-1

A
E3
E2

CLK

DQ
CQ

A
E3
E2

CLK

DQ
CQ

-A

n-2

n-1

A
E3
E2

CLK

DQ
CQ

A
E3
E2

CLK

DQ
CQ

-A

n-2

n-1

A
E3
E2

CLK

DQ
CQ

A
E3
E2

CLK

DQ
CQ

-A

n-2

n-1

Bank 0

Bank 1

Bank 2

Bank 3

A0-An

CLK

DQ0-DQn

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SYNCHRONOUS TRUTH TABLE

CLK

ADV

Previous

Current Operation

DQ/CQ

(tn)

Operation

(tn)

(tn+1)

Bank Deselect

***

Hi-Z

Bank Deselect

Bank Deselect (Continue)

Hi-Z

Deselect

***

Hi-Z/CQ

Deselect

Deselect (Continue)

Hi-Z/CQ

Write

***

Dn/CQ

Loads new address

(tn)

Stores DQx if

BWx

= 0

Write (Abort)

***

Hi-Z/CQ

Loads new address

No data stored

Write

Write Continue

Dn-1/CQ

Dn/CQ

Increments address by 1

(tn-1)

(tn)

Stores DQx if

BWx

= 0

Write

Write Continue (Abort)

Dn-1/CQ

Hi-Z/CQ

Increments address by 1

(tn-1)

No data stored

Read

***

Qn/CQ

Loads new address

(tn)

Read

Read Continue

Qn-1/CQ

Qn/CQ

Increments address by 1

(tn-1)

(tn)

Notes:
1. If E2 = EP2 and E3 = EP3 then E = "T" else E = "F".
2. If one or more

BWx

= 0 then BW = "T" else BW = "F".

3. "1" = input "high"; "0" = input "low"; "X" = input "don't care"; "T" = input "true"; "F" = input "false".
4. "***" indicates that the DQ input requirement/output state and CQ output state are determined by the previous operation.
5. DQs are tri-stated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
6. CQs are tri-stated in response to Bank Deselect commands only, one full cycle after the command is sampled.
7. Up to 3 Continue operations may be initiated after initiating a Read or Write operation to burst transfer up to 4 distinct pieces of data per single

external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial external (base) address.

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READ/WRITE CONTROL STATE DIAGRAM

READ

CONTINUE

WRITE

CONTINUE

DESELECT

BANK

DESELECT

X,F,0,X or
X,X,1,X

1,T,0,X or
X,X,1,X

0,T,0,1

X,X,1,X

X,F,0,X

0,T,0,0

X,F,0,X

0,T,0,0

0,T,0,1

0,T,0,0

0,T,0,1

1,T,0,X

X,X,1,X

0,T,0,1

X,F,0,X

Notes:
1. The notation "X,X,X,X" controlling the state transitions above indicate the states of inputs

, E, ADV, and

respectively.

2. If (E2 = EP2 and E3 = EP3) then E = "T" else E = "F".
3. "1" = input "high"; "0" = input "low"; "X" = input "don't care"; "T" = input "true"; "F" = input "false".

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ABSOLUTE MAXIMUM RATINGS

(All voltages reference to GND )

Symbol

Description

Value

Unit

Voltage on V

Pins

0.5 to 2.5

DDQ

Voltage in V

DDQ

Pins

0.5 to 2.3

I/O

Voltage on I/O Pins

0.5 to V

DDQ

+0.5 (

2.3 V max.)

Voltage on Other Input Pins

0.5 to V

DDQ

+0.5 (

2.3 V max.)

Input Current on Any Pin

±100

mA dc

OUT

Output Current on Any Pin

±100

mA dc

Maximum Junction Temperature

125

STG

Storage Temperature

-55 to 125

Note:

Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Operation should be limited to Recommended
Operating Conditions. Exposure to conditions exceeding Recommended Operating Conditions, for an extended period of time, may
affect reliability of this component.

CURRENT STATE & NEXT STATE DEFINITION FOR READ/WRITE CONTROL STATE DIAGRAM

n n+1

n+2

n+3

Current State

Next State

Command

Transition

Current State (n)

Input Command Code

Next State (n+1)

KEY

POWER SUPPLY CHARACTERISTICS

= 0 min., 25 typ, 70 max °C)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

1.7

1.8

1.9

DDQ

(1)

1.8 V I/O Supply Voltage

1.7

1.8

1.5 V I/O Supply Voltage

1.4

1.5

1.6

Note:

1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V

DDQ

1.6V

(i.e., 1.5 V I/O) and 1.7 V

DDQ

1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.

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CMOS I/O DC INPUT CHARACTERISTICS

Symbol

Parameter

DDQ

Min.

Typ.

Max.

Unit

CMOS Input High Voltage

1.8

1.2

DDQ

+ 0.3

1.5

1.0

DDQ

+ 0.3

CMOS Input Low Voltage

1.8

0.3

0.6

1.5

0.3

0.5

Note:

For devices supplied with CMOS input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.

I/O CAPACITANCE (T

= 25 °C, f = 1 MH

)

Symbol

Parameter

Test conditions

Min.

Max.

Unit

Address

Input Capacitance

= 0 V

3.5

Control

Input Capacitance

= 0 V

3.5

Clock

Input Capacitance

= 0 V

3.5

Data

Output Capacitance

OUT

= 0 V

4.5

CQ Clock

Output Capacitance

OUT

= 0 V

4.5

Note: These parameters are sampled and not 100% tested.

Undershoot Measurement and Timing

Overshoot Measurement and Timing

20% t

50%

GND

GND - 1.0V

20% t

50%

+ 1.0V

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IS61LSCS51236

ISSI

AC TEST CONDITIONS

= 1.8V ± 0.1V, T

= 0 to 85°C)

Parameter

Symbol

Conditions

Units

DDQ

1.5V±0.1

1.8 ±0.1

Input High Level

1.25

1.4

Input Low Level

0.25

0.4

Input Rise & Fall Time

2.0

V/ns

Input Reference Level

0.75

0.9

Clock Input High Voltage

KIH

1.25

1.4

Clock Input Low Voltage

KIL

0.25

0.4

Clock Input Rise & Fall Time

2.0

V/ns

Clock Input Reference Level

0.75

0.9

Output Reference Level

0.75

0.9

Output Load Conditions ZQ = V

see below

Notes:

1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown unless otherwise noted.

AC TEST LOADS

0.75V

16.7

0.75V

5 pF

DDQ

= 1.5V

0.9V

16.7

0.9V

5 pF

DDQ

= 1.8V

Figure 1 (V

DDQ

= 1.5V)

Figure 2 (V

DDQ

= 1.8V)

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ISSI

SELECTABLE IMPEDANCE OUTPUT DRIVER DC ELECTRICAL CHARACTERISTICS

Symbol

Parameter

Test Conditions

Min.

Max.

Units

OHL

(1)

Low Drive Output High Voltage

OHL

= 4 mA

DDQ

0.4

OLL

(1)

Low Drive Output Low Voltage

OLL

= 4 mA

0.4

OHH

(2)

High Drive Output High Voltage

OHH

= 8 mA

DDQ

0.4

OLH

(2)

High Drive Output Low Voltage

OLH

= 8 mA

0.4

Notes:
1. ZQ = 1; High Impedance output driver setting
2. ZQ = 0; Low Impedance output driver setting

OUTPUT RESISTANCE

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units

OUT

Output Resistance

= V

DDQ

ZQ = V

= V

DDQ

ZQ = V

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IS61LSCS51236

ISSI

DC ELECTRICAL CHARACTERISTICS

= 1.8V ±0.1V, GND = 0V, T

= 0

to 85

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Input Leakage Current

= GND to V

DDQ

-5

(Address, Control, Clock)

MLI

Input Leakage Current

MIN

= GND to V

-10

(EP2, EP3, M2, M3, M4, ZQ)

DLI

Input Leakage Current

DIN

= GND to V

DDQ

-10

(Data)

OPERATING CURRENTS

Symbol

Parameter

Test Conditions

-333

-300

-250

Units

Com. Ind.

Operating Current

E1 < V

Max.

Pipeline x72

650

KHKH

> t

KHKH

Min.

x36

550

All other inputs

> V

Bank Deselect Current

E1 < V

Min. or

Pipeline x72

250

E2 or E3 False

x36

225

Chip Disable Current

KHKH

> t

KHKH

Min.

All other inputs

> V

CMOS Deselect Current

Device Deselected

Pipeline x72

150

All inputs

x36

150

GND+0.10V > V

> V

0.10V

Note: Com. = 0°C to 70°C

Ind. = 40°C to +85°C

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ISSI

AC ELECTRICAL CHARACTERISTICS

-333

-300

-250

Symbol

Parameter

Min

Max

Min

Max

Min

Max

Unit

KHKH

Clock Cycle Time

3.0

3.3

4.0

KHKL

Clock HIGH Time

1.2

1.3

1.5

KLKH

Clock LOW Time

1.2

1.3

1.5

KHCX

(2)

Clock High to Echo Clock Low-Z

0.5

KHCH

Clock High to Echo Clock High

0.5

1.5

0.5

1.7

0.5

2.0

CHCL

(2)

Echo Clock High Time

KHKL

±200 ps

KHKL

±200 ps

KHKL

±250 ps

KLCL

Clock Low to Echo Clock Low

0.5

1.5

0.5

1.7

0.5

2.0

CLCH

(2)

Echo Clock Low Time

KLKH

±200 ps

KLKH

±200 ps

KLKH

±250 ps

KHCZ

(1, 2)

Clock High to Echo Clock High-Z

1.5

1.7

2.0

KHQX

(1)

Clock High to Output in Low-Z

0.5

KHQV

Clock High to Output Valid

1.6

1.8

2.1

KHQX

Clock High to Output Invalid

0.5

KHQZ

(1)

Clock High to Output in High-Z

0.5

1.6

0.5

1.8

0.5

2.1

CHQV

(2)

Echo Clock High to Output Valid

0.4

0.5

CHQX

(2)

Output Invalid to Echo Clock High

0.4

0.5

AVKH

Address Valid to Clock High

0.6

0.7

0.8

KHAX

Clock High to Address Don't Care

0.4

0.5

EVKH

Enable Valid to Clock High

0.6

0.7

0.8

KHEX

Clock High to Enable Don't Care

0.4

0.5

WVKH

Write Valid to Clock High

0.6

0.7

0.8

KHWX

Clock High to Write Don't Care

0.4

0.5

BVKH

Byte Write Valid to Clock High

0.6

0.7

0.8

KHBX

Clock High to Byte Write Don't Care

0.4

0.5

DVKH

Data In Valid to Clock High

0.6

0.7

0.8

KHDX

Clock High to Data In Don't Care

0.4

0.5

advVKH

ADV Valid to Clock High

0.6

0.7

0.8

KHadvX

Clock High to ADV Don't Care

0.4

0.5

Notes:

1. Measured at 100 mV from steady state. Not 100% tested.
2. Guaranteed by design. Not 100% tested.
3. For any specific temperature and voltage t

KHCZ

< t

KHCX

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ISSI

AC ELECTRICAL CHARACTERISTICS

-225

-200

Symbol

Parameter

Min

Max

Min

Max

Unit

KHKH

Clock Cycle Time

4.5

5.0

KHKL

Clock HIGH Time

1.8

2.0

KLKH

Clock LOW Time

1.8

2.0

KHCX

(2)

Clock High to Echo Clock Low-Z

0.5

KHCH

Clock High to Echo Clock High

0.5

2.5

0.5

3.0

CHCL

(2)

Echo Clock High Time

KHKL

±250 ps t

KHKL

±250 ps ns

KLCL

Clock Low to Echo Clock Low

0.5

2.5

0.5

3.0

CLCH

(2)

Echo Clock Low Time

KLKH

±200 ps t

KLKH

±200 ps ns

KHCZ

(1, 2)

Clock High to Echo Clock High-Z

2.5

3.0

KHQX

(1)

Clock High to Output in Low-Z

0.5

KHQV

Clock High to Output Valid

2.6

3.1

KHQX

Clock High to Output Invalid

0.5

KHQZ

(1)

Clock High to Output in High-Z

0.5

2.6

0.5

3.1

CHQV

(2)

Echo Clock High to Output Valid

0.5

-- 0.5 ns

CHQX

(2)

Output Invalid to Echo Clock High

0.5

AVKH

Address Valid to Clock High

1.1

1.5

KHAX

Clock High to Address Don't Care

0.5

EVKH

Enable Valid to Clock High

1.1

1.5

KHEX

Clock High to Enable Don't Care

0.5

WVKH

Write Valid to Clock High

1.1

1.5

KHWX

Clock High to Write Don't Care

0.5

BVKH

Byte Write Valid to Clock High

1.1

1.5

KHBX

Clock High to Byte Write Don't Care

0.5

DVKH

Data In Valid to Clock High

1.1

1.5

KHDX

Clock High to Data In Don't Care

0.5

advVKH

ADV Valid to Clock High

1.1

1.5

KHadvX

Clock High to ADV Don't Care

0.5

Notes:

1. Measured at 100 mV from steady state. Not 100% tested.
2. Guaranteed by design. Not 100% tested.
3. For any specific temperature and voltage t

KHCZ

< t

KHCX

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ISSI

TIMING PARAMETER KEY--PIPELINED READ CYCLE TIMING

TIMING PARAMETER KEY--LATE WRITE MODE CONTROL AND DATA IN TIMING

Note: tn

VKH

= t

EVKH

, t

WVKH

, t

BVKH

, etc. and t

= t

KHEX

, t

KHWX

, t

KHBX

, etc.

KLKH

KHKH

KHKL

KHQZ

KHQX

KHQV

KHQX1

CQHQV

KHCQH

KHCQX1

CQHCQL

CQLCQH

CQHQX

KHCQZ

= CQ High Z

KHAX

AVKH

ADDRESS

E1,E2,E3
W, Bn, ADV

AVKH

KHAX

VKH

DVKH

KHDX

Control
"A"

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ISSI

JTAG PORT OPERATION

Overview

These devices provide a JTAG Test Access Port (TAP) and
Boundary Scan interface using a limited set of IEEE std.
1149.1 functions. This test mode is intended to provide a
mechanism for testing the interconnect between master
(processor, controller, etc.), SRAMs, other components,
and the printed circuit board.

In conformance with a subset of IEEE std. 1149.1, these
devices contain a TAP Controller and four TAP Registers.
The TAP Registers consist of one Instruction Register

JTAG PIN DESCRIPTIONS

Pin

Pin Name

I/O

Description

TCK

Test Clock

Clocks all TAP events. All inputs are captured on the rising edge of TCK and
all outputs propagate from the falling edge of TCK.

TMS

Test Mode Select

The TMS input is sampled on the rising edge of TCK. This is the command input
for the TAP controller. An undriven TMS input will produce the same result as
a logic one input level.

TDI

Test Data In

The TDI input is sampled on the rising edge of TCK. This is the input side of the
serial registers placed between TDI and TDO. The register placed between TDI
and TDO is determined by the state of the TAP Controller and the instruction
that is currently loaded in the TAP Instruction Register (refer to the TAP
Controller State Diagram). An undriven TDI pin will produce the same result as
a logic one input level.

TDO

Test Data Out

Out

Output that is active depending on the state of the TAP Controller. Output
changes in response to the falling edge of TCK. This is the output side of the
serial registers placed between TDI and TDO.

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while
TMS is held high for five rising edges of TCK. The TAP Controller is also reset automatically at power-up.

and three Data Registers (ID, Bypass, and Boundary
Scan Registers).

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG
port. The port is reset at power-up and will remain inactive
unless clocked. To assure normal operation of the RAM
with the JTAG Port unused, TCK should be tied Low, TDI
and TMS may be left floating or tied to V

. TDO should be

left unconnected.

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ISSI

JTAG TAP BLOCK DIAGRAM

Bypass Register

Instruction Register

ID Code Register

Boundary Scan Register

. . .

. . . . .

2 1 0

31 30 29

2 1 0

Test Access Port (TAP) Controller

TDI

TMS

TCK

TDO

JTAG PORT REGISTERS

Overview

The JTAG registers, referred to as Test Access Port (TAP)
registers, are selected (one at a time) via the sequences
of 1s and 0s applied to TMS as TCK is strobed. Each of
the TAP registers are serial shift registers that capture
serial input data on the rising edge of TCK and push serial
data out on the next falling edge of TCK. When a register
is selected, it is placed between the TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are
executed by the TAP controller when it is moved into the
Run, Test/Idle, or the various data register states. In-
structions are 3 bits long. The Instruction Register can be
loaded when it is placed between the TDI and TDO pins.
The Instruction Register is automatically preloaded with
the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single-bit register that can be
placed between TDI and TDO. It allows serial test data to
be passed through the RAM's JTAG Port to another
device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be
preset by the logic level found on the RAM's input or I/O pins. The
flip flops are then daisy chained together so the levels found can be
shifted serially out of the JTAG Port's TDO pin. The Boundary Scan
Register also includes a number of place holder flip flops (always set
to a logic 1). The relationship between the device pins and the bits
in the Boundary Scan Register is described in the following Scan
Order Table. The Boundary Scan Register, under the control of the
TAP Controller, is loaded with the contents of the RAMs I/O ring
when the controller is in Capture-DR state and then is placed
between the TDI and TDO pins when the controller is moved to
Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST
instructions can be used to activate the Boundary Scan Register.

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JTAG TAP CONTROLLER STATE DIAGRAM

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

Test Logic Reset

Run Test Idle

IDENTIFICATION (ID) REGISTER

The ID Register is a 32-bit register that is loaded with a
device and vendor specific 32-bit code when the controller
is put in Capture-DR state with the IDCODE command
loaded in the Instruction Register. The code is loaded from

a 32-bit on-chip ROM. It describes various attributes of
the RAM as indicated below. The register is then placed
between the TDI and TDO pins when the controller is
moved into Shift-DR state. Bit 0 in the register is the LSB
and the first to reach TDO when shifting begins.

Bit #

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

x72

X X X X

0 0

x36

X X X X 0 0

0 0

0 0 0

0 0

0 1 0

0 0

0 0 0 1

0 1 0

1 0

Presence Register

Die

I/O

ISSI Technology

Revision

Not Used

Configuration

JEDEC Vendor

Code

ID Code

ID REGISTER CONTENTS

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JTAG TAP INSTRUCTION SET SUMMARY

Instruction

Code

Description

EXTEST

(1)

000

Places the Boundary Scan Register between TDI and TDO. When EXTEST is
selected, data will be driven out of the DQ pad.

IDCODE

(1,2)

001

Preloads ID Register and places it between TDI and TDO.

SAMPLE-Z

(1)

010

Captures I/O ring contents. Places the Boundary Scan Register between TDI
and TDO. Forces all Data and Clock output drivers to High-Z.

RFU

(1)

011

Do not use this instruction; Reserved for Future Use. Replicates BYPASS
instruction. Places Bypass Register between TDI and TDO.

SAMPLE/PRELOAD

(1)

100

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.

Private

(1)

101

Private instruction.

RFU

(1)

110

Do not use this instruction; Reserved for Future Use.

BYPASS

(1)

111

Places Bypass Register between TDI and TDO.

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in Test-Logic-Reset state.

TAP CONTROLLER INSTRUCTION SET

Overview

There are two classes of instructions defined in the
Standard 1149.1-1990; standard (public) instructions, and
device specific (private) instructions. Some public instructions
are mandatory for 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
The TAP on this device may be used to monitor all input
and I/O pads. This device will not perform INTEST but can
preform the preload portion of the SAMPLE/PRELOAD
command.

When the TAP controller is placed in Capture-IR state, the
two least significant bits of the instruction register are
loaded with 01. When the controller is moved to the Shift-IR
state, the Instruction Register is placed between TDI and
TDO. In this state the desired instruction is serially loaded
through the TDI input (while the previous contents are
shifted out at TDO). For all instructions, the TAP executes
newly loaded instructions only when the controller is
moved to Update-IR state. The TAP instruction set for this
device is listed in the JTAG TAP Instruction Set Summary.

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JTAG DC RECOMMENDED OPERATING CONDITIONS (T

= 0 to 85°C)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

TIH

JTAG Input High Voltage

1.2

+0.3

TIL

JTAG Input Low Voltage

-0.3

0.6

TOH

JTAG Output High Voltage

CMOS

TOH

= -100

-0.1

TTL

TOH

= -8m

-0.4

TOL

JTAG Output Low Voltage

CMOS

TOL

= 100

0.1

TTL

TOL

= 8m

0.4

TLI

JTAG Input Leakage Current

TIN

=GND to V

-10

JTAG AC TEST CONDITIONS (V

= 1.8V ±0.1V, T

= 0 to 85°C)

Symbol

Parameter

Test Conditions

Unit

TIH

JTAG Input High Voltage

1.6

TIL

JTAG Input Low Voltage

0.2

JTAG Input Rise & Fall Time

1.0

V/ns

JTAG Input Reference Level

0.9

JTAG Output Reference Level

0.9

JTAG Output Load Condition

see AC TEST LOADS

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ISSI

Symbol

Parameter

Min

Max

Unit

THTH

TCK Cycle Time

THTL

TCK High Pulse Width

TLTH

TCK Low Pulse Width

MVTH

TMS Setup Time

THMX

TMS Hold Time

DVTH

TDI Set Up Time

THDX

TDI Hold Time

TLQV

TCK Low to TDO Valid

TLQX

TCK Low to TDO Hold

JTAG PORT TIMING DIAGRAM

TCK

TMS

TDI

TDO

THTL

TLTH

THTH

MVTH

THMX

DVTH

THDX

TLQX

TLQV

JTAG PORT AC ELECTRICAL CHARACTERISTICS

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INSTRUCTION DESCRIPTIONS

BYPASS

When the BYPASS instruction is loaded to the Instruction
Register, the Bypass Register is placed between TDI and
TDO. This occurs when the TAP controller is moved to the
Shift-DR state. This allows the board level scan path to be
shortened to facilitate testing of other devices in the scan
path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public
instruction. When the SAMPLE/PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller
into the Capture-DR state loads the data in the RAMs input
and I/O buffers into the Boundary Scan Register. Some
Boundary Scan Register locations are not associated with
an input or I/O pin, and are loaded with the default state
identified in the BSDL file. Because the RAM clock is
independent from the TAP Clock (TCK) it is possible for
the TAP to attempt to capture the I/O ring contents while
the input buffers are in transition (i.e. in a metastable
state). Although allowing the TAP to sample metastable
inputs will not harm the device, repeatable results cannot
be expected. RAM input signals must be stabilized for
long enough to meet the TAP's input data capture set-up
plus hold time (t

plus t

). The RAM's clock inputs need

not be paused for any other TAP operation except captur-
ing the I/O ring contents into the Boundary Scan Register.
Moving the controller to Shift-DR state then places the
Boundary Scan Register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction.
It is to be executed whenever the instruction register is
loaded with all logic 0s. The EXTEST command does not
block or override the RAM's input pins; therefore, the
RAM's internal state is still determined by its input pins.

Typically, the Boundary Scan Register is loaded with the
desired pattern of data with the SAMPLE/PRELOAD
command. Then the EXTEST command is used to output
the Boundary Scan Register's contents, in parallel, on the
RAM's data output drivers on the falling edge of TCK when
the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in
parallel using the EXTEST command. When the EXTEST
instruction is selected, the state of all the RAM's input and
I/O pins, as well as the default values at Scan Register
locations not associated with a pin (pin marked NC), are
transferred in parallel into the Boundary Scan Register on
the rising edge of TCK in the Capture-DR state, the RAM's
output pins drive out the value of the Boundary Scan
Register location with which each output pin is associated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded
to the ID register when the controller is in Capture-DR
mode and places the ID register between the TDI and TDO
pins in Shift-DR mode. The IDCODE instruction is the
default instruction loaded in at power up and any time the
controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded to the instruction
register, all RAM outputs are forced to inactive state
(high-Z) and the Boundary Scan Register is connected
between TDI and TDO when the TAP controller is moved
to the Shift-DR state.

RFU

These instructions are reserved for future use. In this
device they replicate the BYPASS instruction.

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ISSI

BOUNDARY SCAN ORDER ASSIGNMENTS (by Exit Sequence) -

PH=Place Holder

X72

Ball Loc.

X36

Sequence

Pkg. Ball

Sequence

Pkg. Ball

U 8

U 6

(1)

U 5

(1)

U 7

(1)

MCL

D 6

MCL

(1)

C 7

(1)

C 8

C 9

ADV

AO36

C 3

C 4

(1)

C 5

(1)

C 6

EP2

EP3

H 6

EP3

Note:

1. Input of PH register connected to Vss.

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1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

11/11/02

IS61LSCS25672
IS61LSCS51236

ISSI

BOUNDARY SCAN ORDER ASSIGNMENTS (by Exit Sequence) Continued:

X72

Ball Loc.

X36

Sequence

Pkg. Ball

Sequence

Pkg. Ball

MCH

N 6

MCH

MCL

U 4

DQd

U 2

DQd

U 1

DQd

DQPd

R 1

DQPd

DQPh

R 2

DQh

N 2

DQh

N 1

DQh

CQ2

DQc

H 2

DQc

H 1

DQc

DQPc

DQPg

DQg

D 2

DQg

D 1

DQg

C 2

DQg

C 1

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

11/11/02

IS61LSCS25672
IS61LSCS51236

ISSI

BOUNDARY SCAN ORDER ASSIGNMENTS (by Exit Sequence) Continued:

X72

Ball Loc.

X36

Sequence

Pkg. Ball

Sequence

Pkg. Ball

DQg

DQb

A10

DQb

A11

DQb

B10

DQb

B11

DQb

C10

DQb

C11

DQb

D10

DQb

D11

DQb

DQPb

E11

DQPb

DQPf

E10

DQf

F10

DQf

F11

DQf

G10

DQf

G11

100

DQf

H10

101

DQf

H11

102

DQf

J10

103

DQf

J11

104

CQ1

K11

CQ1

105

CQ1

K10

CQ1

106

DQa

L10

DQa

107

DQa

L11

DQa

108

DQa

M10

DQa

109

DQa

M11

DQa

110

DQa

N10

DQa

111

DQa

N11

DQa

112

DQa

P10

DQa

113

DQa8

P11

DQa8

114

DQPa9

R10

DQPa9

115

DQPe1

R11

116

DQe2

T10

117

DQe3

T11

118

DQe4

U10

119

DQe5

U11

120

DQe6

V10

121

DQe7

V11

122

DQe8

W10

123

DQe9

W11

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

11/11/02

IS61LSCS25672
IS61LSCS51236

ISSI

ORDERING INFORMATION

Commercial Range: 0

°°
°°
°

C to 70

°°
°°
°

Frequency

Order Part No.

Package

256K x 72

250

IS61LSCS25672-250B

209-Ball BGA

300

IS61LSCS25672-300B

209-Ball BGA

333

IS61LSCS25672-333B

209-Ball BGA

512K x 36

250

IS61LSCS51236-250B

209-Ball BGA

300

IS61LSCS51236-300B

209-Ball BGA

333

IS61LSCS51236-333B

209-Ball BGA

Industrial Range: -40

°°
°°
°

C to 85

°°
°°
°

FrequencySpeed (ns)

Order Part No.

Package

TBD

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IS61LSCS51236

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IS61LSCS51236