Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. A
11/30/00

IS61LV12816

ISSI

FEATURES

· High-speed access time: 8, 10, 12, and 15 ns

· CMOS low power operation

· TTL and CMOS compatible interface levels

· Single 3.3V ± 10% power supply

· Fully static operation: no clock or refresh

required

· Three state outputs

· Data control for upper and lower bytes

· Industrial temperature available

128K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY

DESCRIPTION

The

ISSI

IS61LV12816 is a high-speed, 2,097,152-bit static

RAM organized as 131,072 words by 16 bits. It is fabricated
using

ISSI

's high-performance CMOS technology. This highly

reliable process coupled with innovative circuit design
techniques, yields access times as fast as 8 ns with low power
consumption.

When

CE is HIGH (deselected), the device assumes a

standby mode at which the power dissipation can be reduced
down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable and
Output Enable inputs,

CE and OE. The active LOW Write

Enable (

WE) controls both writing and reading of the memory.

A data byte allows Upper Byte (

UB) and Lower Byte (LB)

access.

The IS61LV12816 is packaged in the JEDEC standard 44-pin
400-mil SOJ, 44-pin TSOP, 44-pin LQFP, and 48-pin mini
BGA (6mm x 8mm).

FUNCTIONAL BLOCK DIAGRAM

NOVEMBER 2000

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.

A0-A16

128K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. A
11/30/00

IS61LV12816

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. A

11/30/00

ISSI

PIN CONFIGURATIONS

44-Pin SOJ (K)

I/O0

I/O1

I/O2

I/O3

Vcc

GND

I/O4

I/O5

I/O6

I/O7

A16

A15

A14

A13

A12

I/O15

I/O14

I/O13

I/O12

GND

Vcc

I/O11

I/O10

I/O9

I/O8

A10

A11

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A4
A3
A2
A1
A0

I/O0
I/O1
I/O2
I/O3

Vcc

GND

I/O4
I/O5
I/O6
I/O7

A16
A15
A14
A13
A12

A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC

44-Pin TSOP (T)

48-Pin mini BGA (B)

1 2 3 4 5 6

N/C

I/O

GND

I/O

Vcc

I/O

A16

I/O

GND

I/O

A14

A15

I/O

A12

A13

I/O

A10

A11

44-Pin LQFP (LQ)

1
2
3
4
5
6
7
8
9
10
11

33
32
31
30
29
28
27
26
25
24
23

12 13 14 15 16 17 18 19 20 21 22

44 43 42 41 40 39 38 37 36 35 345

I/O0
I/O1
I/O2
I/O3

Vcc

GND

I/O4
I/O5
I/O6
I/O7

I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC

TOP VIEW

A16

A15

A14

A13

A12

A11

A10

IS61LV12816

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. A
11/30/00

ISSI

OPERATING RANGE

Range

Ambient Temperature

Commercial

0°C to + 70°C

3.3V ± 10%

Industrial

40°C to + 85°C

3.3V ± 10%

DC ELECTRICAL CHARACTERISTICS

(Over Operating Range)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

Output HIGH Voltage

= Min., I

= 4.0 mA

2.4

Output LOW Voltage

= Min., I

= 8.0 mA

0.4

Input HIGH Voltage

(1)

+ 0.3

Input LOW Voltage

(1)

0.3

0.8

Input Leakage

GND - V

- V

µA

Output Leakage

GND - V

OUT

- V

, Outputs Disabled

µA

Note:
1. V

(min.) = 0.3V DC; V

(min.) = 2.0V AC (pulse width - 2.0 ns).

(max.) = V

+ 0.3V DC; V

(max.) = V

+ 2.0V AC (pulse width - 2.0 ns).

PIN DESCRIPTIONS

A0-A16

Address Inputs

I/O0-I/O15

Data Inputs/Outputs

Chip Enable Input

Output Enable Input

Write Enable Input

Lower-byte Control (I/O0-I/O7)

Upper-byte Control (I/O8-I/O15)

No Connection

Vcc

Power

GND

Ground

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

Power Supply Voltage Relative to GND

0.5 to 5.0

TERM

Terminal Voltage with Respect to GND

0.5 to Vcc + 0.5

STG

Storage Temperature

65 to + 150

°C

BIAS

Temperature Under Bias:

Com.

10 to + 85

°C

Ind.

45 to + 90

°C

Power Dissipation

2.0

OUT

DC Output Current

±20

Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

IS61LV12816

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. A

11/30/00

ISSI

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns

-10 ns

-12 ns

-15 ns

Symbol

Parameter

Test Conditions

Min. Max.

Unit

Vcc Operating

= Max.,

CE = V

Com.

150

125

110

Supply Current

OUT

= 0 mA, f = Max.

Ind.

160

135

120

100

TTL Standby

= Max.,

Com.

Current

= V

or V

Ind.

(TTL Inputs)

CE · V

, f = max

CMOS Standby

= Max.,

Com.

Current

CE - V

0.2V,

Ind.

(CMOS Inputs)

> V

0.2V, or

- 0.2V, f = 0

Note:
1. At f = f

MAX

, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

TRUTH TABLE

I/O PIN

Mode

I/O0-I/O7

I/O8-I/O15

Vcc Current

Not Selected

High-Z

, I

Output Disabled

High-Z

Read

OUT

High-Z

OUT

Write

High-Z

IS61LV12816

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. A
11/30/00

ISSI

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns

-10 ns

-12 ns

-15 ns

Symbol

Parameter

Min.

Max

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Read Cycle Time

Address Access Time

OHA

Output Hold Time

ACE

CE Access Time

DOE

OE Access Time

HZOE

(2)

OE to High-Z Output

LZOE

(2)

OE to Low-Z Output

HZCE

(2)

CE to High-Z Output

LZCE

(2)

CE to Low-Z Output

LB, UB Access Time

HZB

(2)

LB, UB to High-Z Output

LZB

(2)

LB, UB to Low-Z Output

Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels

of 0V to 3.0V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

3 ns

Input and Output Timing

1.5V

and Reference Level

Output Load

See Figures 1 and 2

AC TEST LOADS

Figure 1.

319

5 pF

Including

jig and

scope

353

OUTPUT

3.3V

CAPACITANCE

(1)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Input/Output Capacitance

OUT

= 0V

Note:
1. Tested initially and after any design or process changes that may affect these parameters.

319

30 pF

Including

jig and

scope

353

OUTPUT

3.3V

Figure 2.

IS61LV12816

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. A

11/30/00

ISSI

DATA VALID

READ1.eps

PREVIOUS DATA VALID

OHA

OUT

ADDRESS

OHA

DOE

LZOE

ACE

LZCE

HZOE

HIGH-Z

DATA VALID

UB_CEDR2.eps

HZB

ADDRESS

LB, UB

OUT

HZCE

LZB

READ CYCLE NO. 2

(1,3)

AC WAVEFORMS

READ CYCLE NO. 1

(1,2)

(Address Controlled) (

CE = OE = V

UB or LB = V

)

Notes:
1.

WE is HIGH for a Read Cycle.

2. The device is continuously selected.

OE, CE, UB, or LB = V

3. Address is valid prior to or coincident with

CE LOW transition.

IS61LV12816

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. A
11/30/00

ISSI

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,3)

(Over Operating Range)

-8 ns

-10 ns

-12 ns

-15 ns

Symbol

Parameter

Min.

Max

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Write Cycle Time

SCE

CE to Write End

6.5

Address Setup Time

6.5

to Write End

Address Hold from Write End

Address Setup Time

PWB

LB, UB Valid to End of Write

6.5

PWE

WE Pulse Width (OE = HIGH)

PWE

WE Pulse Width (OE = LOW)

6.5

Data Setup to Write End

Data Hold from Write End

HZWE

(3)

WE LOW to High-Z Output

LZWE

(3)

WE HIGH to Low-Z Output

Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V

to 3.0V and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of

CE LOW and UB or LB, and WE LOW. All signals must be in valid

states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing
are referenced to the rising or falling edge of the signal that terminates the write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

IS61LV12816

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. A
11/30/00

ISSI

WRITE CYCLE NO. 2

(1)

(

WE Controlled, OE = HIGH during Write Cycle)

DATA UNDEFINED

LOW

VALID ADDRESS

PWE1

HIGH-Z

PBW

HZWE

ADDRESS

UB, LB

OUT

DATA

VALID

LZWE

UB_CEWR2.eps

WRITE CYCLE NO. 3

(

WE Controlled: OE is LOW During Write Cycle)

DATA UNDEFINED

VALID ADDRESS

LOW

PWE2

HIGH-Z

PBW

HZWE

ADDRESS

UB, LB

OUT

DATA

VALID

LZWE

UB_CEWR3.eps

IS61LV12816

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. A

11/30/00

ISSI

DATA UNDEFINED

ADDRESS 1

ADDRESS 2

HIGH-Z

PBW

WORD 1

LOW

WORD 2

UB_CEWR4.eps

HZWE

ADDRESS

UB, LB

OUT

DATA

VALID

LZWE

PBW

DATA

VALID

WRITE CYCLE NO. 4

(

LB, UB Controlled, Back-to-Back Write)

(1,3)

Notes:
1. The internal Write time is defined by the overlap of

CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be

in valid states to initiate a Write, but any can be deasserted to terminate the Write. The

, and

timing is

referenced to the rising or falling edge of the signal that terminates the Write.

2. Tested with

OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.

WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.

IS61LV12816

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. A
11/30/00

ISSI

IS61LV12816 STANDARD VERSION

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed (ns) Order Part No.

Package

IS61LV12816-8B

mini BGA (6mm x 8mm)

IS61LV12816-8K

400-mil Plastic SOJ

IS61LV12816-8LQ

LQFP

IS61LV12816-8T

Plastic TSOP

IS61LV12816-10B

mini BGA (6mm x 8mm)

IS61LV12816-10K

400-mil Plastic SOJ

IS61LV12816-10LQ

LQFP

IS61LV12816-10T

Plastic TSOP

IS61LV12816-12B

mini BGA (6mm x 8mm)

IS61LV12816-12K

400-mil Plastic SOJ

IS61LV12816-12LQ

LQFP

IS61LV12816-12T

Plastic TSOP

IS61LV12816-15B

mini BGA (6mm x 8mm)

IS61LV12816-15K

400-mil Plastic SOJ

IS61LV12816-15LQ

LQFP

IS61LV12816-15T

Plastic TSOP

IS61LV12816 STANDARD VERSION

ORDERING INFORMATION

Industrial Range: 40°C to +85°C

Speed (ns) Order Part No.

Package

IS61LV12816-8BI

mini BGA (6mm x 8mm)

IS61LV12816-8KI

400-mil Plastic SOJ

IS61LV12816-8LQI

LQFP

IS61LV12816-8TI

Plastic TSOP

IS61LV12816-10BI

mini BGA (6mm x 8mm)

IS61LV12816-10KI

400-mil Plastic SOJ

IS61LV12816-10LQI

LQFP

IS61LV12816-10TI

Plastic TSOP

IS61LV12816-12BI

mini BGA (6mm x 8mm)

IS61LV12816-12KI

400-mil Plastic SOJ

IS61LV12816-12LQI

LQFP

IS61LV12816-12TI

Plastic TSOP

IS61LV12816-15BI

mini BGA (6mm x 8mm)

IS61LV12816-15KI

400-mil Plastic SOJ

IS61LV12816-15LQI

LQFP

IS61LV12816-15TI

Plastic TSOP

ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: 1-800-379-4774
Fax: (408) 588-0806

E-mail: sales@issi.com

www.issi.com

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