IS61LV12816L

ISSI

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. F
10/27/05

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.

FEATURES

· High-speed access time: 8, 10 ns

· Operating Current: 50mA (typ.)

· Stand by Current: 700µA (typ.)

· TTL and CMOS compatible interface levels

· Single 3.3V power supply

· Fully static operation: no clock or refresh

required

· Three state outputs

· Data control for upper and lower bytes

· Industrial temperature available

· Lead-free available

128K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY

DESCRIPTION

The

ISSI

IS61LV12816L is a high-speed, 2,097,152-bit

static RAM organized as 131,072 words by 16 bits. It is
fabricated using

ISSI

's high-performance CMOS

technology. This highly reliable process coupled with
innovative circuit design techniques, yields access times
as fast as 8 ns with low power consumption.

When

is HIGH (deselected), the device assumes a

standby mode at which the power dissipation can be
reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,

and

. The active LOW

Write Enable (

) controls both writing and reading of the

memory. A data byte allows Upper Byte (

) and Lower

Byte (

) access.

The IS61LV12816L is packaged in the JEDEC standard
44-pin TSOP (Type II), 44-pin LQFP, and 48-pin mini BGA
(6mm x 8mm).

FUNCTIONAL BLOCK DIAGRAM

OCTOBER 2005

A0-A16

128Kx16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VDD

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

IS61LV12816L

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. F

10/27/05

ISSI

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A4
A3
A2
A1
A0

I/O0
I/O1
I/O2
I/O3

GND

I/O4
I/O5
I/O6
I/O7

A16
A15
A14
A13
A12

A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
V

I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC

44-Pin TSOP (Type II) (T)

PIN DESCRIPTIONS

A0-A16

Address Inputs

I/O0-I/O15

Data Inputs/Outputs

Chip Enable Input

Output Enable Input

Write Enable Input

Lower-byte Control (I/O0-I/O7)

Upper-byte Control (I/O8-I/O15)

No Connection

Power

GND

Ground

TRUTH TABLE

I/O PIN

Mode

I/O0-I/O7

I/O8-I/O15

Current

Not Selected

High-Z

, I

Output Disabled

High-Z

Read

OUT

High-Z

OUT

Write

High-Z

PIN CONFIGURATION

IS61LV12816L

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. F
10/27/05

ISSI

PIN DESCRIPTIONS

A0-A16

Address Inputs

I/O0-I/O15

Data Inputs/Outputs

Chip Enable Input

Output Enable Input

Write Enable Input

Lower-byte Control (I/O0-I/O7)

Upper-byte Control (I/O8-I/O15)

No Connection

Power

GND

Ground

48-Pin mini BGA (B)

44-Pin LQFP (LQ)

1
2
3
4
5
6
7
8
9
10
11

33
32
31
30
29
28
27
26
25
24
23

12 13 14 15 16 17 18 19 20 21 22

44 43 42 41 40 39 38 37 36 35 345

I/O0
I/O1
I/O2
I/O3

GND

I/O4
I/O5
I/O6
I/O7

I/O15
I/O14
I/O13
I/O12
GND
V

I/O11
I/O10
I/O9
I/O8
NC

TOP VIEW

A16

A15

A14

A13

A12

A11

A10

PIN CONFIGURATION

1 2 3 4 5 6

I/O

GND

I/O

A16

I/O

GND

I/O

A14

A15

I/O

A12

A13

I/O

A10

A11

IS61LV12816L

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. F

10/27/05

ISSI

OPERATING RANGE

Range

Ambient Temperature

(8 n

)

(10 n

)

Commercial

0°C to +70°C

3.3V + 10%, -5%

3.3V + 10%

Industrial

40°C to +85°C

3.3V + 10%, -5%

3.3V + 10%

DC ELECTRICAL CHARACTERISTICS

(Over Operating Range)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

Output HIGH Voltage

= Min., I

= 4.0 mA

2.4

Output LOW Voltage

= Min., I

= 8.0 mA

0.4

Input HIGH Voltage

(1)

+ 0.3

Input LOW Voltage

(1)

0.3

0.8

Input Leakage

GND

µA

Output Leakage

GND

OUT

, Outputs Disabled

µA

Note:

(min.) = 0.3V DC; V

(min.) = 2.0V AC (pulse width - 2.0 ns). Not 100% tested.

(max.) = V

+ 0.3V DC; V

(max.) = V

+ 2.0V AC (pulse width - 2.0 ns). Not 100% tested.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

Power Supply Voltage Relative to GND

0.5 to 4.0V

TERM

Terminal Voltage with Respect to GND

0.5 to V

+ 0.5

STG

Storage Temperature

65 to + 150

°C

Power Dissipation

1.0

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.

IS61LV12816L

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. F
10/27/05

ISSI

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns

-10 ns

Symbol

Parameter

Test Conditions

Min. Max.

Unit

Operating

= Max.,

= V

Com.

Supply Current

OUT

= 0 mA, f = Max.

Ind.

typ.

(2)

TTL Standby

= Max.,

Com.

Current

= V

or V

Ind.

(TTL Inputs)

, f = max

CMOS Standby

= Max.,

Com.

Current

0.2V,

Ind.

(CMOS Inputs)

0.2V, or

typ.

(2)

700

0.2V, f = 0

Note:

1. At f = f

MAX

, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

2. Typical values are measured at V

=3.3V, T

=25

C. Not 100% tested.

CAPACITANCE

(1)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Input/Output Capacitance

OUT

= 0V

Note:

1. Tested initially and after any design or process changes that may affect these parameters.

IS61LV12816L

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. F

10/27/05

ISSI

AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

3 ns

Input and Output Timing

1.5V

and Reference Level

Output Load

See Figures 1 and 2

AC TEST LOADS

Figure 1.

319

5 pF

Including

jig and

scope

353

OUTPUT

3.3V

Figure 2.

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns

-10 ns

Symbol

Parameter

Min.

Max

Min.

Max.

Unit

Read Cycle Time

Address Access Time

OHA

Output Hold Time

ACE

Access Time

DOE

Access Time

3.5

HZOE

(2)

to High-Z Output

3.5

LZOE

(2)

to Low-Z Output

HZCE

(2)

to High-Z Output

3.5

LZCE

(2)

to Low-Z Output

3.5

Access Time

3.5

HZB

(2)

to High-Z Output

3.5

LZB

(2)

to Low-Z Output

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to

3.0V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

= 50

1.5V

OUTPUT

30 pF
Including
jig and
scope

IS61LV12816L

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. F
10/27/05

ISSI

DATA VALID

READ1.eps

PREVIOUS DATA VALID

OHA

OUT

ADDRESS

OHA

DOE

LZOE

ACE

LZCE

HZOE

HIGH-Z

DATA VALID

UB_CEDR2.eps

HZB

ADDRESS

OUT

HZCE

LZB

READ CYCLE NO. 2

(1,3)

AC WAVEFORMS

READ CYCLE NO. 1

(1,2)

(Address Controlled) (

= V

)

Notes:

is HIGH for a Read Cycle.

2. The device is continuously selected.

, or

= V

3. Address is valid prior to or coincident with

LOW transition.

IS61LV12816L

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. F

10/27/05

ISSI

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,3)

(Over Operating Range)

-8 ns

-10 ns

Symbol

Parameter

Min.

Max

Min.

Max.

Unit

Write Cycle Time

SCE

to Write End

Address Setup Time

to Write End

Address Hold from Write End

Address Setup Time

PBW

Valid to End of Write

6.5

PWE

Pulse Width (

= HIGH)

PWE

Pulse Width (

= LOW)

6.5

Data Setup to Write End

Data Hold from Write End

HZWE

(3)

LOW to High-Z Output

LZWE

(3)

HIGH to Low-Z Output

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to

3.0V and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of

LOW and

, and

LOW. All signals must be in valid states

to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

IS61LV12816L

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. F

10/27/05

ISSI

WRITE CYCLE NO. 2

(1)

(

Controlled,

= HIGH during Write Cycle)

WRITE CYCLE NO. 3

(

Controlled:

is LOW During Write Cycle)

DATA UNDEFINED

LOW

VALID ADDRESS

PWE1

HIGH-Z

PBW

HZWE

ADDRESS

OUT

DATA

VALID

LZWE

UB_CEWR2.eps

DATA UNDEFINED

VALID ADDRESS

LOW

PWE2

HIGH-Z

PBW

HZWE

ADDRESS

OUT

DATA

VALID

LZWE

UB_CEWR3.eps

IS61LV12816L

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. F
10/27/05

ISSI

DATA UNDEFINED

ADDRESS 1

ADDRESS 2

HIGH-Z

PBW

WORD 1

LOW

WORD 2

UB_CEWR4.eps

HZWE

ADDRESS

OUT

DATA

VALID

LZWE

PBW

DATA

VALID

WRITE CYCLE NO. 4

(

Controlled, Back-to-Back Write)

(1,3)

Notes:

1. The internal Write time is defined by the overlap of

= LOW,

and/or

= LOW, and

= LOW. All signals must be

in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t

, t

, and t

timing is

referenced to the rising or falling edge of the signal that terminates the Write.

2. Tested with OE HIGH for a minimum of 4 ns before

= LOW to place the I/O in a HIGH-Z state.

3. WE may be held LOW across many address cycles and the

pins can be used to control the Write function.

IS61LV12816L

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. F

10/27/05

ISSI

DATA RETENTION WAVEFORM

(

Controlled)

DATA RETENTION SWITCHING CHARACTERISTICS

Symbol

Parameter

Test Condition

Options

Min.

Typ.

(1)

Max.

Unit

for Data Retention

See Data Retention Waveform

2.0

3.6

Data Retention Current

= 2.0V,

0.2V

Com.

0.7

Ind.

SDR

Data Retention Setup Time

See Data Retention Waveform

RDR

Recovery Time

See Data Retention Waveform

Note 1:

Typical values are measured at V

= 3.3V, T

= 25

C. Not 100% tested.

- 0.2V

SDR

RDR

GND

Data Retention Mode

IS61LV12816L

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. F
10/27/05

ISSI

ORDERING INFORMATION:

Commercial Range: 0°C to +70°C

Speed (ns)

Order Part No.

Package

IS61LV12816L-8T

Plastic TSOP (Type II)

IS61LV12816L-8TL

Plastic TSOP (Type II), Lead-free

IS61LV12816L-10T

Plastic TSOP (Type II)

IS61LV12816L-10TL

Plastic TSOP (Type II), Lead-free

Industrial Range: 40°C to +85°C

Speed (ns)

Order Part No.

Package

IS61LV12816L-8BI

mini BGA (6mm x 8mm)

IS61LV12816L-8TI

Plastic TSOP (Type II)

IS61LV12816L-10BI

mini BGA (6mm x 8mm)

IS61LV12816L-10BLI

mini BGA (6mm x 8mm), Lead-free

IS61LV12816L-10LQI

LQFP

IS61LV12816L-10LQLI

LQFP, Lead-free

IS61LV12816L-10TI

Plastic TSOP (Type II)

IS61LV12816L-10TLI

Plastic TSOP (Type II), Lead-free

PACKAGING INFORMATION

ISSI

Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. B
05/30/03

LQFP (Low Profile Quad Flat Pack)
Package Code: LQ (44-pin)

Low Profile Quad Flat Pack (LQ)

Ref. Std.

MS-026

No. Leads

Millimeters

Inches

Symbol

Min

Max

Min

Max

1.60

0.063

0.05

0.15

0.002

0.006

1.35

1.45

0.053

0.057

0.30

0.45

0.012

0.018

0.09

0.20

0.004

0.008

12.00 BSC

0.472 BSC

10.00 BSC

0.394 BSC

12.00 BSC

0.472 BSC

10.00 BSC

0.394 BSC

0.80 BSC

0.031 BSC

0.45

0.75

0.018

0.030

1.00 REF.

0.039 REF.

Notes:
1. All dimensioning and tolerancing

conforms to ANSI Y14.5M-1982.

2. Dimensions D1 and E1 do not include

mold protrusions. Allowable protrusion is
0.25 mm per side. D1 and E1 include
mold mismatch.

3. Controlling dimension: millimeters.

SEATING
PLANE

PACKAGING INFORMATION

ISSI

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. D
01/15/03

Mini Ball Grid Array
Package Code: B (48-pin)

Notes:
1. Controlling dimensions are in millimeters.

mBGA - 6mm x 8mm

MILLIMETERS

INCHES

Sym.

Min. Typ. Max.

N0.
Leads

1.20

0.047

0.24

0.30

0.009

0.012

0.60

0.024

7.90

8.10

0.311

0.319

5.25 BSC

0.207 BSC

5.90

6.10

0.232

0.240

3.75 BSC

0.148 BSC

0.75 BSC

0.030 BSC

0.30

0.35

0.40

0.012 0.014 0.016

mBGA - 8mm x 10mm

MILLIMETER

INCHES

Sym.

Min. Typ. Max.

N0.
Leads

1.20

0.047

0.24

0.30

0.009

0.012

0.60

0.024

9.90

10.10

0.390

0.398

5.25 BSC

0.207 BSC

7.90

8.10

0.311

0.319

3.75 BSC

0.148 BSC

0.75 BSC

0.030 BSC

0.30

0.35

0.40

0.012 0.014 0.016

SEATING PLANE

b (48x)

Top View

Bottom View

6 5 4 3 2 1

1 2 3 4 5 6

PACKAGING INFORMATION

ISSI

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. F
06/18/03

Plastic TSOP
Package Code: T (Type II)

SEATING PLANE

N/2

N/2+1

Notes:
1. Controlling dimension: millimieters,

unless otherwise specified.

2. BSC = Basic lead spacing

between centers.

3. Dimensions D and E1 do not

include mold flash protrusions and
should be measured from the
bottom of the package.

4. Formed leads shall be planar with

respect to one another within
0.004 inches at the seating plane.

Plastic TSOP (T - Type II)

Millimeters

Inches

Millimeters

Inches

Millimeters

Inches

Symbol Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Ref. Std.

No. Leads (N)

1.20

0.047

1.20

0.047

1.20

0.047

0.05

0.15

0.002 0.006

0.05

0.15

0.002 0.006

0.05

0.15

0.002 0.006

0.30

0.52

0.012 0.020

0.30

0.45

0.012 0.018

0.30

0.45

0.012 0.018

0.12

0.21

0.005 0.008

0.12

0.21

0.005 0.008

0.12

0.21

0.005 0.008

20.82 21.08

0.820 0.830

18.31 18.52

0.721 0.729

20.82 21.08

0.820 0.830

10.03 10.29

0.391 0.400

10.03 10.29

0.395 0.405

10.03 10.29

0.395 0.405

11.56 11.96

0.451 0.466

11.56 11.96

0.455 0.471

11.56 11.96

0.455 0.471

1.27 BSC

0.050 BSC

0.80 BSC

0.032 BSC

0.80 BSC

0.031 BSC

0.40

0.60

0.016 0.024

0.41

0.60

0.016 0.024

0.40

0.60

0.016 0.024

ZD 0.95 REF 0.037 REF 0.81 REF 0.032 REF 0.88 REF 0.035 REF

0°

5°

0°

5°

0°

5°

0°

5°

0°

5°

0°

5°

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