IS61LV12824
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
1
Rev. D
06/22/05
Copyright 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
FEATURES
High-speed access time: 8, 10 ns
CMOS low power operation
-- 756 mW (max.) operating @ 8 ns
-- 36 mW (max.) standby @ 8 ns
TTL compatible interface levels
Single 3.3V power supply
Fully static operation: no clock or refresh
required
Three state outputs
Available in 119-pin Plastic Ball Grid Array
(PBGA) and 100-pin TQFP packages.
Industrial temperature available
Lead-free available
DESCRIPTION
The
ISSI
IS61LV12824 is a high-speed, static RAM organized
as 131,072 words by 24 bits. It is fabricated using
ISSI
's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields ac-
cess times as fast as 8 ns with low power consumption.
When
CE1
,
CE2
are HIGH and CE2 is LOW (deselected), the
device assumes a standby mode at which the power dissipa-
tion can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE1
, CE2,
CE2
and
OE
. The active
LOW Write Enable (
WE
) controls both writing and reading of
the memory.
The IS61LV12824 is packaged in the JEDEC standard
119-pin PBGA and 100-pin TQFP.
FUNCTIONAL BLOCK DIAGRAM
JUNE 2005
A0-A16
CE1
OE
WE
128K x 24
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
CE2
CE2
I/O0-I/O23
128K x 24 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
IS61LV12824
ISSI
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. D
06/22/05
PIN CONFIGURATION - 119-pin PBGA
PIN DESCRIPTIONS
A0-A16
Address Inputs
I/O0-I/O23 Data Inputs/Outputs
CE1
,
CE2
Chip Enable Input LOW
CE2
Chip Enable Input HIGH
OE
Output Enable Input
WE
Write Enable Input
NC
No Connection
Vcc
Power
V
CCQ
I/O Power
GND
Ground
1
2
3
4
5
6
7
A
NC
A11
A14
A15
A16
A4
NC
B
NC
A12
A13
CE1
A5
A3
NC
C
I/O16
NC
CE2
NC
CE2
NC
I/O0
D
I/O17
V
CCQ
GND
GND
GND
V
CCQ
I/O1
E
I/O18
GND
V
CC
GND
V
CC
GND
I/O2
F
I/O19
V
CCQ
GND
GND
GND
V
CCQ
I/O3
G
I/O20
GND
V
CC
GND
V
CC
GND
I/O4
H
I/O21
V
CCQ
GND
GND
GND
V
CCQ
I/O5
J
V
CCQ
GND
V
CC
GND
V
CC
GND
V
CCQ
K
I/O22
V
CCQ
GND
GND
GND
V
CCQ
I/O6
L
I/O23
GND
V
CC
GND
V
CC
GND
I/O7
M
I/O12
V
CCQ
GND
GND
GND
V
CCQ
I/O8
N
I/O13
GND
V
CC
GND
V
CC
GND
I/O9
P
I/O14
V
CCQ
GND
GND
GND
V
CCQ
I/O10
R
I/O15
NC
NC
NC
NC
NC
I/O11
T
NC
A10
A8
WE
A0
A1
NC
U
NC
A9
A7
OE
A6
A2
NC
IS61LV12824
1
2
3
4
5
6
7
8
9
10
11
12
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
3
Rev. D
06/22/05
PIN CONFIGURATION
100-Pin TQFP
NC
Vcc
GND
I/O0
I/O1
GND
Vcc
Q
I/O2
I/O3
GND
Vcc
Q
I/O4
I/O5
Vcc
NC
NC
GND
I/O6
I/O7
Vcc
Q
GND
I/O8
I/O9
Vcc
Q
GND
I/O10
I/O11
Vcc
GND
NC
NC
NC
A11
A12
A13
A14
A15
CE2
Vcc
GND
CE2
CE1
A16
A5
A4
A3
NC
NC
NC
NC
NC
Vcc
GND
I/O16
I/O17
GND
Vcc
Q
I/O18
I/O19
GND
Vcc
Q
I/O20
I/O21
Vcc
NC
NC
GND
I/O22
I/O23
Vcc
Q
GND
I/O12
I/O13
Vcc
Q
GND
I/O14
I/O15
Vcc
GND
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
NC
NC
NC
NC
A10
A9
A8
A7
OE
GND
Vcc
WE
A6
A0
A1
A2
NC
NC
NC
NC
46 47 48 49 50
PIN DESCRIPTIONS
A0-A16
Address Inputs
I/O0-I/O23
Data Inputs/Outputs
CE1
,
CE2
Chip Enable Input LOW
CE2
Chip Enable Input HIGH
OE
Output Enable Input
WE
Write Enable Input
NC
No Connection
Vcc
Power
V
CCQ
I/O Power
GND
Ground
IS61LV12824
ISSI
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. D
06/22/05
OPERATING RANGE
Range
Ambient Temperature
V
CC
(8 ns)
V
CC
(10 ns)
Commercial
0C to +70C
3.3V + 10%, 5%
3.3V 10%
Industrial
40C to +85C
3.3V + 10%, 5%
3.3V 10%
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 4.0 mA
2.4
--
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
--
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
(1)
0.3
0.8
V
I
LI
Input Leakage
GND
V
IN
V
CC
1
1
A
I
LO
Output Leakage
GND
V
OUT
V
CC
, Outputs Disabled
1
1
A
Note:
1. V
IL
(min.) = 0.3V DC; V
IL
(min.) = 2.0V AC (pulse width
2.0 ns).
V
IH
(max.) = V
CC
+ 0.3V DC; V
IH
(max.) = V
CC
+ 2.0V AC (pulse width
2.0 ns).
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
CC
Power Supply Voltage Relative to GND
0.5 to 5.0
V
V
TERM
Terminal Voltage with Respect to GND
0.5 to Vcc + 0.5
V
T
STG
Storage Temperature
65 to + 150
C
T
BIAS
Temperature Under Bias:
Com.
10 to + 85
C
Ind.
45 to + 90
C
P
T
Power Dissipation
2.0
W
I
OUT
DC Output Current
20
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TRUTH TABLE
Mode
WE
WE
WE
WE
WE
CE1
CE1
CE1
CE1
CE1
CE2
CE2
CE2
CE2
CE2
CE2
OE
OE
OE
OE
OE
I/O0-I/O23
Vcc Current
Not Selected
X
H
X
X
X
High-Z
I
SB
1
, I
SB
2
X
X
L
X
X
X
X
X
H
X
Output Disabled
H
L
H
L
H
High-Z
I
CC
Read
H
L
H
L
L
D
OUT
I
CC
Write
L
L
H
L
X
D
IN
I
CC
IS61LV12824
1
2
3
4
5
6
7
8
9
10
11
12
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
5
Rev. D
06/22/05
CAPACITANCE
(1)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Input/Output Capacitance
V
OUT
= 0V
8
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-8 ns
-10 ns
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
I
CC
Vcc Dynamic Operating
V
CC
= Max.,
Com.
--
210
--
180
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
--
240
--
210
I
SB
1
TTL Standby Current
V
CC
= Max.,
Com.
--
70
--
50
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
, f = max.
Ind.
--
80
--
55
CE1
,
CE2
,
V
IH
, CE2
V
IL
I
SB
2
CMOS Standby
V
CC
= Max.,
Com.
--
10
--
10
mA
Current (CMOS Inputs)
CE1
,
CE2
V
CC
0.2V,
Ind.
--
20
--
20
CE2
0.2V, V
IN
V
CC
0.2V,
or V
IN
0.2V, f = 0
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
2 ns
Input and Output Timing
1.5V
and Reference Level
Output Load
See Figures 1 and 2
AC TEST LOADS
Figure 1
Figure 2
319
5 pF
Including
jig and
scope
353
OUTPUT
3.3V
OUTPUT
Z
O
= 50
1.5V
50
PDF 
ZIP