IS61LV12824

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
04/17/01

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

FEATURES

· High-speed access time: 8, 9, 10, 12 ns

· CMOS low power operation

-- 756 mW (max.) operating @ 8 ns

-- 36 mW (max.) standby @ 8 ns

· TTL compatible interface levels

· Single 3.3V power supply

· Fully static operation: no clock or refresh

required

· Three state outputs

· Available in 119-pin Plastic Ball Grid Array

(PBGA) and 100-pin TQFP packages.

· Industrial temperature available

DESCRIPTION

The

ISSI

IS61LV12824 is a high-speed, static RAM organized

as 131,072 words by 24 bits. It is fabricated using

ISSI

's high-

performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields ac-
cess times as fast as 8 ns with low power consumption.

When

CE1, CE2 are HIGH and CE2 is LOW (deselected), the

device assumes a standby mode at which the power dissipa-
tion can be reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,

CE1, CE2, CE2 and OE. The active

LOW Write Enable (

WE) controls both writing and reading of

the memory.

The IS61LV12824 is packaged in the JEDEC standard
119-pin PBGA and 100-pin TQFP.

FUNCTIONAL BLOCK DIAGRAM

DECEMBER 1999

A0-A16

CE1

128K x 24

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

CE2

I/O0-I/O23

128K x 24 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY

IS61LV12824

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

04/17/01

PIN CONFIGURATION - 119-pin PBGA

PIN DESCRIPTIONS

A0-A16

Address Inputs

I/O0-I/O23 Data Inputs/Outputs

CE1, CE2 Chip Enable Input LOW

CE2

Chip Enable Input HIGH

Output Enable Input

Write Enable Input

No Connection

Vcc

Power

CCQ

I/O Power

GND

Ground

A11

A14

A15

A16

A12

A13

CE1

I/O16

CE2

I/O0

I/O17

CCQ

GND

CCQ

I/O1

I/O18

GND

I/O2

I/O19

CCQ

GND

CCQ

I/O3

I/O20

GND

I/O4

I/O21

CCQ

GND

CCQ

I/O5

CCQ

GND

CCQ

I/O22

CCQ

GND

CCQ

I/O6

I/O23

GND

I/O7

I/O12

CCQ

GND

CCQ

I/O8

I/O13

GND

I/O9

I/O14

CCQ

GND

CCQ

I/O10

I/O15

I/O11

A10

IS61LV12824

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
04/17/01

PIN CONFIGURATION
100-Pin TQFP

NC
Vcc
GND
I/O0
I/O1
GND
Vcc

I/O2
I/O3
GND
Vcc

I/O4
I/O5
Vcc
NC
NC
GND
I/O6
I/O7
Vcc

GND
I/O8
I/O9
Vcc

GND
I/O10
I/O11
Vcc
GND
NC

A11

A12

A13

A14

A15

CE2

Vcc

GND

CE2

CE1

A16

Vcc

GND

I/O16
I/O17

GND
Vcc

I/O18
I/O19

GND
Vcc

I/O20
I/O21

Vcc

NC
NC

GND

I/O22
I/O23

Vcc

GND

I/O12
I/O13

Vcc

GND

I/O14
I/O15

Vcc

GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

A10

GND

Vcc

46 47 48 49 50

IS61LV12824

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

04/17/01

OPERATING RANGE

Range

Ambient Temperature

(8, 9 ns)

(10, 12 ns)

Commercial

0°C to +70°C

3.3V + 10%, 5%

3.3V ± 10%

Industrial

40°C to +85°C

3.3V + 10%, 5%

3.3V ± 10%

DC ELECTRICAL CHARACTERISTICS

(Over Operating Range)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

Output HIGH Voltage

= Min., I

= 4.0 mA

2.4

Output LOW Voltage

= Min., I

= 8.0 mA

0.4

Input HIGH Voltage

2.2

+ 0.3

Input LOW Voltage

(1)

0.3

0.8

Input Leakage

GND

µA

Output Leakage

GND

OUT

, Outputs Disabled

µA

Note:
1. V

(min.) = 0.3V DC; V

(min.) = 2.0V AC (pulse width

2.0 ns).

(max.) = V

+ 0.3V DC; V

(max.) = V

+ 2.0V AC (pulse width

2.0 ns).

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

Power Supply Voltage Relative to GND

0.5 to 5.0

TERM

Terminal Voltage with Respect to GND

0.5 to Vcc + 0.5

STG

Storage Temperature

65 to + 150

°C

BIAS

Temperature Under Bias:

Com.

10 to + 85

°C

Ind.

45 to + 90

°C

Power Dissipation

2.0

OUT

DC Output Current

±20

Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

TRUTH TABLE

Mode

CE1

CE2

I/O0-I/O23

Vcc Current

Not Selected

High-Z

, I

Output Disabled

High-Z

Read

OUT

Write

IS61LV12824

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
04/17/01

CAPACITANCE

(1)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Input/Output Capacitance

OUT

= 0V

Note:
1. Tested initially and after any design or process changes that may affect these parameters.

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns

-9 ns

-10 ns

-12 ns

Symbol Parameter

Test Conditions

Min. Max.

Unit

Vcc Dynamic Operating V

= Max.,

Com.

210

200

180

170

Supply Current

OUT

= 0 mA, f = f

MAX

Ind.

220

210

190

TTL Standby Current

= Max.,

Com.

(TTL Inputs)

= V

or V

, f = max.

Ind.

CE1, CE2,

, CE2

CMOS Standby

= Max.,

Com.

Current (CMOS Inputs)

CE1, CE2

0.2V,

Ind.

CE2

0.2V, V

0.2V,

or V

0.2V, f = 0

Note:
1. At f = f

MAX

, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

2 ns

Input and Output Timing

1.5V

and Reference Level

Output Load

See Figures 1 and 2

AC TEST LOADS

Figure 1

Figure 2

319

5 pF

Including

jig and

scope

353

OUTPUT

3.3V

OUTPUT

= 50

1.5V

IS61LV12824

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

04/17/01

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-8

-9

-10

-12

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Read Cycle Time

Address Access Time

OHA

Output Hold Time

ACE

CE1, CE2 Access Time

ACE

CE2 Access Time

DOE

OE Access Time

HZOE

(2)

OE to High-Z Output

LZOE

(2)

OE to Low-Z Output

HZCE

(2)

CE1, CE2 to High-Z Output

HZCE

(2)

CE2 to High-Z Output

LZCE

(2)

CE, CE2 to Low-Z Output

LZCE

(2)

CE2 to Low-Z Output

Notes:
1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and

output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.

IS61LV12824

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
04/17/01

READ CYCLE NO. 2

(1,3)

AC WAVEFORMS

READ CYCLE NO. 1

(1,2)

(Address Controlled) (

CE1 = CE2 = OE = V

; CE2 = V

)

Notes:
1.

WE is HIGH for a Read Cycle.

2. The device is continuously selected.

OE, CE1, CE2 = V

. CE2 = V

3. Address is valid prior to or coincident with

CE1, CE2 LOW and CE2 HIGH transition.

DATA VALID

READ1.eps

PREVIOUS DATA VALID

OHA

OUT

ADDRESS

OHA

DOE

LZOE

ACS1

ACS2

LZCS1

LZCS2

HZOE

HIGH-Z

DATA VALID

ADDRESS

CS1

CS2

OUT

HZCS1

HZCS2

CS2_RD2.eps

IS61LV12824

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

04/17/01

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,3)

(Over Operating Range)

-8

-9

-10

-12

Symbol Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Write Cycle Time

SCE

CE1, CE2 to Write End

SCE

CE2 to Write End

Address Setup Time

to Write End

Address Hold from Write End

Address Setup Time

PWE

WE Pulse Width (OE = HIGH) 6

PWE

WE Pulse Width (OE = LOW)

Data Setup to Write End

4.5

Data Hold from Write End

HZWE

(2)

WE LOW to High-Z Output

3.5

LZWE

(2)

WE HIGH to Low-Z Output

Notes:
1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V

and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of

CE1, CE2 LOW, CE2 HIGH and WE LOW. All signals must be in valid

states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.

IS61LV12824

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
04/17/01

WRITE CYCLE NO. 1

(

CE Controlled, OE = HIGH or LOW)

WRITE CYCLE NO. 2

(1)

(

WE Controlled: OE = HIGH during Write Cycle)

DATA UNDEFINED

VALID ADDRESS

SCE1

SCE2

PWE1

PWE2

HIGH-Z

HZWE

ADDRESS

CE1

CE2

OUT

DATA

VALID

LZWE

CE2_WR1.eps

DATA UNDEFINED

LOW

VALID ADDRESS

PWE1

HIGH-Z

HZWE

ADDRESS

CE1

OUT

DATA

VALID

LZWE

HIGH

CE2

CE2_WR2.eps

IS61LV12824

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

04/17/01

WRITE CYCLE NO. 3

(1)

(

WE Controlled: OE

LOW

DURING

RITE

YLE

)

Note:
1. The internal Write time is defined by the overlap of

CE1 and CE2 = LOW, CE2 = HIGH and WE = LOW. All signals must be

in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is
referenced to the rising or falling edge of the signal that terminates the Write.

DATA UNDEFINED

VALID ADDRESS

LOW

PWE2

HIGH-Z

HZWE

ADDRESS

CE1

OUT

DATA

VALID

LZWE

HIGH

CE2

CE2_WR3.eps

IS61LV12824

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
04/17/01

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed (ns) Order Part No.

Package

IS61LV12824-8B

Plastic Ball Grid Array

IS61LV12824-8TQ

TQFP

IS61LV12824-9B

Plastic Ball Grid Array

IS61LV12824-9TQ

TQFP

IS61LV12824-10B

Plastic Ball Grid Array

IS61LV12824-10TQ

TQFP

IS61LV12824-12B

Plastic Ball Grid Array

IS61LV12824-12TQ

TQFP

ORDERING INFORMATION

Industrial Range: 40°C to +85°C

Speed (ns) Order Part No.

Package

IS61LV12824-9BI

Plastic Ball Grid Array

IS61LV12824-9TQI

TQFP

IS61LV12824-10BI

Plastic Ball Grid Array

IS61LV12824-10TQI

TQFP

IS61LV12824-12BI

Plastic Ball Grid Array

IS61LV12824-12TQI

TQFP

ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: 1-800-379-4774
Fax: (408) 588-0806

E-mail: sales@issi.com

www.issi.com

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