Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. I
11/09/99

IS61LV256

ISSI

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.

FEATURES

· High-speed access times:

-- 8, 10, 12, 15, 20 ns

· Automatic power-down when chip is deselected

· CMOS low power operation

-- 345 mW (max.) operating

-- 7 mW (max.) CMOS standby

· TTL compatible interface levels

· Single 3.3V power supply

· Fully static operation: no clock or refresh

required

· Three-state outputs

DESCRIPTION

The

ISSI

IS61LV256 is a very high-speed, low power,

32,768-word by 8-bit static RAM. It is fabricated using

ISSI

's high-performance CMOS technology. This highly

reliable process coupled with innovative circuit design
techniques, yields access times as fast as 8 ns maximum.

When

is HIGH (deselected), the device assumes a

standby mode at which the power dissipation is reduced to
50 µW (typical) with CMOS input levels.

Easy memory expansion is provided by using an active
LOW Chip Enable (

). The active LOW Write Enable

(

) controls both writing and reading of the memory.

The IS61LV256 is available in the JEDEC standard 28-pin,
300-mil SOJ and the 450-mil TSOP (Type I) package.

32K x 8 LOW VOLTAGE
CMOS STATIC RAM

OCTOBER 1999

FUNCTIONAL BLOCK DIAGRAM

A0-A14

256 X 1024

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

IS61LV256

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. I

11/09/99

PIN CONFIGURATION

28-Pin SOJ

22
23
24
25
26
27
28
1
2
3
4
5
6
7

21
20
19
18
17
16
15
14
13
12
11
10

9
8

A11

A9
A8

A13

VCC

A14
A12

A7
A6
A5
A4
A3

A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2

A14

A12

I/O0

I/O1

I/O2

GND

VCC

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

PIN CONFIGURATION

28-Pin TSOP (Type I)

PIN DESCRIPTIONS

A0-A14

Address Inputs

Chip Enable Input

Output Enable Input

Write Enable Input

I/O0-I/O7

Input/Output

Vcc

Power

GND

Ground

TRUTH TABLE

Mode

I/O Operation

Vcc Current

Not Selected

High-Z

, I

(Power-down)

Output Disabled

High-Z

Read

OUT

Write

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

Power Supply Voltage Relative to GND

0.5 to +4.6

TERM

Terminal Voltage with Respect to GND

0.5 to +4.6

BIAS

Temperature Under Bias

Com.

10 to +85

°C

Ind.

45 to +90

STG

Storage Temperature

65 to +150

°C

Power Dissipation

OUT

DC Output Current

±20

Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.

IS61LV256

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. I
11/09/99

DC ELECTRICAL CHARACTERISTICS

(Over Operating Range)

Symbol Parameter

Test Conditions

Min.

Max.

Unit

Output HIGH Voltage

= Min., I

= 2.0 mA

2.4

Output LOW Voltage

= Min., I

= 4.0 mA

0.4

Input HIGH Voltage

2.2

+ 0.3

Input LOW Voltage

(1)

0.3

0.8

Input Leakage

GND

Com.

µA

Ind.

Output Leakage

GND

OUT

, Outputs Disabled

Com.

µA

Ind.

Notes:
1. V

(min.) = 0.3V (DC); V

(min.) = 2.0V (pulse width

2.0 ns).

(max.) = V

+ 0.5V (DC); V

(max.) = Vcc + 2.0V (pulse width

2.0 ns).

2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

CAPACITANCE

(1,2)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T

= 25°C, f = 1 MHz, Vcc = 3.3V.

OPERATING RANGE

Range

Ambient Temperature

Speed

Commercial

0°C to +70°C

8, 10, 12

3.3V, +10%, 5%

15, 20

3.3V ± 10%

Industrial

40°C to +85°C

All

3.3V + 10%, 5%

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns

(2)

-10 ns

(2)

-12 ns

-15 ns

-20 ns

Sym. Parameter

Test Conditions

Min. Max.

Unit

Vcc Dynamic Operating

= Max.,

= V

Com.

-- 120

-- 110

-- 100

-- 90

-- 80

Supply Current

OUT

= 0 mA, f = f

MAX

Ind.

-- --

-- 120

-- 110

-- 100

-- 90

TTL Standby Current

= Max.,

Com.

-- 15

-- 10

(TTL Inputs)

= V

or V

Ind.

-- --

-- 20

, f = 0

CMOS Standby

= Max.,

Com.

Current (CMOS Inputs)

0.2V,

Ind.

-- --

> V

0.2V, or

0.2V, f = 0

Notes:
1. At f = f

MAX

, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

2. Shaded area = PREPRODUCTION AVAILABILITY.

IS61LV256

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. I

11/09/99

AC TEST LOADS

Figure 1.

Figure 2.

AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

3 ns

Input and Output Timing

1.5V

and Reference Levels

Output Load

See Figures 1 and 2

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns

(2)

-10 ns

(2)

-12 ns

-15 ns

-20 ns

Symbol

Parameter

Min. Max.

Unit

Read Cycle Time

Address Access Time

OHA

Output Hold Time

ACE

Access Time

DOE

Access Time

LZOE

(3)

to Low-Z Output

HZOE

(3)

to High-Z Output

LZCE

(3)

to Low-Z Output

HZCE

(3)

to High-Z Output

(4)

to Power-Up

(4)

to Power-Down

Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse

levels of 0 to 3.0V and output loading specified in Figure 1.

2. Shaded area = PREPRODUCTION AVAILABILITY.
3. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100%

tested.

4. Not 100% tested.

319

30 pF

Including

jig and

scope

353

OUTPUT

3.3V

319

5 pF

Including

jig and

scope

353

OUTPUT

3.3V

IS61LV256

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. I
11/09/99

DATA VALID

READ1.eps

PREVIOUS DATA VALID

OHA

OUT

ADDRESS

OHA

DOE

LZOE

ACE

LZCE

HZOE

HIGH-Z

DATA VALID

CE_RD2.eps

ADDRESS

OUT

HZCE

READ CYCLE NO. 2

(1,3)

Notes:
1.

is HIGH for a Read Cycle.

2. The device is continuously selected.

= V

3. Address is valid prior to or coincident with

LOW transitions.

AC WAVEFORMS

READ CYCLE NO. 1

(1,2)

IS61LV256

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. I

11/09/99

AC WAVEFORMS

WRITE CYCLE NO. 1

(

Controlled,

is HIGH or LOW)

(1 )

DATA UNDEFINED

VALID ADDRESS

SCE

PWE1

PWE2

HIGH-Z

HZWE

ADDRESS

OUT

DATA

VALID

LZWE

CE_WR1.eps

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,2)

(Over Operating Range)

-8 ns

(3)

-10 ns

(3)

-12 ns

-15 ns

-20 ns

Symbol

Parameter

Min. Max.

Unit

Write Cycle Time

SCE

to Write End

6.5

Address Setup Time

6.5

to Write End

Address Hold

from Write End

Address Setup Time

PWE

Pulse Width (

HIGH)

6.5

PWE

Pulse Width (

LOW)

Data Setup to Write End

Data Hold from Write End

HZWE

(4)

LOW to High-Z Output

3.5

LZWE

(4)

HIGH to Low-Z Output

Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse

levels of 0 to 3.0V and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of

LOW and

LOW. All signals must be in valid states

to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing
are referenced to the rising or falling edge of the signal that terminates the Write.

3. Shaded area = PREPRODUCTION AVAILABILITY.
4. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%

tested.

IS61LV256

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. I
11/09/99

DATA UNDEFINED

LOW

VALID ADDRESS

PWE1

HIGH-Z

HZWE

ADDRESS

OUT

DATA

VALID

LZWE

CE_WR2.eps

WRITE CYCLE NO. 2

(

Controlled,

is HIGH During Write Cycle)

(1,2)

WRITE CYCLE NO. 3

(

Controlled,

is LOW During Write Cycle)

(1)

DATA UNDEFINED

VALID ADDRESS

LOW

PWE2

HIGH-Z

HZWE

ADDRESS

OUT

DATA

VALID

LZWE

CE_WR3.eps

Notes:
1. The internal write time is defined by the overlap of

LOW and

LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if

· V

IS61LV256

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. I

11/09/99

ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: 1-800-379-4774
Fax: (408) 588-0806

E-mail: sales@issi.com

www.issi.com

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed (ns)

Order Part No.

Package

IS61LV256-8T

TSOP - Type I

IS61LV256-8J

300-mil Plastic SOJ

IS61LV256-10T

TSOP - Type I

IS61LV256-10J

300-mil Plastic SOJ

IS61LV256-12T

TSOP - Type I

IS61LV256-12J

300-mil Plastic SOJ

IS61LV256-15T

TSOP - Type I

IS61LV256-15J

300-mil Plastic SOJ

IS61LV256-15T

TSOP - Type I

IS61LV256-20J

300-mil Plastic SOJ

ORDERING INFORMATION

Industrial Range: 40°C to +85°C

Speed (ns)

Order Part No.

Package

IS61LV256-10TI

TSOP - Type I

IS61LV256-10JI

300-mil Plastic SOJ

IS61LV256-12TI

TSOP - Type I

IS61LV256-12JI

300-mil Plastic SOJ

IS61LV256-15TI

TSOP - Type I

IS61LV256-15JI

300-mil Plastic SOJ

IS61LV256-20TI

TSOP - Type I

IS61LV256-20JI

300-mil Plastic SOJ

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