Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
09/29/00

IS61LV25616

ISSI

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.

FEATURES

· High-speed access time:

-- 7, 8, 10, 12, and 15 ns

· CMOS low power operation

· Low stand-by power:

-- Less than 5 m

(typ.) CMOS stand-by

· TTL compatible interface levels

· Single 3.3V power supply

· Fully static operation: no clock or refresh

required

· Three state outputs

· Data control for upper and lower bytes

· Industrial temperature available

256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY

DESCRIPTION

The

ISSI

IS61LV25616 is a high-speed, 4,194,304-bit static

RAM organized as 262,144 words by 16 bits. It is fabricated
using

ISSI

's high-performance CMOS technology. This highly

reliable process coupled with innovative circuit design tech-
niques, yields high-performance and low power consumption
devices.

When

CE is HIGH (deselected), the device assumes a standby

mode at which the power dissipation can be reduced down
with CMOS input levels.

Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,

CE and OE. The active LOW Write

Enable (

WE) controls both writing and reading of the memory.A

data byte allows Upper Byte (

UB) and Lower Byte (LB) access.

The IS61LV25616 is packaged in the JEDEC standard
44-pin 400-mil SOJ, 44-pin TSOP Type II, 44-pin LQFP and
48-pin Mini BGA (8mm x 10mm).

FUNCTIONAL BLOCK DIAGRAM

A0-A17

256K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

AUGUST 2000

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

09/29/00

IS61LV25616

ISSI

PIN DESCRIPTIONS

A0-A17

Address Inputs

I/O0-I/O15

Data Inputs/Outputs

Chip Enable Input

Output Enable Input

Write Enable Input

Lower-byte Control (I/O0-I/O7)

Upper-byte Control (I/O8-I/O15)

No Connection

Vcc

Power

GND

Ground

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A0
A1
A2
A3
A4

I/O0
I/O1
I/O2
I/O3

Vcc

GND

I/O4
I/O5
I/O6
I/O7

A5
A6
A7
A8
A9

A17
A16
A15
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10

1
2
3
4
5
6
7
8
9
10
11

33
32
31
30
29
28
27
26
25
24
23

12 13 14 15 16 17 18 19 20 21 22

44 43 42 41 40 39 38 37 36 35 34

I/O0
I/O1
I/O2
I/O3

Vcc

GND

I/O4
I/O5
I/O6
I/O7

I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC

TOP VIEW

A17

A16

A15

A14

A13

A12

A11

A10

PIN CONFIGURATIONS

44-Pin TSOP (Type II) and SOJ

44-Pin LQFP

1 2 3 4 5 6

N/C

I/O

GND

I/O

A17

I/O

Vcc

I/O

A16

I/O

GND

I/O

A14

A15

I/O

A12

A13

I/O

A10

A11

48-Pin mini BGA

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
09/29/00

IS61LV25616

ISSI

TRUTH TABLE

I/O PIN

Mode

I/O0-I/O7

I/O8-I/O15

Vcc Current

Not Selected

High-Z

, I

Output Disabled

High-Z

Read

OUT

High-Z

OUT

Write

High-Z

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter

Value

Unit

TERM

Terminal Voltage with Respect to GND

0.5 to Vcc+0.5

BIAS

Temperature Under Bias

45 to +90

°C

Vcc Related to GND

0.3 to +4.0

STG

Storage Temperature

65 to +150

°C

Power Dissipation

1.0

Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

OPERATING RANGE

7, 8, 10 ns

12 ns, 15 ns

Range

Ambient Temperature

Commercial

0°C to +70°C

3.3V +10%, -5%

3.3V ± 10%

Industrial

40°C to +85°C

3.3V +10%, -5%

3.3V ± 10%

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

09/29/00

IS61LV25616

ISSI

CAPACITANCE

(1)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Input/Output Capacitance

OUT

= 0V

Note:

1. Tested initially and after any design or process changes that may affect these parameters.

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-7, -8

-10

-12

-15

Symbol

Parameter

Test Conditions

Min. Max.

Unit

Vcc Dynamic Operating

= Max.,

Com.

260

240

220

Supply Current

OUT

= 0 mA, f = f

MAX

Ind.

300

280

250

TTL Standby Current

= Max.,

Com.

(TTL Inputs)

= V

or V

Ind.

, f = f

MAX

TTL Standby Current

= Max.,

Com.

(TTL Inputs)

= V

or V

Ind.

, f = 0

CMOS Standby

= Max.,

Com.

Current (CMOS Inputs)

0.2V,

Ind.

0.2V, or

0.2V, f = 0

Note:
1. At f = f

MAX

, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

Shaded area product in development

DC ELECTRICAL CHARACTERISTICS

(Over Operating Range)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

Output HIGH Voltage

= Min., I

= 4.0 mA

2.4

Output LOW Voltage

= Min., I

= 8.0 mA

0.4

Input HIGH Voltage

2.0

+ 0.3

Input LOW Voltage

(1)

0.3

0.8

Input Leakage

GND

Com.

µA

Ind.

Output Leakage

GND

OUT

, 4

Com.

µA

Outputs Disabled

Ind.

Notes:
1. V

(min.) = 2.0V for pulse width less than 10 ns.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
09/29/00

IS61LV25616

ISSI

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-7

-8

-10

-12

-15

Symbol

Parameter

Min. Max.

Unit

Read Cycle Time

Address Access Time

OHA

Output Hold Time

ACE

CE Access Time

DOE

OE Access Time

3.5

HZOE

(2)

OE to High-Z Output

2.5

LZOE

(2)

OE to Low-Z Output

HZCE

CE to High-Z Output

LZCE

(2)

CE to Low-Z Output

2.5

LB, UB Access Time

3.5

HZB

(2)

LB, UB to High-Z Output

2.5

LZB

(2)

LB, UB to Low-Z Output

Power Up Time

Power Down Time

Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V,

input pulse levels of 0V to 3.0V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
Shaded area product in development

AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

3 ns

Input and Output Timing

1.5V

and Reference Level

Output Load

See Figures 1 and 2

AC TEST LOADS

Figure 1

Figure 2

319

5 pF

Including

jig and

scope

353

OUTPUT

3.3V

= 50

1.5V

OUTPUT

30 pF
Including
jig and
scope

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

09/29/00

IS61LV25616

ISSI

DATA VALID

READ1.eps

PREVIOUS DATA VALID

OHA

OUT

ADDRESS

OHA

DOE

LZOE

ACE

LZCE

HZOE

HIGH-Z

DATA VALID

UB_CEDR2.eps

HZB

ADDRESS

LB, UB

OUT

HZCE

LZB

50%

Supply

Current

50%

READ CYCLE NO. 2

(1,3)

AC WAVEFORMS

READ CYCLE NO. 1

(1,2)

(Address Controlled) (

CE = OE = V

UB or LB = V

)

Notes:
1.

WE is HIGH for a Read Cycle.

2. The device is continuously selected.

OE, CE, UB, or LB = V

3. Address is valid prior to or coincident with

CE LOW transition.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
09/29/00

IS61LV25616

ISSI

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,3)

(Over Operating Range)

-7

-8

-10

-12

-15

Symbol

Parameter

Min. Max.

Unit

Write Cycle Time

SCE

CE to Write End

5.5

Address Setup Time

5.5

to Write End

Address Hold from Write End

Address Setup Time

PWB

LB, UB Valid to End of Write

5.5

PWE

WE Pulse Width

5.5

PWE

WE Pulse Width (OE = LOW)

Data Setup to Write End

3.5

Data Hold from Write End

HZWE

(2)

WE LOW to High-Z Output

3.5

LZWE

(2)

WE HIGH to Low-Z Output

Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and

output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of

CE LOW and UB or LB, and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.

Shaded area product in development

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

09/29/00

IS61LV25616

ISSI

Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the

CE and WE inputs and at least one of

the

LB and UB inputs being in the LOW state.

2. WRITE = (

CE)

[

(

LB) = (UB)

]

(

WE).

AC WAVEFORMS

WRITE CYCLE NO. 1

(

CE Controlled, OE is HIGH or LOW)

(1 )

DATA UNDEFINED

VALID ADDRESS

SCE

PWE1

PWE2

HIGH-Z

PBW

HZWE

ADDRESS

UB, LB

OUT

DATA

VALID

LZWE

UB_CEWR1.eps

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
09/29/00

IS61LV25616

ISSI

AC WAVEFORMS

WRITE CYCLE NO. 2

(

WE Controlled. OE is HIGH During Write Cycle)

(1,2)

DATA UNDEFINED

LOW

VALID ADDRESS

PWE1

HIGH-Z

PBW

HZWE

ADDRESS

UB, LB

OUT

DATA

VALID

LZWE

UB_CEWR2.eps

WRITE CYCLE NO. 3

(

WE Controlled. OE is LOW During Write Cycle)

(1)

DATA UNDEFINED

VALID ADDRESS

LOW

PWE2

HIGH-Z

PBW

HZWE

ADDRESS

UB, LB

OUT

DATA

VALID

LZWE

UB_CEWR3.eps

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

09/29/00

IS61LV25616

ISSI

AC WAVEFORMS

WRITE CYCLE NO. 4

(

LB, UB Controlled, Back-to-Back Write)

(1,3)

DATA UNDEFINED

ADDRESS 1

ADDRESS 2

HIGH-Z

PBW

WORD 1

LOW

WORD 2

UB_CEWR4.eps

HZWE

ADDRESS

UB, LB

OUT

DATA

VALID

LZWE

PBW

DATA

VALID

Notes:
1. The internal Write time is defined by the overlap of

CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid

states to initiate a Write, but any can be deasserted to terminate the Write. The

, and

timing is referenced to the

rising or falling edge of the signal that terminates the Write.

2. Tested with

OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.

WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
09/29/00

IS61LV25616

ISSI

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed

Order Part No.

Package

(ns)

IS61LV25616-7T

TSOP (Type II)

IS61LV25616-7K

400-mil SOJ

IS61LV25616-7LQ

LQFP

IS61LV25616-7B

Mini BGA (8mm x 10mm)

IS61LV25616-8T

TSOP (Type II)

IS61LV25616-8K

400-mil SOJ

IS61LV25616-8LQ

LQFP

IS61LV25616-8B

Mini BGA (8mm x 10mm)

IS61LV25616-10T

TSOP (Type II)

IS61LV25616-10K

400-mil SOJ

IS61LV25616-10LQ

LQFP

IS61LV25616-10B

Mini BGA (8mm x 10mm)

IS61LV25616-12T

TSOP (Type II)

IS61LV25616-12K

400-mil SOJ

IS61LV25616-12LQ

LQFP

IS61LV25616-12B

Mini BGA (8mm x 10mm)

IS61LV25616-15T

TSOP (Type II)

IS61LV25616-15K

400-mil SOJ

IS61LV25616-15LQ

LQFP

IS61LV25616-15B

Mini BGA (8mm x 10mm)

Shaded area product in development

Industrial Range: 40°C to +85°C

Speed

Order Part No.

Package

(ns)

IS61LV25616-8TI

TSOP (Type II)

IS61LV25616-8KI

400-mil SOJ

IS61LV25616-8LQI

LQFP

IS61LV25616-8BI

Mini BGA (8mm x 10mm)

IS61LV25616-10TI

TSOP (Type II)

IS61LV25616-10KI

400-mil SOJ

IS61LV25616-10LQI

LQFP

IS61LV25616-10BI

Mini BGA (8mm x 10mm)

IS61LV25616-12TI

TSOP (Type II)

IS61LV25616-12KI

400-mil SOJ

IS61LV25616-12LQI

LQFP

IS61LV25616-12BI

Mini BGA (8mm x 10mm)

IS61LV25616-15TI

TSOP (Type II)

IS61LV25616-15KI

400-mil SOJ

IS61LV25616-15LQI

LQFP

IS61LV25616-15BI

Mini BGA (8mm x 10mm)

Shaded area product in development

ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: 1-800-379-4774
Fax: (408) 588-0806

E-mail: sales@issi.com

www.issi.com

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