Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A
02/21/03

IS61LV25616AL

ISSI

Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.

FEATURES

· High-speed access time:

-- 10, 12 ns

· CMOS low power operation

· Low stand-by power:

-- Less than 5 m

(typ.) CMOS stand-by

· TTL compatible interface levels

· Single 3.3V power supply

· Fully static operation: no clock or refresh

required

· Three state outputs

· Data control for upper and lower bytes

· Industrial temperature available

256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY

DESCRIPTION

The

ISSI

IS61LV25616AL is a high-speed, 4,194,304-bit

static RAM organized as 262,144 words by 16 bits. It is
fabricated using

ISSI

's high-performance CMOS technol-

ogy. This highly reliable process coupled with innovative
circuit design techniques, yields high-performance and low
power consumption devices.

When

is HIGH (deselected), the device assumes a

standby mode at which the power dissipation can be
reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,

and

. The active LOW

Write Enable (

) controls both writing and reading of the

memory. A data byte allows Upper Byte (

) and Lower

Byte (

) access.

The IS61LV25616AL is packaged in the JEDEC standard
44-pin 400-mil SOJ, 44-pin TSOP Type II, 44-pin LQFP and
48-pin Mini BGA (8mm x 10mm).

FUNCTIONAL BLOCK DIAGRAM

A0-A17

256K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VDD

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

FEBRUARY 2003

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A

02/21/03

IS61LV25616AL

ISSI

TRUTH TABLE

I/O PIN

Mode

I/O0-I/O7

I/O8-I/O15

Current

Not Selected

High-Z

, I

Output Disabled

High-Z

Read

OUT

High-Z

OUT

Write

High-Z

PIN DESCRIPTIONS

A0-A17

Address Inputs

I/O0-I/O15

Data Inputs/Outputs

Chip Enable Input

Output Enable Input

Write Enable Input

Lower-byte Control (I/O0-I/O7)

Upper-byte Control (I/O8-I/O15)

No Connection

Power

GND

Ground

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A0
A1
A2
A3
A4

I/O0
I/O1
I/O2
I/O3

VDD

GND

I/O4
I/O5
I/O6
I/O7

A5
A6
A7
A8
A9

A17
A16
A15
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10

PIN CONFIGURATIONS

44-Pin TSOP (Type II) and SOJ

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A
02/21/03

IS61LV25616AL

ISSI

1
2
3
4
5
6
7
8
9
10
11

33
32
31
30
29
28
27
26
25
24
23

12 13 14 15 16 17 18 19 20 21 22

44 43 42 41 40 39 38 37 36 35 34

I/O0
I/O1
I/O2
I/O3

VDD

GND

I/O4
I/O5
I/O6
I/O7

I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC

TOP VIEW

A17

A16

A15

A14

A13

A12

A11

A10

1 2 3 4 5 6

N/C

I/O

GND

I/O

A17

I/O

A16

I/O

GND

I/O

A14

A15

I/O

A12

A13

I/O

A10

A11

48-Pin mini BGA

PIN CONFIGURATIONS

44-Pin LQFP

PIN DESCRIPTIONS

A0-A17

Address Inputs

I/O0-I/O15

Data Inputs/Outputs

Chip Enable Input

Output Enable Input

Write Enable Input

Lower-byte Control (I/O0-I/O7)

Upper-byte Control (I/O8-I/O15)

No Connection

Power

GND

Ground

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A

02/21/03

IS61LV25616AL

ISSI

DC ELECTRICAL CHARACTERISTICS

(Over Operating Range)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

Output HIGH Voltage

= Min., I

= 4.0 mA

2.4

Output LOW Voltage

= Min., I

= 8.0 mA

0.4

Input HIGH Voltage

2.0

+ 0.3

Input LOW Voltage

(1)

0.3

0.8

Input Leakage

GND

Com.

µA

Ind.

Output Leakage

GND

OUT

Com.

µA

Outputs Disabled

Ind.

Notes:
1. V

(min.) = 2.0V for pulse width less than 10 ns.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter

Value

Unit

TERM

Terminal Voltage with Respect to GND

0.5 to V

+0.5

STG

Storage Temperature

65 to +150

°C

Power Dissipation

1.0

Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

OPERATING RANGE

Range

Ambient Temperature

10ns

12ns

Commercial

0°C to +70°C

3.3V +10%, -5%

3.3V + 10%

Industrial

40°C to +85°C

3.3V +10%, -5%

3.3V + 10%

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A
02/21/03

IS61LV25616AL

ISSI

CAPACITANCE

(1)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Input/Output Capacitance

OUT

= 0V

Note:

1. Tested initially and after any design or process changes that may affect these parameters.

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-10

-12

Symbol Parameter

Test Conditions

Min. Max.

Unit

Dynamic Operating

= Max.,

Com.

100

Supply Current

OUT

= 0 mA, f = f

MAX

Ind.

110

100

TTL Standby Current

= Max.,

Com.

(TTL Inputs)

= V

or V

Ind.

, f = f

MAX

TTL Standby Current

= Max.,

Com.

(TTL Inputs)

= V

or V

Ind.

, f = 0

CMOS Standby

= Max.,

Com.

Current (CMOS Inputs)

0.2V,

Ind.

0.2V, or

0.2V, f = 0

Note:
1. At f = f

MAX

, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

Shaded area product in development

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A

02/21/03

IS61LV25616AL

ISSI

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-10

-12

Symbol

Parameter

Min. Max.

Unit

Read Cycle Time

Address Access Time

OHA

Output Hold Time

ACE

Access Time

DOE

Access Time

HZOE

(2)

to High-Z Output

LZOE

(2)

to Low-Z Output

HZCE

to High-Z Output

LZCE

(2)

to Low-Z Output

Access Time

HZB

(2)

to High-Z Output

LZB

(2)

to Low-Z Output

Power Up Time

Power Down Time

AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

3 ns

Input and Output Timing and Reference Level

1.5V

Output Load

See Figures 1 and 2

AC TEST LOADS

Figure 1

Figure 2

319

5 pF

Including

jig and

scope

353

OUTPUT

3.3V

Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels

of 0V to 3.0V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.

319

30 pF

Including

jig and

scope

353

OUTPUT

3.3V

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A
02/21/03

IS61LV25616AL

ISSI

DATA VALID

READ1.eps

PREVIOUS DATA VALID

OHA

OUT

ADDRESS

AC WAVEFORMS

READ CYCLE NO. 1

(1,2)

(Address Controlled) (

= V

)

OHA

DOE

LZOE

ACE

LZCE

HZOE

HIGH-Z

DATA VALID

UB_CEDR2.eps

HZB

ADDRESS

LB, UB

OUT

HZCE

LZB

50%

Supply

Current

50%

READ CYCLE NO. 2

(1,3)

Notes:
1.

is HIGH for a Read Cycle.

2. The device is continuously selected.

, or

= V

3. Address is valid prior to or coincident with

LOW transition.

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A

02/21/03

IS61LV25616AL

ISSI

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,3)

(Over Operating Range)

-10

-12

Symbol

Parameter

Min. Max.

Unit

Write Cycle Time

SCE

to Write End

Address Setup Time to Write End

Address Hold from Write End

Address Setup Time

PWB

Valid to End of Write

PWE

Pulse Width

PWE

Pulse Width (

= LOW)

Data Setup to Write End

Data Hold from Write End

HZWE

(2)

LOW to High-Z Output

LZWE

(2)

HIGH to Low-Z Output

Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of

0V to 3.0V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of

LOW and

and

LOW. All signals must be in

valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold
timing are referenced to the rising or falling edge of the signal that terminates the write.

OHA

DOE

LZOE

ACE

LZCE

HZOE

HIGH-Z

DATA VALID

UB_CEDR2.eps

HZB

ADDRESS

LB, UB

OUT

HZCE

LZB

50%

Supply

Current

50%

READ CYCLE NO. 2

(1,3)

Notes:
1.

is HIGH for a Read Cycle.

2. The device is continuously selected.

, or

= V

3. Address is valid prior to or coincident with

LOW transition.

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A
02/21/03

IS61LV25616AL

ISSI

WRITE CYCLE NO. 2

(

Controlled.

is HIGH During Write Cycle)

(1,2)

DATA UNDEFINED

LOW

VALID ADDRESS

PWE1

HIGH-Z

PBW

HZWE

ADDRESS

UB, LB

OUT

DATA

VALID

LZWE

UB_CEWR2.eps

Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the

and

inputs and at least one of

the

and

inputs being in the LOW state.

2. WRITE = (

)

[

(

) = (

)

]

(

AC WAVEFORMS

WRITE CYCLE NO. 1

(

Controlled,

is HIGH or LOW)

(1 )

DATA UNDEFINED

VALID ADDRESS

SCE

PWE1

PWE2

HIGH-Z

PBW

HZWE

ADDRESS

UB, LB

OUT

DATA

VALID

LZWE

UB_CEWR1.eps

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A

02/21/03

IS61LV25616AL

ISSI

AC WAVEFORMS

WRITE CYCLE NO. 3

(

Controlled.

is LOW During Write Cycle)

(1)

DATA UNDEFINED

VALID ADDRESS

LOW

PWE2

HIGH-Z

PBW

HZWE

ADDRESS

UB, LB

OUT

DATAIN VALID

LZWE

UB_CEWR3.eps

WRITE CYCLE NO. 4

(

Controlled, Back-to-Back Write)

(1,3)

DATA UNDEFINED

ADDRESS 1

ADDRESS 2

HIGH-Z

PBW

WORD 1

LOW

WORD 2

UB_CEWR4.eps

HZWE

ADDRESS

UB, LB

OUT

DATA

VALID

LZWE

PBW

DATA

VALID

Notes:
1. The internal Write time is defined by the overlap of

= LOW,

and/or

= LOW, and

= LOW. All signals must be in valid

states to initiate a Write, but any can be deasserted to terminate the Write. The

, and

timing is referenced to the

rising or falling edge of the signal that terminates the Write.

2. Tested with

HIGH for a minimum of 4 ns before

= LOW to place the I/O in a HIGH-Z state.

may be held LOW across many address cycles and the

pins can be used to control the Write function.

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A
02/21/03

IS61LV25616AL

ISSI

DATA RETENTION WAVEFORM

(

Controlled)

DATA RETENTION SWITCHING CHARACTERISTICS

(LL)

Symbol

Parameter

Test Condition

Options

Min.

Typ.

(1)

Max.

Unit

for Data Retention

See Data Retention Waveform

2.0

3.6

Data Retention Current

= 2.0V,

0.2V

Com.

Ind.

SDR

Data Retention Setup Time

See Data Retention Waveform

RDR

Recovery Time

See Data Retention Waveform

Note 1:

Typical values are measured at V

= 3.0V, T

= 25

C and not 100% tested.

- 0.2V

SDR

RDR

GND

1.65V

1.4V

Data Retention Mode

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A

02/21/03

IS61LV25616AL

ISSI

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed (ns)

Order Part No.

Package

IS61LV25616AL-10T

TSOP (Type II)

IS61LV25616AL-10K

400-mil SOJ

IS61LV25616AL-10LQ

LQFP

IS61LV25616AL-10B

Mini BGA (8mm x 10mm)

IS61LV25616AL-12T

TSOP (Type II)

IS61LV25616AL-12K

400-mil SOJ

IS61LV25616AL-12B

Mini BGA (8mm x 10mm)

Industrial Range: 40°C to +85°C

Speed (ns)

Order Part No.

Package

IS61LV25616AL-10TI

TSOP (Type II)

IS61LV25616AL-10KI

400-mil SOJ

IS61LV25616AL-10LQI

LQFP

IS61LV25616AL-10BI

Mini BGA (8mm x 10mm)

IS61LV25616AL-12TI

TSOP (Type II)

IS61LV25616AL-12KI

400-mil SOJ

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