Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
Rev. A
04/02/03
IS61LV2568L
IS61LV2568LL
ISSI
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
APRIL 2003
FEATURES
High-speed access time:
IS61LV2568L: 8, 10 ns
IS61LV2568LL: 12 ns
Operating Current:
IS61LV2568L: 50mA (typ.)
IS61LV2568LL: 30mA (typ.)
Standby Current:
IS61LV2568L: 700A (typ.)
IS61LV2568LL: 400A(typ.)
Multiple center power and ground pins for greater
noise immunity
Easy memory expansion with
CE
and
OE
options
CE
power-down
TTL compatible inputs and outputs
Single 3.3V power supply
Packages available:
36-pin 400-mil SOJ
44-pin TSOP (Type II)
36-ball mini BGA (6mm x 8mm)
DESCRIPTION
The
ISSI
IS61LV2568L/IS61LV2568LL is a very high-
speed, low power, 262,144-word by 8-bit CMOS static
RAM. The IS61LV2568L/IS61LV2568LL is fabricated
using
ISSI
's high-performance CMOS technology. This
highly reliable process coupled with innovative circuit
design techniques, yields higher performance and low
power consumption devices.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 36mW (max.) with CMOS input levels.
The S61LV2568L/IS61LV2568LL operates from a single
3.3V power supply and all inputs are TTL-compatible.
The S61LV2568L/IS61LV2568LL is available in 36-pin
400-mil SOJ, 44-pin TSOP (Type II), and 36-ball mini
BGA (6mm x 8mm) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A17
CE
OE
WE
256K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
256K x 8 HIGH-SPEED CMOS STATIC RAM
IS61LV2568L, IS61LV2568LL
ISSI
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. A
04/02/03
PIN DESCRIPTIONS
A0-A17
Address Inputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Bidirectional Ports
V
DD
Power
GND
Ground
NC
No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
A4
A3
A2
A1
A0
CE
I/O0
I/O1
V
DD
GND
I/O2
I/O3
WE
A17
A16
A15
A14
A13
NC
NC
NC
NC
NC
A5
A6
A7
A8
OE
I/O7
I/O6
GND
V
DD
I/O5
I/O4
A9
A10
A11
A12
NC
NC
NC
NC
44
43
42
41
44-Pin TSOP (Type II)
36 Ball mini BGA (6mm x 8mm)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
A0
A1
NC
A3
A6
A8
I/O4
A2
WE
A4
A7
I/O
0
I/O5
NC
A5
I/O
1
GND
V
DD
V
DD
GND
I/O6
NC
A17
I/O
2
I/O7
OE
CE
A16
A15
I/O
3
A9
A10
A11
A12
A13
A14
PIN CONFIGURATION
36-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A4
A3
A2
A1
A0
CE
I/O0
I/O1
V
DD
GND
I/O2
I/O3
WE
A17
A16
A15
A14
A13
NC
A5
A6
A7
A8
OE
I/O7
I/O6
GND
V
DD
I/O5
I/O4
A9
A10
A11
A12
NC
NC
IS61LV2568L, IS61LV2568LL
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
3
Rev. A
04/02/03
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
DD
Supply voltage with Respect to GND
0.5 to +4.0
V
V
TERM
Terminal Voltage with Respect to GND
0.5 to V
DD
+ 0.5
V
T
STG
Storage Temperature
65 to +150
C
P
D
Power Dissipation
1.0
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
TRUTH TABLE
Mode
WE
WE
WE
WE
WE
CE
CE
CE
CE
CE
OE
OE
OE
OE
OE
I/O Operation
V
DD
Current
Not Selected
X
H
X
High-Z
I
SB
1
, I
SB
2
(Power-down)
Output Disabled
H
L
H
High-Z
I
CC
Read
H
L
L
D
OUT
I
CC
Write
L
L
X
D
IN
I
CC
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
DD
= Min., I
OH
= 4.0 mA
2.4
--
V
V
OL
Output LOW Voltage
V
DD
= Min., I
OL
= 8.0 mA
--
0.4
V
V
IH
Input HIGH Voltage
(1)
2.0
V
DD
+ 0.3
V
V
IL
Input LOW Voltage
(1)
0.3
0.8
V
I
LI
Input Leakage
GND
V
IN
V
DD
1
1
A
I
LO
Output Leakage
GND
V
OUT
V
DD
, Outputs Disabled
1
1
A
Note:
1. V
IL
(min) = 0.3V (DC); V
IL
(min) = 2.0V (pulse width - 2.0 ns).
V
IH
(max) = V
DD
+ 0.3V (DC); V
IH
(max) = V
DD
+ 2.0V (pulse width - 2.0 ns).
OPERATING RANGE
Range
Ambient Temperature
V
DD
(8ns)
V
DD
(10 ns, 12 ns)
Commercial
0C to +70C
3.3V +10%,-5%
3.3V + 10%
Industrial
40C to +85C
3.3V +10%,-5%
3.3V + 10%
IS61LV2568L, IS61LV2568LL
ISSI
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. A
04/02/03
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
I/O
Input/Output Capacitance
V
OUT
= 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz, V
DD
= 3.3V.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
IS61LV2568L
-8 ns
-10 ns
Symbol
Parameter
Test Conditions
Min. Max.
Min. Max.
Unit
I
CC
V
DD
Operating
V
DD
= Max.,
CE
= V
IL
Com.
--
65
--
60
mA
Supply Current
I
OUT
= 0 mA, f = Max.
Ind.
--
70
--
65
typ.
(2)
--
50
--
50
I
SB
1
TTL Standby
V
DD
= Max.,
Com.
--
30
--
25
mA
Current
V
IN
= V
IH
or V
IL
Ind.
--
35
--
30
(TTL Inputs)
CE
V
IH
, f = max
I
SB
2
CMOS Standby
V
DD
= Max.,
Com.
--
3
--
3
mA
Current
CE
V
DD
0.2V,
Ind.
--
4
--
4
mA
(CMOS Inputs)
V
IN
V
DD
0.2V, or
typ.
(2)
--
700
--
700
A
V
IN
0.2V, f = 0
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at V
DD
=3.3V, T
A
=25
0
C. Not 100% tested.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
IS61LV2568LL
-12 ns
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
I
CC
V
DD
Operating
V
DD
= Max.,
CE
= V
IL
Com.
--
40
mA
Supply Current
I
OUT
= 0 mA, f = Max.
Ind.
--
45
typ.
(2)
--
30
@ 15ns
(3)
--
25
I
SB
1
TTL Standby
V
DD
= Max.,
Com.
--
20
mA
Current
V
IN
= V
IH
or V
IL
Ind.
--
25
(TTL Inputs)
CE
V
IH
, f = max
I
SB
2
CMOS Standby
V
DD
= Max.,
Com.
--
750
A
Current
CE
V
DD
0.2V,
Ind.
--
900
(CMOS Inputs)
V
IN
V
DD
0.2V, or
typ.
(2)
--
400
V
IN
0.2V, f = 0
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at V
DD
=3.3V, T
A
=25
O
C. Not 100% tested.
3. For 15ns speed (t
AA
), Icc is measured at V
DD
=3.3V, T
A
=25
O
C. Not 100% tested.
IS61LV2568L, IS61LV2568LL
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
Rev. A
04/02/03
AC TEST LOADS
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
3 ns
Input and Output Timing and Reference Levels
1.5V
Output Load
See Figures 1 and 2
319
5 pF
Including
jig and
scope
353
OUTPUT
3.3V
Figure 1
Figure 2
Z
O
= 50
1.5V
50
OUTPUT
30 pF
Including
jig and
scope
IS61LV2568L, IS61LV2568LL
ISSI
6
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. A
04/02/03
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
IS61LV2568LL
- 12 ns
Symbol
Parameter
Min.
Max
Unit
t
RC
Read Cycle Time
12
--
ns
t
AA
Address Access Time
--
12
ns
t
OHA
Output Hold Time
3
--
ns
t
ACE
CE
Access Time
--
12
ns
t
DOE
OE
Access Time
--
5
ns
t
LZOE
(2)
OE
to Low-Z Output
0
--
ns
t
HZOE
(2)
OE
to High-Z Output
0
5
ns
t
LZCE
(2)
CE
to Low-Z Output
3
--
ns
t
HZCE
(2)
CE
to High-Z Output
0
5
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested.
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
IS61LV2568L
- 8 ns
-10 ns
Symbol Parameter
Min.
Max
Min.
Max.
Unit
t
RC
Read Cycle Time
8
--
10
--
ns
t
AA
Address Access Time
--
8
--
10
ns
t
OHA
Output Hold Time
2.5
--
2.5
--
ns
t
ACE
CE
Access Time
--
8
--
10
ns
t
DOE
OE
Access Time
--
3.5
--
4
ns
t
LZOE
(2)
OE
to Low-Z Output
0
--
0
--
ns
t
HZOE
(2)
OE
to High-Z Output
0
3.5
0
4
ns
t
LZCE
(2)
CE
to Low-Z Output
3.5
--
3
--
ns
t
HZCE
(2)
CE
to High-Z Output
0
3.5
0
4
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested.
IS61LV2568L, IS61LV2568LL
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
7
Rev. A
04/02/03
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z
DATA VALID
CE_RD2.eps
ADDRESS
OE
CE
D
OUT
t
HZCE
READ CYCLE NO. 2
(1,3)
(
CE
and
OE
Controlled)
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE
,
CE
= V
IL
.
3. Address is valid prior to or coincident with
CE
LOW transitions.
READ CYCLE NO. 1
(1,2)
(Address Controlled) (
CE
=
OE
= V
IL
)
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
AC WAVEFORMS
IS61LV2568L, IS61LV2568LL
ISSI
8
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. A
04/02/03
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
IS61LV2568L
- 8 ns
-10 ns
Symbol
Parameter
Min.
Max
Min.
Max.
Unit
t
WC
Write Cycle Time
8
--
10
--
ns
t
SCE
CE
to Write End
7
--
8
--
ns
t
AW
Address Setup Time to Write End
7
--
8
--
ns
t
HA
Address Hold from Write End
0
--
0
--
ns
t
SA
Address Setup Time
0
--
0
--
ns
t
PWE
1
WE
Pulse Width (
OE
= HIGH)
6
--
7
--
ns
t
PWE
2
WE
Pulse Width (
OE
= LOW)
6.5
--
8
--
ns
t
SD
Data Setup to Write End
4
--
5
--
ns
t
HD
Data Hold from Write End
0
--
0
--
ns
t
HZWE
(3)
WE
LOW to High-Z Output
--
3
--
4
ns
t
LZWE
(3)
WE
HIGH to Low-Z Output
0
--
0
--
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
IS61LV2568L, IS61LV2568LL
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
9
Rev. A
04/02/03
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(
CE
Controlled,
OE
= HIGH or LOW)
Note:
1. The internal Write time is defined by the overlap of
CE
= LOW and
WE
= LOW. All signals must be in valid states to initiate a
Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or
falling edge of the signal that terminates the Write.
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
IS61LV2568LL
- 12ns
Symbol
Parameter
Min.
Max
Unit
t
WC
Write Cycle Time
12
--
ns
t
SCE
CE
to Write End
8
--
ns
t
AW
Address Setup Time to Write End
8
--
ns
t
HA
Address Hold from Write End
0
--
ns
t
SA
Address Setup Time
0
--
ns
t
PWE
1
WE
Pulse Width (
OE
= HIGH)
8
--
ns
t
PWE
2
WE
Pulse Width (
OE
= LOW)
10
--
ns
t
SD
Data Setup to Write End
6
--
ns
t
HD
Data Hold from Write End
0
--
ns
t
HZWE
(3)
WE
LOW to High-Z Output
--
5
ns
t
LZWE
(3)
WE
HIGH to Low-Z Output
0
--
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
CE_WR1.eps
IS61LV2568L, IS61LV2568LL
ISSI
10
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. A
04/02/03
AC WAVEFORMS
WRITE CYCLE NO. 2
(1)
(
WE
Controlled,
OE
= HIGH during Write Cycle)
WRITE CYCLE NO. 3
(
WE
Controlled:
OE
is LOW During Write Cycle)
Note:
1. The internal Write time is defined by the overlap of
CE
= LOW and
WE
= LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
Note:
1. The internal Write time is defined by the overlap of
CE
= LOW and
WE
= LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR2.eps
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR3.eps
IS61LV2568L, IS61LV2568LL
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
11
Rev. A
04/02/03
ORDERING INFORMATION
IS61LV2568L
Commercial Range: 0C to +70C
Speed (ns)
Order Part No.
Package
8
IS61LV2568L-8B
mini BGA (6mm x 8mm)
IS61LV2568L-8K
400-mil SOJ
IS61LV2568L-8T
TSOP (Type II)
10
IS61LV2568L-10T
TSOP (Type II)
IS61LV2568L
Industrial Range: 40C to +85C
Speed (ns)
Order Part No.
Package
8
IS61LV2568L-8BI
mini BGA (6mm x 8mm)
IS61LV2568L-8KI
400-mil SOJ
IS61LV2568L-8TI
TSOP (Type II)
10
IS61LV2568L-10BI
mini BGA (6mm x 8mm)
IS61LV2568L-10KI
400-mil SOJ
IS61LV2568L-10TI
TSOP (Type II)
IS61LV2568LL
Commercial Range: 0C to +70C
Speed (ns)
Order Part No.
Package
12
IS61LV2568LL-12T
TSOP (Type II)
IS61LV2568LL
Industrial Range: 40C to +85C
Speed (ns)
Order Part No.
Package
12
IS61LV2568LL-12BI
mini BGA (6mm x 8mm)
IS61LV2568LL-12KI
400-mil SOJ
IS61LV2568LL-12TI
TSOP (Type II)
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