Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A
02/25/03

IS61LV5128AL

ISSI

Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.

512K x 8 HIGH-SPEED CMOS STATIC RAM

FEBRUARY 2003

FEATURES

· High-speed access times:

10, 12 ns

· High-performance, low-power CMOS process

· Multiple center power and ground pins for

greater noise immunity

· Easy memory expansion with

and

options

power-down

· Fully static operation: no clock or refresh

required

· TTL compatible inputs and outputs

· Single 3.3V power supply

· Packages available:

36-pin 400-mil SOJ

36-pin miniBGA

44-pin TSOP (Type II)

DESCRIPTION

The

ISSI

IS61LV5128AL is a very high-speed, low power,

524,288-word by 8-bit CMOS static RAM. The
IS61LV5128AL is fabricated using

ISSI

's high-perform-

ance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
higher performance and low power consumption devices.

When

is HIGH (deselected), the device assumes a

standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.

The IS61LV5128AL operates from a single 3.3V power
supply and all inputs are TTL-compatible.

The IS61LV5128AL is available in 36-pin 400-mil SOJ, 36-
pin mini BGA, and 44-pin TSOP (Type II) packages.

FUNCTIONAL BLOCK DIAGRAM

A0-A18

512K X 8

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

I/O

DATA

CIRCUIT

I/O0-I/O7

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A

02/25/03

IS61LV5128AL

ISSI

PIN CONFIGURATION

36 mini BGA

PIN DESCRIPTIONS

A0-A18

Address Inputs

Chip Enable Input

Output Enable Input

Write Enable Input

I/O0-I/O7

Bidirectional Ports

Power

GND

Ground

No Connection

TRUTH TABLE

Mode

I/O Operation

Current

Not Selected

High-Z

, I

(Power-down)

Output Disabled H

High-Z

Read

OUT

Write

I/O0

I/O1

GND

I/O2

I/O3

A18

A17

A16

A15

I/O7

I/O6

GND

I/O5

I/O4

A14

A13

A12

A11

A10

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

NC
NC

A0
A1
A2
A3
A4

I/O0
I/O1

GND

I/O2
I/O3

A5
A6
A7
A8
A9

NC
NC

NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
V

I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC

44
43
42
41

44-Pin TSOP (Type II)

1 2 3 4 5 6

I/O4

I/O5

GND

I/O6

I/O7

A10

A18

A11

A17

A16

A12

A15

A13

I/O0

I/O1

GND

I/O2

I/O3

A14

36-Pin SOJ

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A
02/25/03

IS61LV5128AL

ISSI

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

TERM

Terminal Voltage with Respect to GND

0.5 to V

+ 0.5

STG

Storage Temperature

65 to +150

°C

Power Dissipation

1.0

Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-

nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

OPERATING RANGE

Range

Ambient Temperature

10ns

12ns

Commercial

0°C to +70°C

3.3V +10%, -5%

3.3V +10%

Industrial

-40°C to +85°C

3.3V +10%, -5%

3.3V +10%

CAPACITANCE

(1,2)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

I/O

Input/Output Capacitance

OUT

= 0V

Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T

= 25°C, f = 1 MHz, V

= 3.3V.

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A

02/25/03

IS61LV5128AL

ISSI

DC ELECTRICAL CHARACTERISTICS

(Over Operating Range)

Symbol Parameter

Test Conditions

Min.

Max.

Unit

Output HIGH Voltage

= Min., I

= 4.0 mA

2.4

Output LOW Voltage

= Min., I

= 8.0 mA

0.4

Input HIGH Voltage

2.0

+ 0.3

Input LOW Voltage

(1)

0.3

0.8

Input Leakage

GND

Com.

µA

Ind.

Output Leakage

GND

OUT

, Outputs Disabled

Com.

µA

Ind.

Note:
1. V

= 3.0V for pulse width less than 10 ns.

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-10

-12

Symbol Parameter

Test Conditions

Min. Max.

Unit

Dynamic Operating

= Max.,

Com.

Supply Current

OUT

= 0 mA, f = f

MAX

Ind.

TTL Standby Current

= Max.,

Com.

(TTL Inputs)

= V

or V

Ind.

, f = f

MAX

TTL Standby Current

= Max.,

Com.

(TTL Inputs)

= V

or V

Ind.

, f = 0

CMOS Standby

= Max.,

Com.

Current (CMOS Inputs)

0.2V,

Ind.

0.2V, or

0.2V, f = 0

Note:
1. At f = f

MAX

, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A
02/25/03

IS61LV5128AL

ISSI

AC TEST LOADS

AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

3 ns

Input and Output Timing

1.5V

and Reference Levels

Output Load

See Figures 1 and 2

Figure 1

Figure 2

319

30 pF

Including

jig and

scope

353

OUTPUT

3.3V

319

5 pF

Including

jig and

scope

353

OUTPUT

3.3V

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-10

-12

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

Read Cycle Time

Address Access Time

OHA

Output Hold Time

ACE

Access Time

DOE

Access Time

HZOE

(2)

to High-Z Output

LZOE

(2)

to Low-Z Output

HZCE

to High-Z Output

LZCE

(2)

to Low-Z Output

Power Up Time

Power Down Time

Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse

levels of 0V to 3.0V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A

02/25/03

IS61LV5128AL

ISSI

OHA

DOE

LZOE

ACE

LZCE

HZOE

HIGH-Z

DATA VALID

CE_RD2.eps

ADDRESS

OUT

HZCE

READ CYCLE NO. 2

(1,3)

(

and

Controlled)

Notes:
1.

is HIGH for a Read Cycle.

2. The device is continuously selected.

= V

3. Address is valid prior to or coincident with

LOW transitions.

AC WAVEFORMS
READ CYCLE NO. 1

(1,2)

(Address Controlled) (

= V

)

DATA VALID

READ1.eps

PREVIOUS DATA VALID

OHA

OUT

ADDRESS

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A
02/25/03

IS61LV5128AL

ISSI

AC WAVEFORMS

WRITE CYCLE NO. 1

(1,2)

(

Controlled,

= HIGH or LOW)

DATA UNDEFINED

VALID ADDRESS

SCE

PWE1

PWE2

HIGH-Z

HZWE

ADDRESS

OUT

DATA

VALID

LZWE

CE_WR1.eps

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,3)

(Over Operating Range)

-10

-12

Symbol

Parameter

Min. Max.

Unit

Write Cycle Time

SCE

to Write End

Address Setup Time

to Write End

Address Hold from Write End

Address Setup Time

PWE

Pulse Width

PWE

Pulse Width (

= LOW)

Data Setup to Write End

Data Hold from Write End

HZWE

(2)

LOW to High-Z Output

LZWE

(2)

HIGH to Low-Z Output

Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse

levels of 0V to 3.0V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of

LOW and

LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A

02/25/03

IS61LV5128AL

ISSI

Notes:
1. The internal write time is defined by the overlap of

LOW and

LOW. All signals must be in valid states to initiate a Write, but

any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.

2. I/O will assume the High-Z state if

DATA UNDEFINED

LOW

VALID ADDRESS

PWE1

HIGH-Z

HZWE

ADDRESS

OUT

DATA

VALID

LZWE

CE_WR2.eps

WRITE CYCLE NO. 2

(1,2)

(

Controlled:

is HIGH During Write Cycle)

WRITE CYCLE NO. 3

(

Controlled:

is LOW During Write Cycle)

DATA UNDEFINED

VALID ADDRESS

LOW

PWE2

HIGH-Z

HZWE

ADDRESS

OUT

DATA

VALID

LZWE

CE_WR3.eps

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A
02/25/03

IS61LV5128AL

ISSI

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed (ns)

Order Part No.

Package

IS61LV5128AL-10K

400-mil Plastic SOJ

IS61LV5128AL-10T

TSOP (Type II)

IS61LV5128AL-10B

mini BGA (8mmx10mm)

IS61LV5128AL-12K

400-mil Plastic SOJ

IS61LV5128AL-12T

TSOP (Type II)

Industrial Range: 40°C to +85°C

Speed (ns)

Order Part No.

Package

IS61LV5128AL-10KI

400-mil Plastic SOJ

IS61LV5128AL-10TI

TSOP (Type II)

IS61LV5128AL-10BI

mini BGA (8mmx10mm)

IS61LV5128AL-12KI

400-mil Plastic SOJ

IS61LV5128AL-12TI

TSOP (Type II)

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IS61LV5128AL-15BI

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IS61LV5128AL-15BI