61LV632A
IS61LV632A
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
1
Rev. A
04/17/01
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. Copyright 2001, Integrated Silicon Solution, Inc.
FEATURES
Fast access time:
4 ns-125 MHz; 5 ns-100 MHz;
6 ns-83 MHz; 7 ns-75 MHz; 8 ns-66 MHz
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
PentiumTM or linear burst sequence control
using MODE input
Three chip enables for simple depth expansion
and address pipelining
Common data inputs and data outputs
Power-down control by ZZ input
JEDEC 100-Pin TQFP and PQFP package
3.3V Vcc and 2.5V V
CCQ
for 2.5V I/Os
Two Clock enables and one Clock disable to
eliminate multiple bank bus contention.
Control pins mode upon power-up:
MODE in interleave burst mode
ZZ in normal operation mode
These control pins can be connected to GND
Q
or V
CCQ
to alter their power-up state
DESCRIPTION
The
ISSI
IS61LV632A is a high-speed, low-power synchro-
nous static RAM designed to provide a burstable, high-
performance, secondary cache for the i486TM, PentiumTM,
680X0TM, and PowerPCTM microprocessors. It is organized
as 32,768 words by 32 bits, fabricated with
ISSI
's advanced
CMOS technology. The device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs into
a single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQ1-DQ8,
BW2
controls DQ9-DQ16,
BW3
controls DQ17-DQ24,
BW4
controls DQ25-DQ32, conditioned
by
BWE
being LOW. A LOW on
GW
input would cause all bytes
to be written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated inter-
nally by the IS61LV632A and controlled by the
ADV
(burst
address advance) input pin.
Asynchronous signals include output enable (
OE
), sleep mode
input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH
input on the ZZ pin puts the SRAM in the power-down state.
When ZZ is pulled LOW (or no connect), the SRAM normally
operates after three cycles of the wake-up period. A LOW
input, i.e., GND
Q
, on MODE pin selects LINEAR Burst. A V
CCQ
(or no connect) on MODE pin selects INTERLEAVED Burst.
32K x 32 SYNCHRONOUS FAST STATIC RAM
APRIL 2001
IS61LV632A
ISSI
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A
04/17/01
BLOCK DIAGRAM
15
BINARY
COUNTER
A14-A0
BW1
GW
CLR
CE
CLK
Q0
Q1
MODE
A0'
A0
A1
A1'
CLK
ADV
ADSC
ADSP
13
15
ADDRESS
REGISTER
CE
D
CLK
Q
DQ32-DQ25
BYTE WRITE
REGISTERS
D
CLK
Q
DQ24-DQ17
BYTE WRITE
REGISTERS
D
CLK
Q
DQ16-DQ9
BYTE WRITE
REGISTERS
D
CLK
Q
DQ8-DQ1
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
CE
D
CLK
Q
ENABLE
DELAY
REGISTER
D
CLK
Q
BWE
BW4
CE1
CE3
CE2
BW2
BW3
32K x 32
MEMORY
ARRAY
32
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
32
OE
4
32
OE
DATA[32:1]
IS61LV632A
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
3
Rev. A
04/17/01
PIN CONFIGURATION
100-Pin TQFP and PQFP (Top View)
NC
DQ16
DQ15
VCCQ
GNDQ
DQ14
DQ13
DQ12
DQ11
GNDQ
VCCQ
DQ10
DQ9
GND
NC
VCC
ZZ
DQ8
DQ7
VCCQ
GNDQ
DQ6
DQ5
DQ4
DQ3
GNDQ
VCCQ
DQ2
DQ1
NC
A6
A7
CE1
CE2
BW4
BW3
BW2
BW1
CE3
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
NC
DQ17
DQ18
VCCQ
GNDQ
DQ19
DQ20
DQ21
DQ22
GNDQ
VCCQ
DQ23
DQ24
NC
VCC
NC
GND
DQ25
DQ26
VCCQ
GNDQ
DQ27
DQ28
DQ29
DQ30
GNDQ
VCCQ
DQ31
DQ32
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
NC
NC
46 47 48 49 50
PIN DESCRIPTIONS
A0-A14
Address Inputs
CLK
Clock
ADSP
Processor Address Status
ADSC
Controller Address Status
ADV
Burst Address Advance
BW1
-
BW4
Synchronous Byte Write Enable
BWE
Byte Write Enable
GW
Global Write Enable
CE1
, CE2,
CE3
Synchronous Chip Enable
OE
Output Enable
DQ1-DQ32
Data Input/Output
ZZ
Sleep Mode
MODE
Burst Sequence Mode
V
CC
+3.3V Power Supply
GND
Ground
V
CCQ
Isolated Output Buffer Supply:
+2.5V
GND
Q
Isolated Output Buffer Ground
IS61LV632A
ISSI
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A
04/17/01
TRUTH TABLE
ADDRESS
OPERATION
USED
CE1
CE2
CE3
ADSP ADSC
ADV WRITE
OE
DQ
Deselected, Power-down
None
H
X
X
X
L
X
X
X
High-Z
Deselected, Power-down
None
L
L
X
L
X
X
X
X
High-Z
Deselected, Power-down
None
L
X
H
L
X
X
X
X
High-Z
Deselected, Power-down
None
L
L
X
H
L
X
X
X
High-Z
Deselected, Power-down
None
L
X
H
H
L
X
X
X
High-Z
Read Cycle, Begin Burst External
L
H
L
L
X
X
X
L
Q
Read Cycle, Begin Burst External
L
H
L
L
X
X
X
H
High-Z
Write Cycle, Begin Burst External
L
H
L
H
L
X
L
X
D
Read Cycle, Begin Burst External
L
H
L
H
L
X
H
L
Q
Read Cycle, Begin Burst External
L
H
L
H
L
X
H
H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
Q
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
High-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
Q
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
High-Z
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
D
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
D
Read Cycle, Suspend Burst Current
X
X
X
H
H
H
H
L
Q
Read Cycle, Suspend Burst Current
X
X
X
H
H
H
H
H
High-Z
Read Cycle, Suspend Burst Current
H
X
X
X
H
H
H
L
Q
Read Cycle, Suspend Burst Current
H
X
X
X
H
H
H
H
High-Z
Write Cycle, Suspend Burst Current
X
X
X
H
H
H
L
X
D
Write Cycle, Suspend Burst Current
H
X
X
X
H
H
L
X
D
Notes:
1. All inputs except
OE
must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care.
WRITE
=L means any one or more byte write enable signals (
BW
1-
BW
4) and
BWE
are LOW or
GW
is LOW.
WRITE
=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation,
OE
must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5.
ADSP
LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and
BWE
LOW or
GW
LOW for the subsequent L-H edge of clock.
PARTIAL TRUTH TABLE
FUNCTION
GW
BWE
BW1
BW2
BW3
BW4
READ
H
H
X
X
X
X
READ
H
X
H
H
H
H
WRITE Byte 1
H
L
L
H
H
H
WRITE All Bytes
X
L
L
L
L
L
WRITE All Bytes
L
X
X
X
X
X
IS61LV632A
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
5
Rev. A
04/17/01
INTERLEAVED BURST ADDRESS TABLE (MODE = V
CCQ
or No Connect)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A1 A0
A1 A0
A1 A0
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GND
Q
)
0,0
1,0
0,1
A1', A0' = 1,1
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
T
BIAS
Temperature Under Bias
10 to +85
C
T
STG
Storage Temperature
55 to +150
C
P
D
Power Dissipation
1.8
W
I
OUT
Output Current (per I/O)
100
mA
V
IN
, V
OUT
Voltage Relative to GND for I/O Pins
0.5 to V
CCQ
+ 0.3
V
V
IN
Voltage Relative to GND for
0.5 to 4.6
V
for Address and Control Inputs
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
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