Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)

QUAD (Burst of 2) Synchronous SRAMs

Features

· 1M x 36 or 2M x 18.

· On-chip delay-locked loop (DLL) for wide data

valid window.

· Separate read and write ports with concurrent

read and write operations.

· Synchronous pipeline read with early write oper-

ation.

· Double data rate (DDR) interface for read and

write input ports.

· Fixed 2-bit burst for read and write operations.

· Clock stop support.

· Two input clocks (K and K) for address and con-

trol registering at rising edges only.

· Two input clocks (C and C) for data output con-

trol.

· Two echo clocks (

CQ and CQ) that are delivered

simultaneously with data.

· +1.8V core power supply and 1.5, 1.8V V

DDQ

used with 0.75, 0.9V V

REF

· HSTL input and output levels.

· Registered addresses, write and read controls,

byte writes, data in, and data outputs.

· Full data coherency.

· Boundary scan using limited set of JTAG 1149.1

functions.

· Byte write capability.

· Fine ball grid array (FBGA) package

- 15mm x 17mm body size
- 1mm pitch
- 165-ball (11 x 15) array

· Programmable impedance output drivers via 5x

user-supplied precision resistor.

Description

The 36Mb

IS61QDB21Mx36 and

IS61QDB22Mx18 are synchronous, high-perfor-
mance CMOS static random access memory
(SRAM) devices. These SRAMs have separate I/Os,
eliminating the need for high-speed bus turnaround.
The rising edge of K clock initiates the read/write
operation, and all internal operations are self-timed.
Refer to the Timing Reference Diagram for Truth
Table on page

8 for a description of the basic opera-

tions of these SRAMs.

The input address bus operates at double data rate.
The following are registered internally on the rising
edge of the K clock:

· Read address
· Read enable
· Write enable
· Byte writes
· Data-in for early writes

The following are registered on the rising edge of
the K clock:

· Write address
· Byte writes
· Data-in for second burst addresses

Byte writes can change with the corresponding data-
in to enable or disable writes on a per-byte basis. An
internal write buffer enables the data-ins to be regis-
tered half a cycle earlier than the write address. The
first data-in burst is clocked at the same time as the
write command signal, and the second burst is timed
to the following rising edge of the K clock.

During the burst read operation, the data-outs from
the first burst are updated from output registers off
the second rising edge of the C clock (1.5 cycles
later). The data-outs from the second burst are
updated with the third rising edge of the C clock. The
K and K clocks are used to time the data-outs when-
ever the C and C clocks are tied high.

The device is operated with a single +1.8V power
supply and is compatible with HSTL I/O interfaces.

JULY 2006

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

x36 FBGA Pinout

(Top View)

/SA

NC/SA*

/SA

Q27

Q18

D18

D17

Q17

D27

Q28

D19

D16

D28

D20

Q19

Q16

D15

Q29

D29

Q20

DDQ

Q15

Q30

Q21

D21

DDQ

D14

Q14

D30

D22

Q22

DDQ

Q13

D13

Doff

REF

DDQ

REF

D31

Q31

D23

DDQ

D12

Q32

D32

Q23

DDQ

Q12

Q33

Q24

D24

DDQ

D11

Q11

D33

Q34

D25

D10

D34

D26

Q25

Q10

Q35

D35

Q26

TDO

TCK

TMS

TDI

Note: The following pins are reserved for higher densities: A3 for 64Mb, 10A for 144Mb, and 2A for 288Mb.

x18 FBGA Pinout

(Top View)

/SA*

D10

D11

Q10

Q11

DDQ

Q12

D12

DDQ

D13

Q13

DDQ

Doff

REF

DDQ

REF

D14

DDQ

Q14

DDQ

Q15

D15

DDQ

D16

D17

Q16

Q17

TDO

TCK

TMS

TDI

Note: The following pins are reserved for higher densities: 10A for

72Mb and 2A for 144Mb.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

Pin Description

Symbol

Pin Number

Description

K, K

6B, 6A

Input clock.

C, C

6P, 6R

Input clock for output data control.

CQ, CQ

11A, 1A

Output echo clock.

Doff

DLL disable when low.

9A, 4B, 8B, 5C, 6C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R, 5R,
7R, 8R, 9R

1M x 36 address inputs.

3A, 9A, 4B, 8B, 5C, 6C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R,
5R, 7R, 8R, 9R

2M x 18 address inputs.

D0D8
D9D17

D18D26

D27D35

10P, 11N, 11M, 10K, 11J, 11G, 10E, 11D, 11C
10N, 9M, 9L, 9J, 10G, 9F, 10D, 9C, 9B

3B, 3C, 2D, 3F, 2G, 3J, 3L, 3M, 2N

1C, 1D, 2E, 1G, 1J, 2K, 1M, 1N, 2P

1M x 36 data inputs.

Q0Q8

Q9Q17

Q18Q26
Q27Q35

11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B

9P, 9N, 10L, 9K, 9G, 10F, 9E, 9D, 10B

2B, 3D, 3E, 2F, 3G, 3K, 2L, 3N, 3P
1B, 2C, 1E, 1F, 2J, 1K, 1L, 2M, 1P

1M x 36 data outputs.

D0D8

D9D17

10P, 11N, 11M, 10K, 11J, 11G, 10E, 11D, 11C

3B, 3C, 2D, 3F, 2G, 3J, 3L, 3M, 2N

2M x 18 data inputs.

Q0Q8

Q9Q17

11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B

2B, 2D, 3E, 2F, 3G, 2K, 2L, 3N, 3P

2M x 18 data outputs.

Write control, active low.

Read control, active low.

7B, 7A, 5A,5B

1M x 36 byte write control, active low.

7B, 5A

2M x 18 byte write control, active low.

REF

2H, 10H

Input reference level.

5F, 7F, 5G, 7G, 5H, 7H, 5J, 7J, 5K, 7K

Power supply.

DDQ

4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L

Output power supply.

2A, 10A, 4C, 8C, 4D, 5D, 6D, 7D, 8D, 5E, 6E, 7E, 6F, 6G, 6H, 6J,
6K, 5L, 6L, 7L, 4M, 8M, 4N, 8N

Power supply.

11H

Output driver impedance control.

TMS, TDI, TCK

10R, 11R, 2R

IEEE 1149.1 test inputs (1.8V LVTTL lev-
els).

TDO

IEEE 1149.1 test output (1.8V LVTTL level).

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

SRAM Features

Read Operations

The SRAM operates continuously in a burst-of-two mode. Read cycles are started by registering R in active
low state at the rising edge of the K clock. A second set of clocks, C and C, are used to control the timing to
the outputs. A set of free-running echo clocks, CQ and CQ, are produced internally with timings identical to
the data-outs. The echo clocks can be used as data capture clocks by the receiver device.

When the C and C clocks are connected high, the K and K clocks assume the function of those clocks. In this
case, the data corresponding to the first address is clocked 1.5 cycles later by the rising edge of the K clock.
The data corresponding to the second burst is clocked 2 cycles later by the following rising edge of the K
clock.

A NOP operation (R is high) does not terminate the previous read.

Write Operations

Write operations can also be initiated at every rising edge of the K clock whenever W is low. The write
address is provided 0.5 cycles later, registered by the rising edge of K. Again, the write always occurs in
bursts of two.

The write data is provided in an `early write' mode; that is, the data-in corresponding to the first address of the
burst, is presented 0.5 cycles earlier or at the rising edge of the preceding K clock. The data-in corresponding
to the second write burst address follows next, registered by the rising edge of K.

The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into
the array on the following write cycle. A read cycle to the last write address produces data from the write
buffers. Similarly, a read address followed by the same write address produces the latest write data. The
SRAM maintains data coherency.

Block Diagram

1M x 36

(2M x 18)

Memory

Array

r
i
t
e/Read Dec

ode

ense Am

Write Driver

Select Output Control

Data

Reg

Add
Reg

Control

Logic

Clock

Gen

tput Reg

t
p

t
Select

t
put Dr

i
v

(or 36)

36 (or 18)

Q (Data-Out)

CQ, CQ

(Echo Clock Out)

D (Data-In)

36 (or 18)

Address

4 (or 2)

19 (or 20)

36 (or 18)

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

During a write, the byte writes independently control which byte of any of the two burst addresses is written
(see X18/X36 Write Truth Tables on page

9 and Timing Reference Diagram for Truth Table on page 8).

Whenever a write is disabled (W is high at the rising edge of K), data is not written into the memory.

RQ Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V

to enable the SRAM

to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance
driven by the SRAM. For example, an RQ of 250

results in a driver impedance of 50. The allowable range

of RQ to guarantee impedance matching is between 175

and 350, with the tolerance described in

Programmable Impedance Output Driver DC Electrical Characteristics on page 14. The RQ resistor should
be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded
ZQ trace must be less than 3 pF.

The ZQ pin can also be directly connected to V

DDQ

to obtain a minimum impedance setting. ZQ must never

be connected to V

Programmable Impedance and Power-Up Requirements

Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by
drifts in supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable
impedances values. The final impedance value is achieved within 1024 clock cycles.

Clock Consideration

This device uses an internal DLL for maximum output data valid window. It can be placed in a stopped-clock
mode to minimize power and requires only 1024 cycles to restart.

No clocks can be issued until V

reaches its allowable operating range.

Single Clock Mode

This device can be also operated in single-clock mode. In this case, C and C are both connected high at
power-up and must never change. Under this condition, K and K will control the output timings.

Either clock pair must have both polarities switching and must never connect to V

REF

, as they are not differ-

ential clocks

Depth Expansion

Separate input and output ports enable easy depth expansion, as each port can be selected and deselected
independently. Read and write operations can occur simultaneously without affecting each other. Also, all
pending read and write transactions are always completed prior to deselecting the corresponding port.

In the following application example, the second pair of C and C clocks is delayed such that the return data
meets the data setup and hold times at the bus master.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

Power-Up and Power-Down Sequences

The power supplies must be powered up in the following order:

1. V

2. V

DDQ

3. V

REF

4. Inputs

The power-down sequence must be the reverse. V

DDQ

can be allowed to exceed V

by no more than 0.6V.

Application Example

2M x 18

R W BW

C C K K

017

SRAM #4

R=250

Data-In 071

Data-Out 071

Address 079

Memory
Controller

Return CLK

Source CLK

Return CLK

Source CLK

R W BW

C C K K

017

SRAM #1

R=250

R=50

Vt=V

REF

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

The Timing Reference Diagram for Truth Table on page

8 is helpful in understanding the clock and write truth

tables, as it shows the cycle relationship between clocks, address, data in, data out, and controls. All read
and write commands are issued at the beginning of cycle "t".

State Diagram

Power Up

Write NOP

Load New

Write Address

DDR Write

Read NOP

Load New

Read Address

DDR Read

Read

Write

Read

Write

Read

Write

Read

Write

Always

(fixed)

Always

(fixed)

Notes: 1. Internal burst counter is fixed as two-bit linear; that is, when first address is A0+0, next internal burst address is A0+1.

2. Read refers to read active status with R = low. Read refers to read inactive status with R = high.

5. State machine control timing sequence is controlled by K.

4. The read and write state machines can be active simultaneously.

3. Write refers to write active status with W = low. Write refers to write inactive status with W = high.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

Timing Reference Diagram for Truth Table

Clock Truth Table

(Use the following table with the Timing Reference Diagram for Truth Table.)

Mode

Clock

Controls

Data-In

Data-Out

B+1

A+1

Stop Clock

Stop

Previous state

Previous State

Previous state

No Operation (NOP)

High-Z

Read A

D out at C

(t + 1.5)

D out at C (t + 2)

Write B

D in at K (t)

D in at K

(t + 0.5)

Notes:

1. The internal burst counter is always fixed as two-bit.

2. X = don't care; H = logic "1"; L = logic "0".

3. A read operation is started when control signal R is active low

4. A write operation is started when control signal W is active low. Before entering into the stop clock, all pending read and write

commands must be completed.

5. For timing definitions, refer to the AC Characteristics on page 16. Signals must have AC specifications at timings indicated in

parenthesis with respect to switching clocks K, K, C, and C.

t+1

t+2

t+3

Read A

Write B

Read C

Write D

A+1

C+2

C+3

K Clock

0,1,2,3

Address

Data-In

Data-Out

C Clock

CQ Clock

Cycle

B+1

D+1

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

X36 Write Truth Table

Use the following table with the Timing Reference Diagram for Truth Table on

page

Operation

K(t)

(t + 0.5)

B+1

Write Byte 0

D0-8 (t)

Write Byte 1

D9-17 (t)

Write Byte 2

D18-26 (t)

Write Byte 3

D27-35 (t)

Write All Bytes

D0-35 (t)

Abort Write

Don't care

Write Byte 0

D0-8 (t + 0.5)

Write Byte 1

D9-17 (t + 0.5)

Write Byte 2

D18-26 (t + 0.5)

Write Byte 3

D27-35 (t + 0.5)

Write All Bytes

D0-35 (t + 0.5)

Abort Write

Don't care

Notes;

1. For all cases. W must be active low during the rising edge of K occurring at time t.

2. For timing definitions, refer to the AC Characteristics on page 16. Signals must have AC specifications with respect to switching

clocks K and K.

X18 Write Truth Table

(Use this table with the Timing Reference Diagram for Truth Table on page

8.)

Operation

K(t)

(t + 0.5)

B+1

Write Byte 0 on B

D08 (t)

Write Byte 1 on B

D917 (t)

Write All Bytes on B

D017 (t)

Abort Write on B

Don't care

Write Byte 1 on B+1

D08(t + 0.5)

Write Byte 2 on B+1

D917(t + 0.5)

Write All Bytes on B+1

D017(t + 0.5)

Abort Write on B+1

Don't care

Notes;

1. Refer to Timing Reference Diagram for Truth Table on page

8. Cycle time starts at n and is referenced to the K clock.

2. For all cases, W must be active low during the rising edge of K occurring at t.

3. For timing definitions, refer to the AC Characteristics on page 16. Signals must have AC specs with respect to switching clocks K

and K.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

Absolute Maximum Ratings

Item

Symbol

Rating

Units

Power supply voltage

-0.5 to 2.6

Output power supply voltage

DDQ

-0.5 to 2.6

Input voltage

-0.5 to 2.6

Data out voltage

DOUT

-0.5 to 2.6

Operating temperature

0 to 70

° C

Junction temperature

110

° C

Storage temperature

STG

-55 to +125

° C

Note: Stresses greater than those listed in this table can cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions above those indicated in the operational sections of this datasheet is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

Recommended DC Operating Conditions

= 0 to +

70° C)

Parameter

Symbol

Minimum

Typical

Maximum

Units

Notes

Supply voltage

1.8 - 5%

1.8 + 5%

Output driver supply voltage

DDQ

1.4

1.9

Input high voltage

REF

+0.1

DDQ

+ 0.2

1, 2

Input low voltage

-0.2

REF

- 0.1

1, 3

Input reference voltage

REF

0.68

0.95

1, 5

Clocks signal voltage

IN - CLK

-0.2

DDQ

+ 0.2

1, 4

1. All voltages are referenced to V

. All V

, V

DDQ

, and V

pins must be connected.

2. V

(Max) AC = See 0vershoot and Undershoot Timings.

3. V

(Min) AC = See 0vershoot and Undershoot Timings.

4. V

IN-CLK

specifies the maximum allowable DC excursions of each clock (K, K, C, and C).

5. Peak-to-peak AC component superimposed on V

REF

may not exceed 5% of V

REF.

0vershoot and Undershoot Timings

PBGA Thermal Characteristics

Item

Symbol

Rating

Units

Thermal resistance junction to ambient (airflow = 1m/s)

TBD

° C/W

Thermal resistance junction to case

TBD

° C/W

Thermal resistance junction to pins

TBD

° C/W

DDQ

20% Min Cycle Time

DDQ

+0.6V

GND-0.6V

GND

20% Min Cycle Time

Overshoot Timing

Undershoot Timing

(Max) AC

(Min) AC

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

Capacitance

= 0 to +

70° C, V

= 1.8V -5%, +5%, f = 1MHz)

Parameter

Symbol

Test Condition

Maximum

Units

Input capacitance

= 0V

Data-in capacitance (D0D35)

DIN

= 0V

Data-out capacitance (Q0Q35)

OUT

= 0V

Clocks Capacitance (K, K, C, C

DC Electrical Characteristics

= 0 to + 70C, V

= 1.8V -5%, +5%)

Parameter

Symbol

Minimum

Maximum

Units

Notes

x36 average power supply operating current

OUT

= 0, V

= V

or V

)

DD30

DD40

DD50

1, 3

x18 average power supply operating current

OUT

= 0, V

= V

or V

)

DD30

DD40

DD50

1, 3

Power supply standby current

(R = V

, W = V

. All other inputs = V

or V

, I

= 0)

SBSS

200

Input leakage current, any input (except JTAG)

= V

or V

) I

-2 +2 uA

Output leakage current

OUT

= V

or V

DDQ

, Q in High-Z) I

-5 +5 uA

Output "high" level voltage (I

= -6mA) V

DDQ

-0.4 V

DDQ

Output "low" level voltage (I

= +6mA) V

+0.4 V 2, 4

JTAG leakage current

= V

or V

) I

LIJTAG

-100 uA

1. I

OUT

= chip output current.

2. Minimum impedance output driver.
3. The numeric suffix indicates the part operating at speed, as indicated in AC Characteristics on page 16 (that is, I

DD25

indicates

2.5ns cycle time).

4. JEDEC Standard JESD8-6 Class 1 compatible.
5. For JTAG inputs only.
6. Currents are estimates only and need to be verified.

800
700
600

+100

2, 4

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

Typical AC Input Characteristics

Item

Symbol

Minimum

Maximum

Notes

AC input logic high

(ac)

REF

+ 0.4

1, 2, 3, 4

AC input logic low

(ac)

REF

- 0.4

1, 2, 3, 4

Clock input logic high (K, K, C, C)

IH-CLK

(ac)

REF

+ 0.4

1, 2, 3

Clock input logic low (K, K, C, C)

IL-CLK

(ac)

REF

- 0.4

1, 2, 3

1. The peak-to-peak AC component superimposed on V

REF

may not exceed 5% of the DC component of V

REF

2. Performance is a function of V

and V

levels to clock inputs.

3. See the AC Input Definition diagram.
4. See the AC Input Definition diagram. The signals should swing monotonically with no steps rail-to-rail with input signals never ring-

ing back past VIH (AC) and VIL (AC) during the input setup and input hold window. VIH (AC) and VIL (AC) are used for timing pur-
poses only.

AC Input Definition

Programmable Impedance Output Driver DC Electrical Characteristics

= 0 to +70

° C, V

= 1.8V -5%, +5%, V

DDQ

= 1.5, 1.8V)

Parameter

Symbol

Minimum

Maximum

Units

Notes

Output "high" level voltage

DDQ

/ 2

DDQ

1, 3

Output "low" level voltage

DDQ

/ 2

2, 3

1. I

± 15% @ V

= V

DDQ

/ 2 For: 175

RQ 350.

2. I

± 15% @ V

= V

DDQ

/ 2 For: 175

RQ 350.

3. Parameter tested with RQ = 250

and V

DDQ

= 1.5V.

(AC)

REF

(AC)

Setup

Time

Hold

Time

REF

RAIL

-RAIL

VDDQ

------------------

--------

VDDQ

------------------

--------

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

AC Test Loading

5pF

0.75, 0.9V

Test

Comparator

AC Test Conditions

= 0 to +

70C, V

= 1.8V -5%, +5%, V

DDQ

= 1.5, 1.8V)

Parameter

Symbol

Conditions

Units

Notes

Output driver supply voltage

DDQ

1.5, 1.8

Input high level

1.25

0.25

Input Low Level

Input reference voltage

REF

0.75

Input rise time

0.35

Input fall time

0.35

Output timing reference level

DDQ/2

Output load conditions

1, 2

1. See AC Test Loading.
2. Parameter tested with RQ = 250 and V

DDQ

= 1.5V.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

AC Characteristics

= 0 to +

70C, V

= 1.8V -5%, +5%)

Parameter

Symbol

(333MHz)

Units

Notes

Min

Max

Clock

Cycle time (K, K, C, C)

KHKH

3.0

4.0

Clock phase jitter (K, K, C, C)

KC-VAR

Clock high pulse (K, K, C, C)

KHKL

Clock low pulse (K, K, C, C)

KLKH

Clock to clock (K

, C

)

KHKH

Clock to data clock (K

, K

)

KHCH

DLL lock (K, C)

KC-

lock

K static to DLL reset

KC-

reset

Output Times

C, C high to output valid

CHQV

0.40

1, 3

C, C high to output hold

CHQX

-0.40

C, C high to echo clock valid

CHCQV

0.35

C, C high to echo clock hold

CHCQX

-0.35

CQ, CQ high to output valid

CQHQV

0.25

1, 3

CQ, CQ high to output hold

CQHQX

-0.25

C high to output high-Z

CHQZ

0.33

C high to output low-Z

CHQX1

-0.33

Setup Times

Address valid to K, K rising edge

AVKH

0.33

Control inputs valid to K rising edge

IVKH

0.33

Data-in valid to K, K rising edge

DVKH

0.33

Hold Times

K rising edge to address hold

KHAX

0.33

K rising edge to control inputs hold

KHIX

0.33

K, K rising edge to data-in hold

KHDX

0.33

1. See AC Test Loading on page 15.
2. During normal operation, V

, V

, T

RISE

, and T

FALL

of inputs must be within 20% of V

, V

, T

RISE

, and T

FALL

of clock.

3. If C, C are tied high, then K,

become the references for C,

timing parameters.

0.12

1.2

1.35

0.0

1.35

1024

cycle

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

AC Characteristics

= 0 to + 70C, V

= 1.8V -5%, +5%)

Parameter

Symbol

(250MHz)

(200MHz)

Units

Notes

Min

Max

Min

Max

Clock

Cycle time (K, K, C, C)

KHKH

4.0

6.0

5.0

7.5

Clock phase jitter (K, K, C, C)

KC-VAR

0.2

Clock high pulse (K, K, C, C)

KHKL

1.6

2.0

Clock low pulse (K, K, C, C)

KLKH

1.6

2.0

Clock to clock (K

, C

)

KHKH

1.8

2.2

Clock to data clock (K

, K

)

KHCH

0.0

1.8

0.0

2.3

DLL lock (K, C)

KC-

lock

1024

cycle

K static to DLL reset

KC-

reset

Output Times

C, C high to output valid

CHQV

0.45

1, 3

C, C high to output hold

CHQX

-0.45

1, 3

C, C high to echo clock valid

CHCQV

0.40

0.4

C, C high to echo clock hold

CHCQX

-0.40

CQ, CQ High to output valid

CQHQV

0.30

0.40

1, 3

CQ, CQ high to output hold

CQHQX

-0.30

-0.40

1, 3

C High to output high-Z

CHQZ

0.35

0.38

1, 3

C High to output low-Z

CHQX1

-0.35

-0.38

1, 3

Setup Times

Address valid to K, K rising edge

AVKH

0.35

0.4

Control inputs valid to K rising edge

IVKH

0.35

0.4

Data-in valid to K, K rising edge

DVKH

0.35

0.4

Hold Times

K rising edge to address hold

KHAX

0.35

0.4

K rising edge to Control Inputs Hold

KHIX

0.35

0.4

K, K rising edge to data-in hold

KHDX

0.35

0.4

1. See AC Test Loading on page 15.
2. During normal operation, V

, V

, T

RISE

, and T

FALL

of inputs must be within 20% of V

, V

, T

RISE

, and T

FALL

of clock.

3. If C, C are tied high, then K,

become the references for C,

timing parameters.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

Read and Deselect Cycles Timing Diagram

CHCQX

CHCQV

CHCQX

CHCQV

CQHQX

CQHQV

CHQV

CHQZ

CHQX

CHQV

CHQX

KLKH

KHKH

KHKL

KHIX

IVKH

KHAX

AVKH

KHKH

KLKH

KHKH

KHKL

Read

NOP

Read

NOP

Q1-1

Q1-2

Q2-1

Q2-2

Q3-1

Q (Data Out)

KLKH

Notes: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 (that is, the next internal

burst address following A1+0).

2. Outputs are disabled one cycle after an NOP.

Don't Care

Undefined

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

Write and NOP Timing Diagram

KHDX

DVKH

KHIX

IVKH

KHAX

AVKH

KHKH

KLKH

KHKL

Write

NOP

Write

NOP

D1-1

D1-2

D2-1

D2-2

D3-1

D3-2

D(Data In)

Don't Care

Undefined

Notes: 1. D1-1 refers to input to address A1+0, D1-2 refers to input to address A1+1 (that is, the next internal

burst address following A1+0).

2. BWx assumed active.

KHIX

IVKH

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

IEEE 1149.1 TAP and Boundary Scan

The SRAM provides a limited set of JTAG functions to test the interconnection between SRAM I/Os and
printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM
core.

In conformance with IEEE Standard 1149.1, the SRAM contains a TAP controller, instruction register,
boundary scan register, bypass register, and ID register.

The TAP controller has a standard 16-state machine that resets internally on power-up. Therefore, a TRST
signal is not required.

Signal List

· TCK: test clock
· TMS: test mode select
· TDI: test data-in
· TDO: test data-out

JTAG DC Operating Characteristics

= 0 to +

70° C)

Operates with JEDEC Standard 8-5 (1.8V) logic signal levels

Parameter

Symbol

Minimum

Typical

Maximum

Units

Notes

JTAG input high voltage

IH1

1.3

+0.3

JTAG input low voltage

IL1

-0.3

0.5

JTAG output high level

OH1

-0.4

1, 2

JTAG output low level

OL1

0.4

1, 3

1. All JTAG inputs and outputs are LVTTL-compatible.
2. I

OH1

-|2mA|

3. I

OL1

+|2mA|.

JTAG AC Test Conditions

= 0 to +

70° C, V

= 1.8V -5%, +5%)

Parameter

Symbol

Conditions

Units

Input pulse high level

IH1

1.3

Input pulse low level

IL1

0.5

Input rise time

1.0

Input fall time

1.0

Input and output timing reference level

0.9

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

JTAG AC Characteristics

= 0 to +

70° C, V

= 1.8V -5%, +5%)

Parameter

Symbol

Minimum

Maximum

Units

Notes

TCK cycle time

THTH

TCK high pulse width

THTL

TCk low pulse width

TLTH

TMS setup

MVTH

TMS hold

THMX

TDI setup

DVTH

TDI hold

THDX

TCK low to valid data

TLOV

1. See AC Test Loading on page 15.

JTAG Timing Diagram

TCK

TMS

TDI

TDO

THTL

TLTH

THTH

THMX

THDX

TLOV

MVTH

DVTH

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

Scan Register Definition

Bit Size x18 or x36

Instruction

Bypass

Boundary Scan

109

ID Register Definition

Part

Field Bit Number and Description

Revision Number

(31:29)

Part Configuration

(28:12)

JEDEC Code

(11:1)

Start Bit

(0)

2M x 18

000

00def0wx0t0q0b0s0

000 101 001 00

1M x 36

000

00def0wx0t0q0b0s0

000 101 001 00

Part Configuration Definition:
def = 010 for 36Mb
wx = 11 for x36, 10 for x18
t = 1 for DLL, 0 for non-DLL
q = 1 for Q

DB2, 0 for DDR

b = 1 for burst of 4, 0 for burst of 2
s = 1 for separate I/0, 0 for common I/O

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

List of IEEE 1149.1 Standard Violations

· 7.2.1.b, e
· 7.7.1.a-f
· 10.1.1.b, e
· 10.7.1.a-d
· 6.1.1.d

Instruction Set

Code

Instruction

TDO Output

Notes

000

EXTEST

Boundary Scan Register

2,6

001

IDCODE

32-bit Identification Register

010

SAMPLE-Z

Boundary Scan Register

1, 2

011

PRIVATE

Do not use

100

SAMPLE

Boundary Scan Register

101

PRIVATE

Do not use

110

PRIVATE

Do not use

111

BYPASS

Bypass Register

1. Places Qs in high-Z in order to sample all input data, regardless of other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.
3. BYPASS register is initiated to V

when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded

TDI when exiting the shift-DR state.

4. SAMPLE instruction does not place DQs in high-Z.
5. This instruction is reserved. Invoking this instruction will cause improper SRAM functionality.
6. This EXTEST is not IEEE 1149.1-compliant. By default, it places Q in high-Z. If the internal register on the scan chain is set high,

Q will be updated with information loaded via a previous SAMPLE instruction. The actual transfer occurs during the update IR
state after EXTEST is loaded. The value of the internal register can be changed during SAMPLE and EXTEST only.

JTAG Block Diagram

Bypass Register (1 bit)

Identification Register (32 bits)

Instruction Register (3 bits)

TAP Controller

Control Signals

TDI

TMS

TCK

TDO

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
06/29/06

ISSI

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs

Order

Pin ID

Order

Pin ID

Order

Pin ID

10D

10C

11D

11B

11C

11P

10B

10P

11A

10N

10A

10M

11N

11L

11M

10L

11K

10K

10J

11J

11H

100

10G

101

102

11F

103

11G

104

105

10F

106

11E

107

10E

108

109

Internal

Note:

1) NC pins as defined on FBGA pinouts on page 2 are read as "don't cares".

2) State of Internal pin (#109) is loaded via JTAG

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IS61QDB21M36-250M3