Integrated Silicon Solution, Inc. · 1-800-379-4774

Rev. B
06/28/01

IS61S6432

ISSI

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

FEATURES

· Internal self-timed write cycle

· Individual Byte Write Control and Global Write

· Clock controlled, registered address, data and

control

· PentiumTM or linear burst sequence control using

MODE input

· Three chip enables for simple depth expansion

and address pipelining

· Common data inputs and data outputs

· Power-down control by ZZ input

· JEDEC 100-Pin TQFP and PQFP package

· Single +3.3V power supply

· Two Clock enables and one Clock disable to

eliminate multiple bank bus contention

· Control pins mode upon power-up:

MODE in interleave burst mode
ZZ in normal operation mode
These control pins can be connected to GNDQ
or VCCQ to alter their power-up state

· Industrial temperature available

DESCRIPTION

The

ISSI

IS61S6432 is a high-speed, low-power

synchronous static RAM designed to provide a burstable,
high-performance, secondary cache for the PentiumTM,
680X0TM, and PowerPCTM microprocessors. It is organized
as 65,536 words by 32 bits, fabricated with

ISSI

's advanced

CMOS technology. The device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positive-edge-
triggered single clock input.

Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

BW1

controls DQ1-DQ8,

BW2

controls DQ9-DQ16,

BW3

controls DQ17-DQ24,

BW4

controls DQ25-DQ32,

conditioned by

BWE

being LOW. A LOW on

input would

cause all bytes to be written.

Bursts can be initiated with either

ADSP

(Address Status

Processor) or

ADSC

(Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated
internally by the IS61S6432 and controlled by the

ADV

(burst address advance) input pin.

Asynchronous signals include output enable (

), sleep

mode input (ZZ), clock (CLK) and burst mode input (MODE).
A HIGH input on the ZZ pin puts the SRAM in the power-
down state. When ZZ is pulled LOW (or no connect), the
SRAM normally operates after three cycles of the wake-up
period. A LOW input, i.e., GND

, on MODE pin selects

LINEAR Burst. A V

CCQ

(or no connect) on MODE pin selects

INTERLEAVED Burst.

64K x 32 SYNCHRONOUS
PIPELINE STATIC RAM

JUNE 2001

FAST ACCESS TIME

Symbol

Parameter

-200

(1)

-166

-133

-117

-5

-6

-7

-8

Unit

CLK Access Time

Cycle Time

7.5

8.5

Frequency

200

166

133

117

100

MHz

Note:
1. ADVANCE INFORMATION ONLY.

Integrated Silicon Solution, Inc. · 1-800-379-4774

Rev.B

06/28/01

IS61S6432

ISSI

BLOCK DIAGRAM

BINARY

COUNTER

A15-A0

BW1

CLR

CLK

MODE

A0'

A1'

CLK

ADV

ADSC

ADSP

ADDRESS

REGISTER

CLK

DQ32-DQ25

BYTE WRITE

REGISTERS

CLK

DQ24-DQ17

BYTE WRITE

REGISTERS

CLK

DQ16-DQ9

BYTE WRITE

REGISTERS

CLK

DQ8-DQ1

BYTE WRITE

REGISTERS

CLK

ENABLE

REGISTER

CLK

ENABLE

DELAY

REGISTER

CLK

BWE

BW4

CE1

CE3

CE2

BW2

BW3

64K x 32

MEMORY

ARRAY

INPUT

REGISTERS

CLK

OUTPUT

REGISTERS

CLK

DATA[32:1]

Integrated Silicon Solution, Inc. · 1-800-379-4774

Rev.B
06/28/01

IS61S6432

ISSI

PIN CONFIGURATION

100-Pin TQFP and PQFP (Top View)

NC
DQ16
DQ15
VCCQ
GNDQ
DQ14
DQ13
DQ12
DQ11
GNDQ
VCCQ
DQ10
DQ9
GND
NC
VCC
ZZ
DQ8
DQ7
VCCQ
GNDQ
DQ6
DQ5
DQ4
DQ3
GNDQ
VCCQ
DQ2
DQ1
NC

CE1

CE2

BW4

BW3

BW2

BW1

CE3

VCC

GND

CLK

BWE

ADSC

ADSP

ADV

DQ17
DQ18

VCCQ

GNDQ

DQ19
DQ20
DQ21
DQ22

GNDQ

VCCQ

DQ23
DQ24

VCCQ

VCC

GND

DQ25
DQ26

VCCQ

GNDQ

DQ27
DQ28
DQ29
DQ30

GNDQ

VCCQ

DQ31
DQ32

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

MODE

GND

VCC

A10

A11

A12

A13

A14

A15

46 47 48 49 50

PIN DESCRIPTIONS

A0-A15

Address Inputs

CLK

Clock

ADSP

Processor Address Status

ADSC

Controller Address Status

ADV

Burst Address Advance

BW1

BW4

Synchronous Byte Write Enable

BWE

Byte Write Enable

Global Write Enable

CE1

, CE2,

CE3

Synchronous Chip Enable

Output Enable

DQ1-DQ32

Data Input/Output

Sleep Mode

MODE

Burst Sequence Mode

+3.3V Power Supply

GND

Ground

CCQ

Isolated Output Buffer Supply: +3.3V

GND

Isolated Output Buffer Ground

No Connect

Integrated Silicon Solution, Inc. · 1-800-379-4774

Rev.B

06/28/01

IS61S6432

ISSI

TRUTH TABLE

Address

Operation

Used

CE1

CE2

CE3

ADSP ADSC

ADV

WRITE

Deselected, Power-down

None

High-Z

Deselected, Power-down

None

High-Z

Deselected, Power-down

None

High-Z

Deselected, Power-down

None

High-Z

Deselected, Power-down

None

High-Z

Read Cycle, Begin Burst

External

Read Cycle, Begin Burst

External

High-Z

Write Cycle, Begin Burst

External

Read Cycle, Begin Burst

External

Read Cycle, Begin Burst

External

High-Z

Read Cycle, Continue Burst

High-Z

Read Cycle, Continue Burst

High-Z

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Current

Read Cycle, Suspend Burst

Current

High-Z

Read Cycle, Suspend Burst

Current

Read Cycle, Suspend Burst

Current

High-Z

Write Cycle, Suspend Burst

Current

Write Cycle, Suspend Burst

Current

Notes:
1. All inputs except

must meet setup and hold times for the Low-to-High transition of clock (CLK).

2. Wait states are inserted by suspending burst.
3. "X" means don't care. WRITE=L means any one or more byte write enable signals (

BW1

BW4

) and

BWE

are LOW or

LOW. WRITE=H means all byte write enable signals are HIGH.

4. For a Write operation following a Read operation,

must be HIGH before the input data required setup time and held HIGH

throughout the input data hold time.

ADSP

LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or

more byte write enable signals and

BWE

LOW or

LOW for the subsequent L-H edge of clock.

PARTIAL TRUTH TABLE

Function

BWE

BW1

BW2

BW3

BW4

READ

WRITE Byte 1

WRITE All Bytes

Integrated Silicon Solution, Inc. · 1-800-379-4774

Rev.B
06/28/01

IS61S6432

ISSI

INTERLEAVED BURST ADDRESS TABLE

(MODE = V

CCQ

or No Connect)

External Address

1st Burst Address

2nd Burst Address

3rd Burst Address

A1 A0

ABSOLUTE MAXIMUM RATINGS

(1,2,3)

Symbol

Parameter

Value

Unit

BIAS

Temperature Under Bias

40 to +85

°C

STG

Storage Temperature

55 to +150

°C

Power Dissipation

1.8

OUT

Output Current (per I/O)

100

, V

OUT

Voltage Relative to GND for I/O Pins

0.5 to V

CCQ

+ 0.3

Voltage Relative to GND for for Address and Control Inputs

0.5 to 5.5

Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions

may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power up.

LINEAR BURST ADDRESS TABLE

(MODE = GND

)

0,0

1,0

0,1

A1', A0' = 1,1

OPERATING RANGE

Range

Ambient Temperature

Commercial

0°C to +70°C

3.3V +10%, 5%

Industrial

40°C to +85°C

3.3V +10%, 5%

Integrated Silicon Solution, Inc. · 1-800-379-4774

Rev.B

06/28/01

IS61S6432

ISSI

POWER SUPPLY CHARACTERISTICS

(Operating Range)

-200

(1)

-166

-133

-117

Symbol Parameter

Test Conditions

Min. Max.

Min. Max. Unit

AC Operating

Device Selected,

Com.

400

215

205

195

Supply Current

All Inputs = V

or V

Ind.

205

OE = V

, Cycle Time · t

min.

Standby Current Device Deselected,

Com.

100

= Max.,

Ind.

CLK Cycle Time · t

min.

Power-Down

ZZ = V

CCQ

, CLK Running

Com.

Mode Current

All Inputs - GND + 0.2V

Ind.

or · V

0.2V

Note:
1. ADVANCE INFORMATION ONLY.

DC ELECTRICAL CHARACTERISTICS

(1,2)

(Over Operating Range)

Symbol Parameter

Test Conditions

Min.

Max.

Unit

Output HIGH Voltage

= 5.0 mA

2.4

Output LOW Voltage

= 5.0 mA

0.4

Input HIGH Voltage

2.0

CCQ

+ 0.3

Input LOW Voltage

0.3

0.8

Input Leakage Current

GND - V

- V

CCQ

(2)

Com.

µA

Ind.

Output Leakage Current

GND - V

OUT

- V

CCQ

= V

Com.

µA

Ind.

Notes:
1. MODE pin have an internal pull-up. ZZ pin has an internal pull-down. These pins may be a No Connect,

tied to GND,or tied to V

CCQ

2. MODE pin should be tied to Vcc or GND. They exhibit ±30 µA maximum leakage current when tied

to - GND + 0.2V or · Vcc 0.2V.

-5

-6

-7

-8

Symbol Parameter

Test Conditions

Min. Max.

Min. Max. Unit

AC Operating

Device Selected,

Com.

175

165

150

140

Supply Current

All Inputs = V

or V

Ind.

185

175

160

150

OE = V

, Cycle Time · t

min.

Standby Current Device Deselected,

Com.

= Max.,

Ind.

CLK Cycle Time · t

min.

Power-Down

ZZ = V

CCQ

, CLK Running

Com.

Mode Current

All Inputs - GND + 0.2V

Ind.

or · V

0.2V

Integrated Silicon Solution, Inc. · 1-800-379-4774

Rev.B
06/28/01

IS61S6432

ISSI

CAPACITANCE

(1,2)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Input/Output Capacitance

OUT

= 0V

Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T

= 25°C, f = 1 MHz, Vcc = 3.3V.

AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

1.5 ns

Input and Output Timing

1.5V

and Reference Level

Output Load

See Figures 1 and 2

Figure 1

Output
Buffer

= 50

1.5V

30 pF

317

5 pF

Including

jig and

scope

351

OUTPUT

3.3V

Figure 2

AC TEST LOADS

Integrated Silicon Solution, Inc. · 1-800-379-4774

Rev.B

06/28/01

IS61S6432

ISSI

READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)

-200

(1)

-166

-133

-117

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max

Unit

Cycle Time

7.5

8.5

Clock High Time

1.6

2.4

2.8

Clock Low Time

1.6

2.4

2.8

Clock Access Time

KQX

(2)

Clock High to Output Invalid

1.5

KQLZ

(2,3)

Clock High to Output Low-Z

KQHZ

(2,3)

Clock High to Output High-Z

3.5

1.5

OEQ

Output Enable to Output Valid

3.5

OEQX

(2)

Output Disable to Output Invalid

OELZ

(2,3)

Output Enable to Output Low-Z

OEHZ

(2,3)

Output Disable to Output High-Z

Address Setup Time

2.5

Address Status Setup Time

2.5

Write Setup Time

2.5

CES

Chip Enable Setup Time

2.5

AVS

Address Advance Setup Time

2.5

Address Hold Time

0.5

Address Status Hold Time

0.5

Write Hold Time

0.5

CEH

Chip Enable Hold Time

0.5

AVH

Address Advance Hold Time

0.5

CFG

(4)

Configuration Setup

Notes:
1. ADVANCE INFORMATION ONLY.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
4. Configuration signal MODE is static and must not change during normal operation.

Integrated Silicon Solution, Inc. · 1-800-379-4774

Rev.B
06/28/01

IS61S6432

ISSI

READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)

(Continued)

-5

-6

-7

-8

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max

Unit

Cycle Time

Clock High Time

3.5

Clock Low Time

3.5

Clock Access Time

KQX

(1)

Clock High to Output Invalid

1.5

KQLZ

(1,2)

Clock High to Output Low-Z

KQHZ

(1,2)

Clock High to Output High-Z

1.5

OEQ

Output Enable to Output Valid

OEQX

(1)

Output Disable to Output Invalid

OELZ

(1,2)

Output Enable to Output Low-Z

OEHZ

(1,2)

Output Disable to Output High-Z

Address Setup Time

2.5

Address Status Setup Time

2.5

Write Setup Time

2.5

CES

Chip Enable Setup Time

2.5

AVS

Address Advance Setup Time

2.5

Address Hold Time

0.5

Address Status Hold Time

0.5

Write Hold Time

0.5

CEH

Chip Enable Hold Time

0.5

AVH

Address Advance Hold Time

0.5

CFG

(3)

Configuration Setup

66.7

Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Configuration signal MODE is static and must not change during normal operation.

Integrated Silicon Solution, Inc. · 1-800-379-4774

Rev.B

06/28/01

IS61S6432

ISSI

READ CYCLE TIMING: PIPELINE

Single Read

High-Z

DATA

OUT

DATA

CE3

CE2

CE1

BW4-BW1

BWE

A15-A0

ADV

ADSC

ADSP

CLK

RD1

RD2

Unselected

Burst Read

KQX

RD3

CES

CEH

CES

CEH

CES

CEH

CE2 and CE3 only sampled with ADSP or ADSC

CE1 Masks ADSP

Unselected with CE2

OEQ

OEQX

OELZ

KQLZ

OEHZ

KQHZ

ADSC initiate read

ADSP is blocked by CE1 inactive

AVH

AVS

Suspend Burst

Pipelined Read

Integrated Silicon Solution, Inc. · 1-800-379-4774

Rev.B
06/28/01

IS61S6432

ISSI

WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)

-200

(1)

-166

-133

-117

Symbol

Parameter

Min. Max.

Min. Max. Min. Max.

Unit

Cycle Time

7.5

8.5

Clock High Time

1.6

2.4

2.8

Clock Low Time

1.6

2.4

2.8

Address Setup Time

2.5

Address Status Setup Time

2.5

Write Setup Time

2.5

Data In Setup Time

2.5

CES

Chip Enable Setup Time

2.5

AVS

Address Advance Setup Time

2.5

Address Hold Time

0.5

Address Status Hold Time

0.5

Data In Hold Time

0.5

Write Hold Time

0.5

CEH

Chip Enable Hold Time

0.5

AVH

Address Advance Hold Time

0.5

CFG

(2)

Configuration Setup

-5

-6

-7

-8

Symbol

Parameter

Min. Max.

Min. Max. Min. Max.

Unit

Cycle Time

Clock High Time

3.5

Clock Low Time

3.5

Address Setup Time

2.5

Address Status Setup Time

2.5

Write Setup Time

2.5

Data In Setup Time

2.5

CES

Chip Enable Setup Time

2.5

AVS

Address Advance Setup Time

2.5

Address Hold Time

0.5

Address Status Hold Time

0.5

Data In Hold Time

0.5

Write Hold Time

0.5

CEH

Chip Enable Hold Time

0.5

AVH

Address Advance Hold Time

0.5

CFG

(2)

Configuration Setup

Note:
1. ADVANCE INFORMATION ONLY.
2. Configuration signal MODE is static and must not change during normal operation.

Integrated Silicon Solution, Inc. · 1-800-379-4774

Rev.B

06/28/01

IS61S6432

ISSI

WRITE CYCLE TIMING

Single Write

DATA

OUT

DATA

CE3

CE2

CE1

BW4-BW1

BWE

A15-A0

ADV

ADSC

ADSP

CLK

WR1

WR2

Unselected

Burst Write

WR3

CES

CEH

CES

CEH

CES

CEH

CE2 and CE3 only sampled with ADSP or ADSC

CE1 Masks ADSP

Unselected with CE2

ADSC initiate Write

ADSP is blocked by CE1 inactive

AVH

AVS

ADV must be inactive for ADSP Write

WR1

WR2

WR3

High-Z

BW4-BW1 only are applied to first cycle of WR2

Write

Integrated Silicon Solution, Inc. · 1-800-379-4774

Rev.B
06/28/01

IS61S6432

ISSI

READ/WRITE CYCLE SWITCHING CHARACTERISTICS

(Over Operating Range)

-200

(1)

-166

-133

-117

Symbol

Parameter

Min. Max.

Min. Max. Min. Max.

Unit

Cycle Time

7.5

8.5

Clock High Time

1.6

2.4

2.8

Clock Low Time

1.6

2.4

2.8

Clock Access Time

KQX

(2)

Clock High to Output Invalid

1.5

KQLZ

(2,3)

Clock High to Output Low-Z

KQHZ

(2,3)

Clock High to Output High-Z

3.5

1.5

OEQ

Output Enable to Output Valid

3.5

OEQX

(2)

Output Disable to Output Invalid

OELZ

(2,3)

Output Enable to Output Low-Z

OEHZ

(2,3)

Output Disable to Output High-Z

Address Setup Time

2.5

Address Status Setup Time

2.5

Write Setup Time

2.5

CES

Chip Enable Setup Time

2.5

Address Hold Time

0.5

Address Status Hold Time

0.5

Write Hold Time

0.5

CEH

Chip Enable Hold Time

0.5

CFG

(4)

Configuration Setup

Integrated Silicon Solution, Inc. · 1-800-379-4774

Rev.B

06/28/01

IS61S6432

ISSI

READ/WRITE CYCLE SWITCHING CHARACTERISTICS

(Over Operating Range)

(Continued)

-5

-6

-7

-8

Symbol

Parameter

Min. Max.

Min. Max. Min. Max.

Unit

Cycle Time

Clock High Time

3.5

Clock Low Time

3.5

Clock Access Time

KQX

(1)

Clock High to Output Invalid

1.5

KQLZ

(1,2)

Clock High to Output Low-Z

KQHZ

(1,2)

Clock High to Output High-Z

1.5

OEQ

Output Enable to Output Valid

OEQX

(1)

Output Disable to Output Invalid

OELZ

(1,2)

Output Enable to Output Low-Z

OEHZ

(1,2)

Output Disable to Output High-Z

Address Setup Time

2.5

Address Status Setup Time

2.5

Write Setup Time

2.5

CES

Chip Enable Setup Time

2.5

Address Hold Time

0.5

Address Status Hold Time

0.5

Write Hold Time

0.5

CEH

Chip Enable Hold Time

0.5

CFG

(3)

Configuration Setup

Integrated Silicon Solution, Inc. · 1-800-379-4774

Rev.B
06/28/01

IS61S6432

ISSI

READ/WRITE CYCLE TIMING: PIPELINE

Single Read

Single Write

High-Z

DATA

OUT

DATA

CE3

CE2

CE1

BW4-BW1

BWE

A15-A0

ADV

ADSC

ADSP

CLK

RD1

WR1

Unselected

Burst Read

KQX

ADSP is blocked by CE1 inactive

RD2

RD3

CES

CEH

CES

CEH

CES

CEH

CE2 and CE3 only sampled with ADSP or ADSC

CE1 Masks ADSP

Unselected with CE3

OEQ

OEQX

OELZ

KQLZ

OEHZ

KQX

KQHZ

Integrated Silicon Solution, Inc. · 1-800-379-4774

Rev.B

06/28/01

IS61S6432

ISSI

SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-200

(2)

-166

-133

-117

Symbol

Parameter

Min. Max.

Min.

Max

Min. Max. Min. Max.

Unit

Cycle Time

7.5

8.5

Clock High Time

1.6

2.4

2.8

Clock Low Time

1.6

2.4

2.8

Clock Access Time

KQX

(3)

Clock High to Output Invalid

1.5

KQLZ

(3,4)

Clock High to Output Low-Z

KQHZ

(3,4)

Clock High to Output High-Z

3.5

1.5

OEQ

Output Enable to Output Valid

3.5

OEQX

(3)

Output Disable to Output Invalid

OELZ

(3,4)

Output Enable to Output Low-Z

OEHZ

(3,4)

Output Disable to Output High-Z

Address Setup Time

2.5

Address Status Setup Time

2.5

CES

Chip Enable Setup Time

2.5

Address Hold Time

2.5

Address Status Hold Time

2.5

CEH

Chip Enable Hold Time

2.5

ZZS

(5)

ZZ Standby

cyc

ZZREC

(6)

ZZ Recovery

cyc

Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. ADVANCE INFORMATION ONLY.
3. Guaranteed but not 100% tested. This parameter is periodically sampled.
4. Tested with load in Figure 2.
5. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data

retention is guaranteed when ZZ is asserted and clock remains active.

6. ADSC and ADSP must not be asserted for at least two cycles after leaving ZZ state.

Integrated Silicon Solution, Inc. · 1-800-379-4774

Rev.B
06/28/01

IS61S6432

ISSI

SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

(Continued)

-5

-6

-7

-8

Symbol

Parameter

Min. Max.

Min. Max. Min. Max.

Unit

Cycle Time

Clock High Time

3.5

Clock Low Time

3.5

Clock Access Time

KQX

(2)

Clock High to Output Invalid

1.5

KQLZ

(2,3)

Clock High to Output Low-Z

KQHZ

(2,3)

Clock High to Output High-Z

1.5

OEQ

Output Enable to Output Valid

OEQX

(2)

Output Disable to Output Invalid

OELZ

(2,3)

Output Enable to Output Low-Z

OEHZ

(2,3)

Output Disable to Output High-Z

Address Setup Time

2.5

Address Status Setup Time

2.5

CES

Chip Enable Setup Time

2.5

Address Hold Time

2.5

Address Status Hold Time

2.5

CEH

Chip Enable Hold Time

2.5

ZZS

(4)

ZZ Standby

cyc

ZZREC

(5)

ZZ Recovery

cyc

Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
4. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data

retention is guaranteed when ZZ is asserted and clock remains active.

5. ADSC and ADSP must not be asserted for at least two cycles after leaving ZZ state.

Integrated Silicon Solution, Inc. · 1-800-379-4774

Rev.B
06/28/01

IS61S6432

ISSI

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Frequency (MHz) Order Part Number

Package

200

IS61S6432-200TQ

TQFP

IS61S6432-200PQ

PQFP

166

IS61S6432-166TQ

TQFP

IS61S6432-166PQ

PQFP

133

IS61S6432-133TQ

TQFP

IS61S6432-133PQ

PQFP

117

IS61S6432-117TQ

TQFP

IS61S6432-117PQ

PQFP

100

IS61S6432-5TQ

TQFP

IS61S6432-5PQ

PQFP

IS61S6432-6TQ

TQFP

IS61S6432-6PQ

PQFP

IS61S6432-7TQ

TQFP

IS61S6432-7PQ

PQFP

IS61S6432-8TQ

TQFP

IS61S6432-8PQ

PQFP

NOTICE

Integrated Silicon Solution, Inc., reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. Integrated Silicon Solution, Inc. assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon
a user's specific application. While the information in this publication has been carefully checked, Integrated Silicon Solution, Inc.
shall not be liable for any damages arising as a result of any error or omission.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety
or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and
(c) potential liability of Integrated Silicon Solution, Inc. is adequately protected under the circumstances.

Reproduction in whole or in part, without the prior written consent of Integrated Silicon Solution, Inc., is prohibited.

ORDERING INFORMATION

Industrial Range: 40°C to +85°C

Frequency (MHz)

Order Part Number

Package

117

IS61S6432-117TQI

TQFP

IS61S6432-117PQI

PQFP

100

IS61S6432-5TQI

TQFP

IS61S6432-5PQI

PQFP

IS61S6432-6TQI

TQFP

IS61S6432-6PQI

PQFP

IS61S6432-7TQI

TQFP

IS61S6432-7PQI

PQFP

IS61S6432-8TQI

TQFP

IS61S6432-8PQI

PQFP

ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: 1-800-379-4774

Fax: (408) 588-0806

E-mail: sales@issi.com

www.issi.com

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