Integrated Silicon Solution, Inc. -- 1-800-379-4774
1
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. Copyright 2001, Integrated Silicon Solution, Inc.
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
FEATURES
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
PentiumTM or linear burst sequence control using
MODE input
Three chip enable option for simple depth expansion
and address pipelining
Common data inputs and data outputs
JEDEC 100-Pin TQFP and
119-pin PBGA package
Single +3.3V, +10%, 5% power supply
Power-down snooze mode
3.3V I/O For SPD
2.5V I/O For LPD
Double cycle deselect
Snooze MODE for reduced-power standby
T version (three chip selects)
D version (two chip selects)
DESCRIPTION
The
ISSI
IS61SPD25632, IS61SPD25636, S61SPD51218,
IS61LPD25632, IS61LPD25636, and IS61LPD51218 are
high-speed, low-power synchronous static RAMs designed
to provide a burstable, high-performance, secondary cache for
the PentiumTM, 680X0TM, and PowerPCTM microprocessors.
The IS61SPD25632 and IS61LPD25632 are organized as
262,144 words by 32 bits and the IS61SPD25636 and
IS61LPD25636 are organized as 262,144 words by 36 bits.
The IS61SPD51218 and IS61LPS51218 are organized as
524,288 words by 18 bits. Fabricated with
ISSI
's advanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous inputs
pass through registers controlled by a positive-edge-triggered
single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (
BWE
).input combined with one or more individual
byte write signals (
BWx
). In addition, Global Write (
GW
)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS PIPELINE,
DOUBLE-CYCLE DESELECT STATIC RAM
PRELIMINARY INFORMATION
SEPTEMBER 2000
FAST ACCESS TIME
Symbol
Parameter
-166*
-150
-133
-5
Units
t
KQ
Clock Access Time
3.5
3.8
4
5
ns
t
KC
Cycle Time
6
6.7
7.5
10
ns
Frequency
166
150
133
100
MHz
*This speed available only in SPD version
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
BLOCK DIAGRAM
18/19
BINARY
COUNTER
A17-A0
(61SPD25632/36,
61LPD25632/36)
BWa
GW
CLR
CE
CLK
Q0
Q1
MODE
A0'
A0
A1
A1'
CLK
ADV
ADSC
ADSP
16/17
18/19
ADDRESS
REGISTER
CE
D
CLK
Q
DQd
BYTE WRITE
REGISTERS
D
CLK
Q
DQc
BYTE WRITE
REGISTERS
D
CLK
Q
DQb
BYTE WRITE
REGISTERS
D
CLK
Q
DQa
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
CE
D
CLK
Q
ENABLE
DELAY
REGISTER
D
CLK
Q
BWE
BWd
(T, D)
CE
(T)
CE2
(T, D) CE2
BWb
BWc
256Kx32; 256Kx36;
512Kx18
MEMORY ARRAY
32, 36,
or 18
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
OE
4
OE
DQa - DQd
32, 36,
or 18
32, 36,
or 18
A18-A0
(61SPD51218,
61LPD51218)
(x32/x36)
(x32/x36/x18)
(x32/x36)
(x32/x36/x18)
Integrated Silicon Solution, Inc. -- 1-800-379-4774
3
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
PIN CONFIGURATION
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
NC
VCCQ
A6
CE2
A7
NC
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
NC
A5
NC
NC
A4
A3
A2
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
A10
NC
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
A11
NC
A8
A9
A12
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
NC
A14
NC
A16
A17
A15
NC
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
NC
A13
NC
NC
VCCQ
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
A17
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
119-pin PBGA (Top View)
100-Pin TQFP (D Version)
256K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17
Synchronous Address Inputs
CLK
Synchronous Clock
ADSP
Synchronous Processor Address
Status
ADSC
Synchronous Controller Address
Status
ADV
Synchronous Burst Address Advance
BWa
-
BWd
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
GW
Synchronous Global Write Enable
CE
, CE2
Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
V
CC
+3.3V Power Supply
GND
Ground
V
CCQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ
Snooze Enable
GND
Q
Isolated Output Buffer Ground
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
PIN CONFIGURATION
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
A17
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
100-Pin TQFP (T Version)
256K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17
Synchronous Address Inputs
CLK
Synchronous Clock
ADSP
Synchronous Processor Address
Status
ADSC
Synchronous Controller Address
Status
ADV
Synchronous Burst Address Advance
BWa
-
BWd
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
GW
Synchronous Global Write Enable
CE
, CE2,
CE2
Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
V
CC
+3.3V Power Supply
GND
Ground
V
CCQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ
Snooze Enable
GND
Q
Isolated Output Buffer Ground
Integrated Silicon Solution, Inc. -- 1-800-379-4774
5
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
PIN CONFIGURATION
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
NC
VCCQ
A6
CE2
A7
DQPc
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
DQPd
A5
NC
NC
A4
A3
A2
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
A10
NC
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
A11
NC
A8
A9
A12
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
NC
A14
NC
A16
A17
A15
DQPb
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
DQPa
A13
NC
NC
VCCQ
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
A17
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
256K x 36
119-pin PBGA (Top View)
100-Pin TQFP (D Version)
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17
Synchronous Address Inputs
CLK
Synchronous Clock
ADSP
Synchronous Processor Address
Status
ADSC
Synchronous Controller Address
Status
ADV
Synchronous Burst Address Advance
BWa
-
BWd
Individual Byte Write Enable
BWE
Synchronous Byte Write Enable
GW
Synchronous Global Write Enable
CE
, CE2
Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
V
CC
+3.3V Power Supply
GND
Ground
V
CCQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ
Snooze Enable
DQPa-DQPd
Parity Data I/O
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
PIN CONFIGURATION
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
A17
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
256K x 36
100-Pin TQFP (T Version)
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17
Synchronous Address Inputs
CLK
Synchronous Clock
ADSP
Synchronous Processor Address
Status
ADSC
Synchronous Controller Address
Status
ADV
Synchronous Burst Address Advance
BWa
-
BWd
Individual Byte Write Enable
BWE
Synchronous Byte Write Enable
GW
Synchronous Global Write Enable
CE
, CE2,
CE2
Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
V
CC
+3.3V Power Supply
GND
Ground
V
CCQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ
Snooze Enable
DQPa-DQPd
Parity Data I/O
Integrated Silicon Solution, Inc. -- 1-800-379-4774
7
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
PIN CONFIGURATION
A17
NC
NC
VCCQ
GND
NC
DQPa
DQa8
DQa7
GND
VCCQ
DQa6
DQa5
GND
NC
VCC
ZZ
DQa4
DQa3
VCCQ
GND
DQa2
DQa1
NC
NC
GND
VCCQ
NC
NC
NC
A6
A7
CE
CE2
NC
NC
BWb
BWa
A18
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
NC
NC
NC
VCCQ
GND
NC
NC
DQb1
DQb2
GND
VCCQ
DQb3
DQb4
VCC
VCC
NC
GND
DQb5
DQb6
VCCQ
GND
DQb7
DQb8
DQPb
NC
GND
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQb1
NC
VCCQ
NC
DQb4
VCCQ
NC
DQb6
VCCQ
DQb8
NC
NC
NC
VCCQ
A6
CE2
A7
NC
DQb2
NC
DQb3
NC
VCC
DQb5
NC
DQb7
NC
DQPb
A5
A11
NC
A4
A3
A2
GND
GND
GND
BWb
GND
NC
GND
GND
GND
GND
GND
MODE
A10
NC
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
NC
NC
A8
A9
A12
GND
GND
GND
GND
GND
NC
GND
BWa
GND
GND
GND
NC
A14
NC
A16
A18
A15
DQPa
NC
DQa7
NC
DQa5
VCC
NC
DQa3
NC
DQa2
NC
A13
A17
NC
VCCQ
NC
NC
NC
DQa8
VCCQ
DQa6
NC
VCCQ
DQa4
NC
VCCQ
NC
DQa1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
512K x 18
119-pin PBGA (Top View)
100-Pin TQFP (D Version)
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A18
Synchronous Address Inputs
CLK
Synchronous Clock
ADSP
Synchronous Processor Address
Status
ADSC
Synchronous Controller Address
Status
ADV
Synchronous Burst Address Advance
BWa
-
BWb
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
GW
Synchronous Global Write Enable
CE
, CE2
Synchronous Chip Enable
OE
Output Enable
DQa-DQb
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
V
CC
+3.3V Power Supply
GND
Ground
V
CCQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ
Snooze Enable
DQPa-DQPb
Parity Data I/O DQPa is parity for DQa1-8;
DQPb is parity for DQb1-8
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A18
Synchronous Address Inputs
CLK
Synchronous Clock
ADSP
Synchronous Processor Address
Status
ADSC
Synchronous Controller Address
Status
ADV
Synchronous Burst Address Advance
BWa
-
BWb
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
GW
Synchronous Global Write Enable
CE
, CE2,
CE2
Synchronous Chip Enable
OE
Output Enable
DQa-DQb
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
V
CC
+3.3V Power Supply
GND
Ground
V
CCQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ
Snooze Enable
DQPa-DQPb
Parity Data I/O DQPa is parity for DQa1-8;
DQPb is parity for DQb1-8
PIN CONFIGURATION
A17
NC
NC
VCCQ
GND
NC
DQPa
DQa8
DQa7
GND
VCCQ
DQa6
DQa5
GND
NC
VCC
ZZ
DQa4
DQa3
VCCQ
GND
DQa2
DQa1
NC
NC
GND
VCCQ
NC
NC
NC
A6
A7
CE
CE2
NC
NC
BWb
BWa
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
NC
NC
NC
VCCQ
GND
NC
NC
DQb1
DQb2
GND
VCCQ
DQb3
DQb4
VCC
VCC
NC
GND
DQb5
DQb6
VCCQ
GND
DQb7
DQb8
DQPb
NC
GND
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
A18
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
512K x 18
100-Pin TQFP (T Version)
Integrated Silicon Solution, Inc. -- 1-800-379-4774
9
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
PARTIAL TRUTH TABLE
Function
GW
BWE
BWa
BWb
BWc
BWd
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte 1
H
L
L
H
H
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
TRUTH TABLE
Address
Operation
Used
CE
CE2
CE2
ADSP ADSC
ADV WRITE
OE
DQ
Deselected, Power-down
None
H
X
X
X
L
X
X
X
High-Z
Deselected, Power-down
None
L
X
H
L
X
X
X
X
High-Z
Deselected, Power-down
None
L
L
X
L
X
X
X
X
High-Z
Deselected, Power-down
None
L
X
H
H
L
X
X
X
High-Z
Deselected, Power-down
None
L
L
X
H
L
X
X
X
High-Z
Read Cycle, Begin Burst
External
L
H
L
L
X
X
X
X
Q
Read Cycle, Begin Burst
External
L
H
L
H
L
X
Read
X
Q
Write Cycle, Begin Burst
External
L
H
L
H
L
X
Write
X
D
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
Read
L
Q
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
Read
H
High-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
Read
L
Q
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
Read
H
High-Z
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
Write
X
D
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
Write
X
D
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
Read
L
Q
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
Read
H
High-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
Read
L
Q
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
Read
H
High-Z
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
Write
X
D
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
Write
X
D
10
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
INTERLEAVED BURST ADDRESS TABLE (MODE = V
CC
or No Connect)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A1 A0
A1 A0
A1 A0
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
1,0
0,1
A1', A0' = 1,1
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
T
BIAS
Temperature Under Bias
40 to +85
C
T
STG
Storage Temperature
55 to +150
C
P
D
Power Dissipation
1.6
W
I
OUT
Output Current (per I/O)
100
mA
V
IN
, V
OUT
Voltage Relative to GND for I/O Pins
0.5 to V
CCQ
+ 0.5
V
V
IN
Voltage Relative to GND for
0.5 to V
CC
+ 0.5
V
for Address and Control Inputs
V
CC
Voltage on Vcc Supply Relatiive to GND
0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or
electric fields; however, precautions may be taken to avoid application of any voltage higher than
maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
11
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
OPERATING RANGE
Range
Ambient Temperature
V
CC
V
CCQ
Commercial
0C to +70C
3.3V,
+10%, 5%
2.375
3.6V
Industrial
40C to +85C
3.3V,
+10%, 5%
2.375
3.6V
DC ELECTRICAL CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
I
OH
= 2.0 mA, V
CCQ
= 2.5V
1.7
--
V
I
OH
= 4.0 mA, V
CCQ
= 3.3V
2.4
--
V
V
OL
Output LOW Voltage
I
OL
= 2.0 mA, V
CCQ
= 2.5V
--
0.7
V
I
OL
= 8.0 mA, V
CCQ
= 3.3V
--
0.4
V
V
IH
Input HIGH Voltage
V
CCQ
= 2.5V
1.7
V
CCQ
+ 0.3
V
V
CCQ
= 3.3V
2.0
V
CCQ
+ 0.3
V
V
IL
Input LOW Voltage
V
CCQ
= 2.5V
0.3
0.7
V
V
CCQ
= 3.3V
0.3
0.8
V
I
LI
Input Leakage Current
GND
V
IN
V
CCQ
(2)
Com.
2
2
A
Ind.
5
5
I
LO
Output Leakage Current
GND
V
OUT
V
CCQ
,
OE
= V
IH
Com.
2
2
A
Ind.
5
5
POWER SUPPLY CHARACTERISTICS
(Over Operating Range)
-166*
-150
-133
-100
Symbol Parameter
Test Conditions
Max.
Max.
Max.
Max.
Unit
I
CC
AC Operating
Device Selected,
Com.
400
370
350
300
mA
Supply Current
All Inputs = V
IL
or V
IH
Ind.
--
400
380
330
mA
OE
= V
IH
, Vcc = Max.
Cycle Time
t
KC
min.
I
SB
Standby Current
Device Deselected,
Com.
110
105
90
80
mA
V
CC
= Max.,
Ind.
--
110
95
85
mA
All Inputs = V
IH
or V
IL
CLK Cycle Time
t
KC
min.
*This speed available only in SPD version
Notes:
1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to V
CC
.
2. The MODE pin should be tied to Vcc or GND. It exhibits 10 A maximum leakage current when tied to - GND + 0.2V
or
Vcc 0.2V.
12
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Input/Output Capacitance
V
OUT
= 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
1.5 ns
Input and Output Timing
1.5V for 3.3V I/O
and Reference Level
V
CCQ
/2V for 2.5V I/O
Output Load
See Figures 1 and 2
AC TEST LOADS
Figure 2
317
/1667
5 pF
Including
jig and
scope
351
/1538
OUTPUT
3.3V for 3.3V I/O
/2.5V for 2.5v I/O
Figure 1
Output
Buffer
Z
O
= 50
1.5V for 3,3V I/O
V
CCQ
/2V for 2.5V I/O
50
Integrated Silicon Solution, Inc. -- 1-800-379-4774
13
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-166*
-150
-133
-100
Symbol Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
f
MAX
Clock Frequency
--
166
--
150
--
133
--
100
MHz
t
KC
Cycle Time
6
--
6.7
--
7.5
--
10
--
ns
t
KH
Clock High Pulse Width
2.3
--
2.5
--
2.8
--
3
--
ns
t
KL
Clock Low Pulse Width
2.3
--
2.5
--
2.8
--
3
--
ns
t
KQ
Clock Access Time
--
3.5
--
3.8
--
4
--
5
ns
t
KQX
(1)
Clock High to Output Invalid
1.5
--
1.5
--
1.5
--
1.5
--
ns
t
KQLZ
(1,2)
Clock High to Output Low-Z
0
--
0
--
0
--
0
--
ns
t
KQHZ
(1,2)
Clock High to Output High-Z
--
3.5
--
3.8
--
4
--
5
ns
t
OEQ
Output Enable to Output Valid
--
3.5
--
3.8
--
4
--
5
ns
t
OELZ
(1,2)
Output Enable to Output Low-Z
0
--
0
--
0
--
0
--
ns
t
OEHZ
(1,2)
Output Enable to Output High-Z
--
3.2
--
3.8
--
4
--
5
ns
t
AS
Address Setup Time
1.5
--
1.5
--
1.5
--
2
--
ns
t
SS
Address Status Setup Time
1.5
--
1.5
--
1.5
--
2
--
ns
t
WS
Write Setup Time
1.5
--
1.5
--
1.5
--
2
--
ns
t
CES
Chip Enable Setup Time
1.5
--
1.5
--
1.5
--
2
--
ns
t
AVS
Address Advance Setup Time
1.5
--
1.5
--
1.5
--
2
--
ns
t
AH
Address Hold Time
0.5
--
0.5
--
0.5
--
0.5
--
ns
t
SH
Address Status Hold Time
0.5
--
0.5
--
0.5
--
0.5
--
ns
t
WH
Write Hold Time
0.5
--
0.5
--
0.5
--
0.5
--
ns
t
CEH
Chip Enable Hold Time
0.5
--
0.5
--
0.5
--
0.5
--
ns
t
AVH
Address Advance Hold Time
0.5
--
0.5
--
0.5
--
0.5
--
ns
*This speed available only in SPD version
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
14
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
READ/WRITE CYCLE TIMING
Single Read
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BWx
BWE
GW
Address
ADV
ADSC
ADSP
CLK
RD1
RD2
1a
2c
2d
3a
Unselected
Burst Read
t
KQX
t
KC
t
KL
t
KH
t
SS
t
SH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
RD3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
t
OEQ
t
OEQX
t
OELZ
t
KQLZ
t
KQ
t
OEHZ
t
KQHZ
ADSC initiate read
ADSP is blocked by CE inactive
t
AVH
t
AVS
Suspend Burst
Pipelined Read
2a
2b
Integrated Silicon Solution, Inc. -- 1-800-379-4774
15
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-166*
-150
-133
-100
Symbol Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
KC
Cycle Time
6
--
6.7
--
7.5
--
10
--
ns
t
KH
Clock High Pulse Width
2.3
--
2.5
--
2.8
--
3
--
ns
t
KL
Clock Low Pulse Width
2.3
--
2.5
--
2.8
--
3
--
ns
t
AS
Address Setup Time
1.5
--
1.5
--
1.5
--
2
--
ns
t
SS
Address Status Setup Time
1.5
--
1.5
--
1.5
--
2
--
ns
t
WS
Write Setup Time
1.5
--
1.5
--
1.5
--
2
--
ns
t
DS
Data In Setup Time
1.5
--
1.5
--
1.5
--
2
--
ns
t
CES
Chip Enable Setup Time
1.5
--
1.5
--
1.5
--
2
--
ns
t
AVS
Address Advance Setup Time
1.5
--
1.5
--
1.5
--
2
--
ns
t
AH
Address Hold Time
0.5
--
0.5
--
0.5
--
0.5
--
ns
t
SH
Address Status Hold Time
0.5
--
0.5
--
0.5
--
0.5
--
ns
t
DH
Data In Hold Time
0.5
--
0.5
--
0.5
--
0.5
--
ns
t
WH
Write Hold Time
0.5
--
0.5
--
0.5
--
0.5
--
ns
t
CEH
Chip Enable Hold Time
0.5
--
0.5
--
0.5
--
0.5
--
ns
t
AVH
Address Advance Hold Time
0.5
--
0.5
--
0.5
--
0.5
--
ns
*This speed available only in SPD version
16
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
WRITE CYCLE TIMING
Single Write
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BWx
BWE
GW
Address
ADV
ADSC
ADSP
CLK
WR1
WR2
Unselected
Burst Write
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
WR3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
ADSC initiate Write
ADSP is blocked by CE inactive
t
AVH
t
AVS
ADV must be inactive for ADSP Write
WR1
WR2
t
WS
t
WH
WR3
t
WS
t
WH
High-Z
High-Z
1a
3a
t
DS
t
DH
BW4-BW1 only are applied to first cycle of WR2
Write
2c
2d
2a
2b
Integrated Silicon Solution, Inc. -- 1-800-379-4774
17
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
SLEEP MODE TIMING
Don't Care
Deselect or Read Only
Deselect or Read Only
t
RZZI
CLK
ZZ
Isupply
All Inputs
(except ZZ)
Outputs
(Q)
I
SB2
ZZ setup cycle
ZZ recovery cycle
Normal
operation
cycle
t
PDS
t
PUS
t
ZZI
High-Z
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
Max.
Unit
I
SB
2
Current during SNOOZE MODE
ZZ
Vih
--
30
mA
t
PDS
ZZ active to input ignored
--
2
cycle
t
PUS
ZZ inactive to input sampled
2
--
cycle
t
ZZI
ZZ active to SNOOZE current
--
2
cycle
t
RZZI
ZZ inactive to exit SNOOZE current
0
--
ns
18
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
PAR
PAR
PAR
PAR
PART
T
T
T
T IDENTIFICA
IDENTIFICA
IDENTIFICA
IDENTIFICA
IDENTIFICATION
TION
TION
TION
TION
6 1 X P D X X X X X X - X X X X X X
Rating
Commercial
I - Industrial
Package
TQ - TQFP
B - PBGA
Speed
166 - 166 MHz
150 - 150 MHz
133 - 133 MHz
5 - 100 MHz
Density
25632 - 256K x 32
25636 - 256K x 36
51218 - 512K x 18
D - double-cycle dedelect
S - single-cycle deselect
SP - 3.3V I/O synchronous pipeline
LP - 2.5V I/O synchronous pipeline
T - Three chip selects
D - Two chip selects
Integrated Silicon Solution, Inc. -- 1-800-379-4774
19
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
ORDERING INFORMATION
Commercial Range: 0C to +70C
Speed
Order Part Number
Package
166 MHz
IS61SPD25632T-166TQ
TQFP
IS61SPD25632D-166TQ
TQFP
IS61SPD25632D-166B
PBGA
150 MHz
IS61SPD25632T-150TQ
TQFP
IS61SPD25632D-150TQ
TQFP
IS61SPD25632D-150B
PBGA
133 MHz
IS61SPD25632T-133TQ
TQFP
IS61SPD25632D-133TQ
TQFP
IS61SPD25632D-133B
PBGA
100 MHz
IS61SPD25632T-5TQ
TQFP
IS61SPD25632D-5TQ
TQFP
IS61SPD25632D-5B
PBGA
Industrial Range: 40C to +85C
Speed
Order Part Number
Package
150 MHz
IS61SPD25632T-150TQI
TQFP
IS61SPD25632D-150TQI
TQFP
133 MHz
IS61SPD25632T-133TQI
TQFP
IS61SPD25632D-133TQI
TQFP
100 MHz
IS61SPD25632T-5TQI
TQFP
IS61SPD25632D-5TQI
TQFP
Commercial Range: 0C to +70C
Speed
Order Part Number
Package
166 MHz
IS61SPD25636T-166TQ
TQFP
IS61SPD25636D-166TQ
TQFP
IS61SPD25636D-166B
PBGA
150 MHz
IS61SPD25636T-150TQ
TQFP
IS61SPD25636D-150TQ
TQFP
IS61SPD25636D-150B
PBGA
133 MHz
IS61SPD25636T-133TQ
TQFP
IS61SPD25636D-133TQ
TQFP
IS61SPD25636D-133B
PBGA
100 MHz
IS61SPD25636T-5TQ
TQFP
IS61SPD25636D-5TQ
TQFP
IS61SPD25636D-5B
PBGA
Industrial Range: 40C to +85C
Speed
Order Part Number
Package
150 MHz
IS61SPD25636T-150TQI
TQFP
IS61SPD25636D-150TQI
TQFP
133 MHz
IS61SPD25636T-133TQI
TQFP
IS61SPD25636D-133TQI
TQFP
100 MHz
IS61SPD25636T-5TQI
TQFP
IS61SPD25636D-5TQI
TQFP
20
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
ORDERING INFORMATION
Commercial Range: 0C to +70C
Speed
Order Part Number
Package
166 MHz
IS61SPD51218T-166TQ
TQFP
IS61SPD51218D-166TQ
TQFP
IS61SPD51218D-166B
PBGA
150 MHz
IS61SPD51218T-150TQ
TQFP
IS61SPD51218D-150TQ
TQFP
IS61SPD51218D-150B
PBGA
133 MHz
IS61SPD51218T-133TQ
TQFP
IS61SPD51218D-133TQ
TQFP
IS61SPD51218D-133B
PBGA
100 MHz
IS61SPD51218T-5TQ
TQFP
IS61SPD51218D-5TQ
TQFP
IS61SPD51218D-5B
PBGA
Industrial Range: 40C to +85C
Speed
Order Part Number
Package
150 MHz
IS61SPD51218T-150TQI
TQFP
IS61SPD51218D-150TQI
TQFP
133 MHz
IS61SPD51218T-133TQI
TQFP
IS61SPD51218D-133TQI
TQFP
100 MHz
IS61SPD51218T-5TQI
TQFP
IS61SPD51218D-5TQI
TQFP
Integrated Silicon Solution, Inc. -- 1-800-379-4774
21
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
ORDERING INFORMATION
Commercial Range: 0C to +70C
Speed
Order Part Number
Package
150 MHz
IS61LPD25632T-150TQ
TQFP
IS61LPD25632D-150TQ
TQFP
IS61LPD25632D-150B
PBGA
133 MHz
IS61LPD25632T-133TQ
TQFP
IS61LPD25632D-133TQ
TQFP
IS61LPD25632D-133B
PBGA
100 MHz
IS61LPD25632T-5TQ
TQFP
IS61LPD25632D-5TQ
TQFP
IS61LPD25632D-5B
PBGA
Industrial Range: 40C to +85C
Speed
Order Part Number
Package
133 MHz
IS61LPD25632T-133TQI
TQFP
IS61LPD25632D-133TQI
TQFP
100 MHz
IS61LPD25632T-5TQI
TQFP
IS61LPD25632D-5TQI
TQFP
Commercial Range: 0C to +70C
Speed
Order Part Number
Package
150 MHz
IS61LPD25636T-150TQ
TQFP
IS61LPD25636D-150TQ
TQFP
IS61LPD25636D-150B
PBGA
133 MHz
IS61LPD25636T-133TQ
TQFP
IS61LPD25636D-133TQ
TQFP
IS61LPD25636D-133B
PBGA
100 MHz
IS61LPD25636T-5TQ
TQFP
IS61LPD25636D-5TQ
TQFP
IS61LPD25636D-5B
PBGA
Industrial Range: 40C to +85C
Speed
Order Part Number
Package
133 MHz
IS61LPD25636T-133TQI
TQFP
IS61LPD25636D-133TQI
TQFP
100 MHz
IS61LPD25636T-5TQI
TQFP
IS61LPD25636D-5TQI
TQFP
22
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D
IS61LPD25632T/D
IS61SPD25636T/D
IS61LPD25636T/D
IS61SPD51218T/D
IS61LPD51218T/D
ISSI
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
ORDERING INFORMATION
Commercial Range: 0C to +70C
Speed
Order Part Number
Package
150 MHz
IS61LPD51218T-150TQ
TQFP
IS61LPD51218D-150TQ
TQFP
IS61LPD51218D-150B
PBGA
133 MHz
IS61LPD51218T-133TQ
TQFP
IS61LPD51218D-133TQ
TQFP
IS61LPD51218D-133B
PBGA
100 MHz
IS61LPD51218T-5TQ
TQFP
IS61LPD51218D-5TQ
TQFP
IS61LPD51218D-5B
PBGA
Industrial Range: 40C to +85C
Speed
Order Part Number
Package
133 MHz
IS61LPD51218T-133TQI
TQFP
IS61LPD51218D-133TQI
TQFP
100 MHz
IS61LPD51218T-5TQI
TQFP
IS61LPD51218D-5TQI
TQFP
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