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Электронный компонент: IS62C1024-35QI

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Integrated Silicon Solution, Inc. -- 1-800-379-4774
1
Rev. G
01/14/00
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. Copyright 2000, Integrated Silicon Solution, Inc.
IS62C1024
ISSI
DESCRIPTION
The
ISSI
IS62C1024 is a low power,131,072-word by
8-bit CMOS static RAM. It is fabricated using
ISSI
's
high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design techniques,
yields higher performance and low power consumption
devices.
When
CE1
is HIGH or CE2 is LOW (deselected), the
device assumes a standby mode at which the power
dissipation can be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip
Enable inputs,
CE1
and CE2. The active LOW Write
Enable (
WE
) controls both writing and reading of the
memory.
The IS62C1024 is available in 32-pin 525-mil plastic SOP
and TSOP (type 1) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
CE1
OE
WE
512 X 2048
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
CE2
128K x 8 HIGH-SPEED CMOS STATIC RAM
JANUARY 2000
FEATURES
High-speed access time: 35, 45, 55, 70 ns
Low active power: 450 mW (typical)
Low standby power: 500 W (typical) CMOS
standby
Output Enable (
OE
) and two Chip Enable
(
CE1
and CE2) inputs for ease in applications
Fully static operation: no clock or refresh
required
TTL compatible inputs and outputs
Single 5V (10%) power supply
IS62C1024
ISSI
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. G
01/14/00
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
ISSI
62C1024
PIN CONFIGURATION
32-Pin SOP
32-Pin TSOP (Type 1)
PIN DESCRIPTIONS
A0-A16
Address Inputs
CE1
Chip Enable 1 Input
CE2
Chip Enable 2 Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
Vcc
Power
GND
Ground
OPERATING RANGE
Range
Ambient Temperature
V
CC
Commercial
0C to +70C
5V 10%
Industrial
40C to +85C
5V 10%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
IS62C1024
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
3
Rev. G
01/14/00
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to +7.0
V
T
BIAS
Temperature Under Bias
10 to +85
C
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.5
W
I
OUT
DC Output Current (LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz, Vcc = 5.0V.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 1.0 mA
2.4
--
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 2.1 mA
--
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.5
V
V
IL
Input LOW Voltage
(1)
0.3
0.8
V
I
LI
Input Leakage
GND
V
IN
V
CC
Com.
5
5
A
Ind.
10
10
I
LO
Output Leakage
GND
V
OUT
V
CC
Com.
5
5
A
Ind.
10
10
Notes:
1. V
IL
= 3.0V for pulse width less than 10 ns.
TRUTH TABLE
Mode
WE
CE1
CE2
OE
I/O Operation
Vcc Current
Not Selected
X
H
X
X
High-Z
I
SB
1
, I
SB
2
(Power-down)
X
X
L
X
High-Z
I
SB
1
, I
SB
2
Output Disabled H
L
H
H
High-Z
I
CC
Read
H
L
H
L
D
OUT
I
CC
Write
L
L
H
X
D
IN
I
CC
IS62C1024
ISSI
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. G
01/14/00
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
5 ns
Input and Output Timing
1.5V
and Reference Level
Output Load
See Figures 1a and 1b
AC TEST LOADS
Figure 1a.
Figure 1b.
480
5 pF
Including
jig and
scope
255
OUTPUT
5V
480
100 pF
Including
jig and
scope
255
OUTPUT
5V
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-35
-45
-55
-70
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
I
CC
Vcc Dynamic Operating
V
CC
= Max.,
CE
= V
IL
Com.
--
150
--
135
--
120
--
90
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
--
160
--
145
--
130
--
100
I
SB
1
TTL Standby Current
V
CC
= Max.,
Com.
--
40
--
40
--
40
--
40
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
,
CE1
V
IH
, Ind.
--
60
--
60
--
60
--
60
or CE2
V
IL
, f = 0
I
SB
2
CMOS Standby
V
CC
= Max.,
Com.
--
30
--
30
--
30
--
30
mA
Current (CMOS Inputs)
CE1
V
CC
0.2V,
Ind.
--
40
--
40
--
40
--
40
CE2
0.2V, V
IN
V
CC
0.2V,
or V
IN
0.2V, f = 0
Notes:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IS62C1024
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
5
Rev. G
01/14/00
DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-35
-45
-55
-70
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
35
--
45
--
55
--
70
--
ns
t
AA
Address Access Time
--
35
--
45
--
55
--
70
ns
t
OHA
Output Hold Time
3
--
3
--
3
--
3
--
ns
t
ACE
1
CE1
Access Time
--
35
--
45
--
55
--
70
ns
t
ACE
2
CE2 Access Time
--
35
--
45
--
55
--
70
ns
t
DOE
OE
Access Time
--
10
--
20
--
25
--
35
ns
t
LZOE
(2)
OE
to Low-Z Output
0
--
0
--
0
--
0
--
ns
t
HZOE
(2)
OE
to High-Z Output
0
10
0
15
0
20
0
25
ns
t
LZCE
1
(2)
CE1
to Low-Z Output
3
--
5
--
7
--
10
--
ns
t
LZCE
2
(2)
CE2 to Low-Z Output
3
--
5
--
7
--
10
--
ns
t
HZCE
(2)
CE1
or CE2 to High-Z Output
0
10
0
15
0
20
0
25
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
IS62C1024
ISSI
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. G
01/14/00
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range, Standard and Low Power)
-35
-45
-55
-70
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
WC
Write Cycle Time
35
--
45
--
55
--
70
--
ns
t
SCE
1
CE1
to Write End
25
--
35
--
50
--
60
--
ns
t
SCE
2
CE2 to Write End
25
--
35
--
50
--
60
--
ns
t
AW
Address Setup Time to Write End
25
--
35
--
45
--
60
--
ns
t
HA
Address Hold from Write End
0
--
0
--
0
--
0
--
ns
t
SA
Address Setup Time
0
--
0
--
0
--
0
--
ns
t
PWE
(4)
WE
Pulse Width
25
--
35
--
40
--
50
--
ns
t
SD
Data Setup to Write End
20
--
25
--
25
--
30
--
ns
t
HD
Data Hold from Write End
0
--
0
--
0
--
0
--
ns
t
HZWE
(2)
WE
LOW to High-Z Output
--
10
--
15
--
20
--
25
ns
t
LZWE
(2)
WE
HIGH to Low-Z Output
3
--
5
--
5
--
5
--
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with
OE
HIGH.
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE1/
t
ACE2
t
LZCE1/
t
LZCE2
t
HZOE
HIGH-Z
DATA VALID
t
HZCE
ADDRESS
OE
CE1
CE2
DOUT
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE
,
CE1
= V
IL
, CE2 = V
IH
.
3. Address is valid prior to or coincident with
CE1
LOW and CE2 HIGH transitions.
READ CYCLE NO. 2
(1,3)
IS62C1024
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
7
Rev. G
01/14/00
WRITE CYCLE NO. 2 (
CE1
, CE2 Controlled)
(1,2)
HIGH-Z
DATA UNDEFINED
DATA-IN VALID
t
WC
t
SCE1
t
SA
t
HA
t
SCE2
t
PWE
(4)
t
AW
t
HZWE
t
SD
t
HD
t
LZWE
ADDRESS
DIN
CE1
CE2
WE
DOUT
Notes:
1. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE
= V
IH
.
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCE1
t
SCE2
t
AW
t
HA
t
PWE
(4)
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CE1
CE2
WE
DOUT
DIN
AC WAVEFORMS
WRITE CYCLE NO. 1 (
WE
Controlled)
(1,2)
IS62C1024
ISSI
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. G
01/14/00
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
ORDERING INFORMATION
Commercial Range: 0C to +70C
Speed (ns)
Order Part No.
Package
35
IS62C1024-35Q
525-mil Plastic SOP
35
IS62C1024-35T
TSOP, Type 1
45
IS62C1024-45Q
525-mil Plastic SOP
45
IS62C1024-45T
TSOP, Type 1
55
IS62C1024-55Q
525-mil Plastic SOP
55
IS62C1024-55T
TSOP, Type 1
70
IS62C1024-70Q
525-mil Plastic SOP
70
IS62C1024-70T
TSOP, Type 1
Industrial Range: 40C to +85C
Speed (ns)
Order Part No.
Package
35
IS62C1024-35QI
525-mil Plastic SOP
35
IS62C1024-35TI
TSOP, Type 1
45
IS62C1024-45QI
525-mil Plastic SOP
45
IS62C1024-45TI
TSOP, Type 1
55
IS62C1024-55QI
525-mil Plastic SOP
55
IS62C1024-55TI
TSOP, Type 1
70
IS62C1024-70QI
525-mil Plastic SOP
70
IS62C1024-70TI
TSOP, Type 1