ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. Copyright 1999, Integrated Silicon Solution, Inc.
FEATURES
High-speed access time: 15, 20, 25 ns
Automatic power-down when chip is deselected
CMOS low power operation
-- 255 mW (max.) operating
-- 0.18 mW (max.) CMOS standby
TTL compatible interface levels
Single 3.3V power supply
Fully static operation: no clock or refresh
required
Three-state outputs
DESCRIPTION
The
ISSI
IS62LV256L is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using
ISSI
's
high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 15 ns maximum.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation is reduced to
50
W (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (
CE
). The active LOW Write Enable (
WE
) controls
both writing and reading of the memory.
The IS62LV256L is available in the JEDEC standard 28-pin
SOJ and the 450-mil TSOP package.
IS62LV256L
32K x 8 LOW VOLTAGE
CMOS STATIC RAM
FUNCTIONAL BLOCK DIAGRAM
A0-A14
CE
OE
WE
256 X 1024
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
APRIL 1999
Integrated Silicon Solution, Inc.
1
SR033-1A
04/27/99
ISSI
IS62LV256L
2
Integrated Silicon Solution, Inc.
SR033-1A
04/27/99
ISSI
PIN CONFIGURATION
28-Pin SOJ
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
28-Pin TSOP
PIN DESCRIPTIONS
A0-A14
Address Inputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
Vcc
Power
GND
Ground
TRUTH TABLE
Mode
WE
WE
WE
WE
WE
CE
CE
CE
CE
CE
OE
OE
OE
OE
OE
I/O Operation
Vcc Current
Not Selected
X
H
X
High-Z
I
SB
1
, I
SB
2
(Power-down)
Output Disabled
H
L
H
High-Z
I
CC
1
, I
CC
2
Read
H
L
L
D
OUT
I
CC
1
, I
CC
2
Write
L
L
X
D
IN
I
CC
1
, I
CC
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to +4.6
V
T
BIAS
Temperature Under Bias
55 to +125
C
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
0.5
W
I
OUT
DC Output Current (LOW)
20
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
IS62LV256L
Integrated Silicon Solution, Inc.
3
SR033-1A
04/27/99
ISSI
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 2.0 mA
2.4
--
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 4.0 mA
--
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
(1)
0.3
0.8
V
I
LI
Input Leakage
GND
V
IN
V
CC
Com.
2
2
A
Ind.
5
5
I
LO
Output Leakage
GND
V
OUT
V
CC
, Outputs Disabled
Com.
2
2
A
Ind.
5
5
Notes:
1. V
IL
= 3.0V for pulse width less than 10 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
5
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25
C, f = 1 MHz, Vcc = 3.3V.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-15 ns
-20 ns
-25 ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
I
CC
1
Vcc Operating
V
CC
= Max.,
CE
= V
IL
Com.
--
1
--
1
--
1
mA
Supply Current
I
OUT
= 0 mA, f = 0
Ind.
--
2
--
2
--
2
I
CC
2
Vcc Dynamic Operating
V
CC
= Max.,
CE
= V
IL
Com.
--
70
--
60
--
50
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
--
80
--
70
--
60
I
SB
1
TTL Standby Current
V
CC
= Max.,
Com.
--
3
--
3
--
3
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
Ind.
--
5
--
5
--
5
CE
V
IH
, f = 0
I
SB
2
CMOS Standby
V
CC
= Max.,
Com.
--
80
--
80
--
80
A
Current (CMOS Inputs)
CE
V
CC
0.2V,
Ind.
--
100
--
100
-- 100
V
IN
> V
CC
0.2V, or
V
IN
0.2V, f = 0
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
OPERATING RANGE
Range
Ambient Temperature
V
CC
Commercial
0
C to +70
C
3.3V +10%
Industrial
40
C to +85
C
3.3V
10%
IS62LV256L
4
Integrated Silicon Solution, Inc.
SR033-1A
04/27/99
ISSI
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-15 ns
-20 ns
-25 ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
15
--
20
--
25
--
ns
t
AA
Address Access Time
--
15
--
20
--
25
ns
t
OHA
Output Hold Time
2
--
2
--
2
--
ns
t
ACE
CE
Access Time
--
15
--
20
--
25
ns
t
DOE
OE
Access Time
--
7
--
8
--
9
ns
t
LZOE
(2)
OE
to Low-Z Output
0
--
0
--
0
--
ns
t
HZOE
(2)
OE
to High-Z Output
--
8
--
9
--
10
ns
t
LZCE
(2)
CE
to Low-Z Output
3
--
3
--
3
--
ns
t
HZCE
(2)
CE
to High-Z Output
--
6
--
9
--
10
ns
t
PU
(3)
CE
to Power-Up
0
--
0
--
0
--
ns
t
PD
(3)
CE
to Power-Down
--
15
--
18
--
20
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured
500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST LOADS
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
3 ns
Input and Output Timing
1.5V
and Reference Levels
Output Load
See Figures 1 and 2
Figure 1.
Figure 2.
635
30 pF
Including
jig and
scope
702
OUTPUT
3.3V
635
5 pF
Including
jig and
scope
702
OUTPUT
3.3V
IS62LV256L
Integrated Silicon Solution, Inc.
5
SR033-1A
04/27/99
ISSI
DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
50%
50%
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
t
PD
HIGH-Z
t
PU
DATA VALID
t
HZCE
ISB
ADDRESS
OE
CE
D
OUT
SUPPLY
CURRENT
ICC
READ CYCLE NO. 2
(1,3)
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE
,
CE
= V
IL
.
3. Address is valid prior to or coincident with
CE
LOW transitions.
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
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