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Электронный компонент: IS62WV5128CLL-55B2I

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Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
Rev. 00B
03/13/03
IS62WV5128CLL
ISSI
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
512K x 8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
High-speed access time: 55ns, 70ns
CMOS low power operation
1.5 W (typical) CMOS standby
TTL compatible interface levels
Single power supply
2.5V--3.6V V
DD
(62WV5128CLL)
Fully static operation: no clock or refresh
required
Three state outputs
Industrial temperature available
2 CS Options Available
DESCRIPTION
The
ISSI
IS62WV5128CLL are high-speed, 4M bit static
RAMs organized as 512K words by 8 bits. It is fabricated
using
ISSI
's high-performance CMOS technology. This
highly reliable process coupled with innovative circuit
design techniques, yields high-performance and low power
consumption devices.
When
CS1
is HIGH (deselected) or when CS2 is LOW
(deselected) the device assumes a standby mode at
which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE)
controls both writing and reading of the memory.
The IS62WV5128CLL is packaged in the JEDEC standard
36-pin mini BGA (6mm x 8mm). 36-pin mini BGA is
available in both 1CS and 2CS options.
FUNCTIONAL BLOCK DIAGRAM
MARCH 2003
A0-A18
CS1
OE
WE
512K x 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
CS2
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. 00B
03/13/03
IS62WV5128CLL
ISSI
PIN DESCRIPTIONS
A0-A18
Address Inputs
CS1
Chip Enable 1 Input
CS2
Chip Enable 2 Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
NC
No Connection
V
DD
Power
GND
Ground
36-pin mini BGA (B) (6mm x 8mm)
2 CS Option (Package Code B2)
PIN CONFIGURATION
1 2 3 4 5 6
A
B
C
D
E
F
G
H
A0
I/O4
I/O5
GND
V
DD
I/O6
I/O7
A9
A1
A2
OE
A10
NC
WE
NC
A18
CS1
A11
A3
A4
A5
A17
A16
A12
A6
A7
A15
A13
A8
I/O0
I/O1
V
DD
GND
I/O2
I/O3
A14
36-pin mini BGA (B) (6mm x 8mm)
(Package Code B)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
A0
I/O4
I/O5
GND
V
DD
I/O6
I/O7
A9
A1
A2
OE
A10
CS2
WE
NC
A18
CS1
A11
A3
A4
A5
A17
A16
A12
A6
A7
A15
A13
A8
I/O0
I/O1
V
DD
GND
I/O2
I/O3
A14
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
3
Rev. 00B
03/13/03
IS62WV5128CLL
ISSI
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
Parameter
Test Conditions
V
DD
Min.
Max.
Unit
V
OH
Output HIGH Voltage
I
OH
= -1 mA
2.5-3.6V
2.2
--
V
V
OL
Output LOW Voltage
I
OL
= 2.1 mA
2.5-3.6V
--
0.4
V
V
IH
Input HIGH Voltage
2.5-3.6V
2.2
V
DD
+ 0.3
V
V
IL
(1)
Input LOW Voltage
2.5-3.6V
0.2
0.6
V
I
LI
Input Leakage
GND
V
IN
V
DD
1
1
A
I
LO
Output Leakage
GND
V
OUT
V
DD
, Outputs Disabled
1
1
A
Notes:
1. V
IL
(min.) = 1.0V for pulse width less than 10 ns.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.3 to V
DD
+0.5
V
V
DD
V
DD
Related to GND
0.2 to +4.2
V
T
STG
Storage Temperature
55 to +125
C
P
T
Power Dissipation
0.6
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
OPERATING RANGE (V
DD
)
Range
Ambient Temperature
V
DD
Commercial
0C to +70C
2.5V - 3.6V
Industrial
40C to +85C
2.5V - 3.6V
TRUTH TABLE
Mode
WE
WE
WE
WE
WE
CS1
CS1
CS1
CS1
CS1
CS2
OE
OE
OE
OE
OE
I/O Operation
V
DD
Current
Not Selected
X
H
X
X
High-Z
I
SB
1, I
SB
2
(Power-down)
X
X
L
X
High-Z
I
SB
1, I
SB
2
Output Disable
H
L
H
H
High-Z
Icc
Read
H
L
H
L
D
OUT
Icc
Write
L
L
H
X
D
IN
Icc
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. 00B
03/13/03
IS62WV5128CLL
ISSI
AC TEST LOADS
Figure 1
Figure 2
CAPACITANCE
(1)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
8
pF
C
OUT
Input/Output Capacitance
V
OUT
= 0V
10
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST CONDITIONS
Parameter
62WV5128CLL
(Unit)
Input Pulse Level
0.4 to V
DD
-0.3V
Input Rise and Fall Times
5ns
Input and Output Timing
V
REF
and Reference Level
Output Load
See Figures 1 and 2
2.5V - 3.6V
R1(
)
3070
R2(
)
3150
V
REF
1.5V
V
TM
2.8V
R1
30 pF
Including
jig and
scope
R2
OUTPUT
VTM
R1
5 pF
Including
jig and
scope
R2
OUTPUT
VTM
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
Rev. 00B
03/13/03
IS62WV5128CLL
ISSI
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
62WV5128CLL
(2.5V - 3.6V)
Symbol
Parameter
Test Conditions
Max.
Max.
Unit
55 ns
70 ns
I
CC
V
DD
Dynamic Operating
V
DD
= Max.,
Com.
50
45
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
55
50
I
CC
1
Operating Supply
V
DD
= Max.,
Com.
2
2
mA
Current
I
OUT
= 0 mA, f = 0
Ind.
3
3
I
SB
1
TTL Standby Current
V
DD
= Max.,
Com.
0.6
0.6
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
Ind.
0.8
0.8
CS1
= V
IH
, CS2 = V
IL
,
f = 1 MH
Z
I
SB
2
CMOS Standby
V
DD
= Max.,
Com.
10
10
A
Current (CMOS Inputs)
CS1
V
DD
0.2V,
Ind.
10
10
CS2
0.2V,
typ
(2)
0.5
0.5
V
IN
V
DD
0.2V, or
Vin
0.2V, f = 0
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at V
DD
= 3.0V, T
A
= 25
o
C. Not 100% tested.
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
55 ns
70 ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
55
--
70
--
ns
t
AA
Address Access Time
--
55
--
70
ns
t
OHA
Output Hold Time
10
--
10
--
ns
t
ACS1/
t
ACS2
CS1/
CS2 Access Time
--
55
--
70
ns
t
DOE
OE
Access Time
--
35
--
40
ns
t
HZOE
(2)
OE
to High-Z Output
--
20
--
25
ns
t
LZOE
(2)
OE
to Low-Z Output
5
--
5
--
ns
t
HZCS1/
t
HZCS2
(2)
CS1/
CS2 to High-Z Output
0
20
0
25
ns
t
LZCS1/
t
LZCS2
(2)
CS1/
CS2 to Low-Z Output
10
--
10
--
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4 to V
DD
-
0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
6
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. 00B
03/13/03
IS62WV5128CLL
ISSI
AC WAVEFORMS
READ CYCLE NO. 2
(1,3)
(
CS1
,
CS2,
OE
Controlled)
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE
,
CS1
= V
IL
. CS2=
WE
=V
IH
.
3. Address is valid prior to or coincident with
CS1
LOW and CS2 HIGH transition.
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACS1/
t
ACS2
t
LZCS1/
t
LZCS2
t
HZOE
HIGH-Z
DATA VALID
t
HZCS
ADDRESS
OE
CS1
CS2
DOUT
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (
CS1
=
OE
= V
IL
,
CS2 =
WE
= V
IH
)
DATA VALID
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
7
Rev. 00B
03/13/03
IS62WV5128CLL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
55 ns
70 ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
t
WC
Write Cycle Time
55
--
70
--
ns
t
SCS1/
t
SCS2
CS1/
CS2 to Write End
45
--
60
--
ns
t
AW
Address Setup Time to Write End
45
--
60
--
ns
t
HA
Address Hold from Write End
0
--
0
--
ns
t
SA
Address Setup Time
0
--
0
--
ns
t
PWE
WE
Pulse Width
40
--
50
--
ns
t
SD
Data Setup to Write End
25
--
30
--
ns
t
HD
Data Hold from Write End
0
--
0
--
ns
t
HZWE
(3)
WE
LOW to High-Z Output
--
20
--
20
ns
t
LZWE
(3)
WE
HIGH to Low-Z Output
5
--
5
--
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to V
DD
-
0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of
CS1
LOW, CS2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (
CS1
/CS2 Controlled,
OE
= HIGH or LOW)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CS1
CS2
WE
DOUT
DIN
8
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. 00B
03/13/03
IS62WV5128CLL
ISSI
WRITE CYCLE NO. 2
(
WE
Controlled:
OE
is HIGH During Write Cycle)
WRITE CYCLE NO. 3
(
WE
Controlled:
OE
is LOW During Write Cycle)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
CS2
WE
DOUT
DIN
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
CS2
WE
DOUT
DIN
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
9
Rev. 00B
03/13/03
IS62WV5128CLL
ISSI
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Max.
Unit
V
DR
V
DD
for Data Retention
See Data Retention Waveform
1.5
3.6
V
I
DR
Data Retention Current
V
DD
= 1.5V,
CS1/
CS2
V
DD
0.2V
--
10
A
t
SDR
Data Retention Setup Time
See Data Retention Waveform
0
--
ns
t
RDR
Recovery Time
See Data Retention Waveform
t
RC
--
ns
DATA RETENTION WAVEFORM (
CS1
CS1
CS1
CS1
CS1
Controlled)
DATA RETENTION WAVEFORM (CS2 Controlled)
V
DD
CS1 V
DD
-
0.2V
t
SDR
t
RDR
V
DR
CS1
GND
3.0V
2.2V
Data Retention Mode
V
DD
CS2
0.2V
t
SDR
t
RDR
V
DR
0.4V
CS2
GND
3.0
2.2V
Data Retention Mode
10
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. 00B
03/13/03
IS62WV5128CLL
ISSI
ORDERING INFORMATION
IS62WV5128CLL (2.5V - 3.6V)
Commercial Range: 0C to +70C
Speed (ns)
Order Part No.
Package
55
IS62WV5128CLL-55B
mini BGA (6mm x 8mm)
55
IS62WV5128CLL-55B2
mini BGA (6mm x 8mm) 2CS
Industrial Range: 40C to +85C
Speed (ns)
Order Part No.
Package
55
IS62WV5128CLL-55BI
mini BGA (6mm x 8mm)
55
IS62WV5128CLL-55B2I
mini BGA (6mm x 8mm) 2CS
70
IS62WV5128CLL-70BI
mini BGA (6mm x 8mm)
70
IS62WV5128CLL-70B2I
mini BGA (6mm x 8mm) 2CS
PACKAGING INFORMATION
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. E
01/15/03
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Mini Ball Grid Array
Package Code: B (36-pin)
Notes:
1. Controlling dimensions are in millimeters.
mBGA - 6mm x 8mm
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
36
36
A
--
--
1.20
--
--
0.047
A1
0.24
--
0.30
0.009
--
0.012
A2
0.60
--
--
0.024
--
--
D
7.90
8.00
8.10
0.311 0.315 0.319
D1
5.25BSC
0.207BSC
E
5.90
6.00
6.10
0.232 0.236 0.240
E1
3.75BSC
0.148BSC
e
0.75BSC
0.030BSC
b
0.30
0.35
0.40
0.012 0.014 0.016
mBGA - 8mm x 10mm
MILLIMETER
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
36
36
A
--
--
1.20
--
--
0.047
A1
0.24
--
0.30
0.009
--
0.012
A2
0.60
--
--
0.024
--
--
D
9.90 10.00 10.10
0.390 0.394 0.398
D1
5.25BSC
.207BSC
E
7.90
8.00
8.10
0.311 0.315 0.319
E1
3.75BSC
0.148BSC
e
0.75BSC
0.030BSC
b
0.30
0.35
0.40
0.012 0.014 0.016
SEATING PLANE
A
A1
A2
A
B
C
D
E
F
G
H
e
e
D1
E1
E
D
b (36x)
Top View
Bottom View
6 5 4 3 2 1
1 2 3 4 5 6
A
B
C
D
E
F
G
H