ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.

IS63LV1024

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. H
10/02/00

128K x 8 HIGH-SPEED CMOS STATIC RAM
3.3V REVOLUTIONARY PINOUT

FEATURES

· High-speed access times:

8, 10, 12 and 15 ns

· High-performance, low-power CMOS process

· Multiple center power and ground pins for

greater noise immunity

· Easy memory expansion with

CE and OE

options

CE power-down

· Fully static operation: no clock or refresh

required

· TTL compatible inputs and outputs

· Single 3.3V power supply

· Packages available:

32-pin 300-mil SOJ
32-pin 400-mil SOJ
32-pin TSOP (Type II)

DESCRIPTION

The

ISSI

IS63LV1024 is a very high-speed, low power,

131,072-word by 8-bit CMOS static RAM in revolutionary
pinout. The IS63LV1024 is fabricated using

ISSI

high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design
techniques, yields higher performance and low power
consumption devices.

When

CE is HIGH (deselected), the device assumes a

standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.

The IS63LV1024 operates from a single 3.3V power
supply and all inputs are TTL-compatible.

FUNCTIONAL BLOCK DIAGRAM

A0-A16

128K X 8

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

SEPTEMBER 2000

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. H

10/02/00

IS63LV1024

ISSI

PIN CONFIGURATION

32-Pin SOJ

I/O0

I/O1

Vcc

GND

I/O2

I/O3

A16

A15

A14

A13

I/O7

I/O6

GND

Vcc

I/O5

I/O4

A12

A11

A10

PIN DESCRIPTIONS

A0-A16

Address Inputs

Chip Enable Input

Output Enable Input

Write Enable Input

I/O0-I/O7

Bidirectional Ports

Vcc

Power

GND

Ground

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

TERM

Terminal Voltage with Respect to GND

0.5 to Vcc + 0.5

BIAS

Temperature Under Bias

55 to +125

°C

STG

Storage Temperature

65 to +150

°C

Power Dissipation

1.0

Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

TRUTH TABLE

Mode

I/O Operation Vcc Current

Not Selected

High-Z

, I

(Power-down)

Output Disabled H

High-Z

, I

Read

OUT

, I

Write

, I

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

A0
A1
A2
A3

I/O0
I/O1

Vcc

GND

I/O2
I/O3

A4
A5
A6
A7

A16
A15
A14
A13
OE
I/o7
I/O6
GND
Vcc
I/O5
I/O4
A12
A11
A10
A9
A8

PIN CONFIGURATION

32-Pin TSOP (Type II) (T)

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. H
10/02/00

IS63LV1024

ISSI

DC ELECTRICAL CHARACTERISTICS

(Over Operating Range)

Symbol Parameter

Test Conditions

Min.

Max.

Unit

Output HIGH Voltage

= Min., I

= 4.0 mA

2.4

Output LOW Voltage

= Min., I

= 8.0 mA

0.4

Input HIGH Voltage

2.2

+ 0.3

Input LOW Voltage

(1)

0.3

0.8

Input Leakage

GND

Com.

µA

Ind.

Output Leakage

GND

OUT

, Outputs Disabled

Com.

µA

Ind.

Notes:
1. V

= 3.0V for pulse width less than 10 ns.

CAPACITANCE

(1,2)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

I/O

Input/Output Capacitance

OUT

= 0V

Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T

= 25°C, f = 1 MHz, Vcc = 3.3V.

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns

-10 ns

-12 ns

-15 ns

Symbol Parameter

Test Conditions

Min. Max.

Unit

Vcc Operating

= Max.,

CE = V

Com.

160

150

130

120

Supply Current

OUT

= 0 mA, f = Max.

Ind.

170

160

140

130

TTL Standby

= Max.,

Com.

Current

= V

or V

Ind.

(TTL Inputs)

, f = Max

TTL Standby

= Max.,

Com.

Current

= V

or V

Ind.

(TTL Inputs)

, f = 0

CMOS Standby

= Max.,

Com.

Current

0.2V,

Ind.

(CMOS Inputs)

0.2V, or

0.2V, f = 0

Notes:
1. At f = f

MAX

, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

OPERATING RANGE

Range

Ambient Temperature

Commercial

0°C to +70°C

3.3V ± 0.3V

Industrial

40°C to +85°C

3.3V ± 0.15V

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. H

10/02/00

IS63LV1024

ISSI

AC TEST LOADS

AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

3 ns

Input and Output Timing

1.5V

and Reference Levels

Output Load

See Figures 1a and 1b

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns

-10 ns

-12 ns

-15 ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Read Cycle Time

Address Access Time

OHA

Output Hold Time

ACE

CE Access Time

DOE

OE Access Time

LZOE

(2)

OE to Low-Z Output

HZOE

(2)

OE to High-Z Output

LZCE

(2)

CE to Low-Z Output

HZCE

(2)

CE to High-Z Output

CE to Power Up Time

CE to Power Down Time

Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and C1

output loading specified in Figure 1.

2. Tested with the C2 load in Figure 1. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

Figure 1

OUTPUT

= 1.5V

OUT

= 50

317

5 pF

Including

jig and

scope

351

OUTPUT

3.3V

Figure 2

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. H
10/02/00

IS63LV1024

ISSI

DATA VALID

READ1.eps

PREVIOUS DATA VALID

OHA

OUT

ADDRESS

OHA

DOE

LZOE

ACE

LZCE

HZOE

HIGH-Z

DATA VALID

CE_RD2.eps

ADDRESS

OUT

HZCE

READ CYCLE NO. 2

(1,3)

Notes:
1.

WE is HIGH for a Read Cycle.

2. The device is continuously selected.

OE, CE = V

3. Address is valid prior to or coincident with

CE LOW transitions.

AC WAVEFORMS

READ CYCLE NO. 1

(1,2)

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. H

10/02/00

IS63LV1024

ISSI

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,3)

(Over Operating Range)

-8 ns

-10 ns

-12 ns

-15 ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Write Cycle Time

SCE

CE to Write End

Address Setup Time to

Write End

Address Hold from

Write End

Address Setup Time

PWE

(1)

WE Pulse Width (OE High)

PWE

(2)

WE Pulse Width (OE Low)

Data Setup to Write End

Data Hold from Write End

HZWE

(2)

WE LOW to High-Z Output

LZWE

(2)

WE HIGH to Low-Z Output

Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and

output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of

CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but

any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.

AC WAVEFORMS

WRITE CYCLE NO. 1

(1,2

(

CE Controlled, OE = HIGH or LOW)

DATA UNDEFINED

VALID ADDRESS

SCE

PWE1

PWE2

HIGH-Z

HZWE

ADDRESS

OUT

DATA

VALID

LZWE

CE_WR1.eps

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. H
10/02/00

IS63LV1024

ISSI

DATA UNDEFINED

LOW

VALID ADDRESS

PWE1

HIGH-Z

HZWE

ADDRESS

OUT

DATA

VALID

LZWE

CE_WR2.eps

WRITE CYCLE NO. 2

(1)

(

WE Controlled, OE = HIGH during Write Cycle)

WRITE CYCLE NO. 3

(

WE Controlled: OE is LOW During Write Cycle)

DATA UNDEFINED

VALID ADDRESS

LOW

PWE2

HIGH-Z

HZWE

ADDRESS

OUT

DATA

VALID

LZWE

CE_WR3.eps

Notes:
1. The internal write time is defined by the overlap of

CE LOW and WE LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if

OE · V

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. H

10/02/00

IS63LV1024

ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: 1-800-379-4774

Fax: (408) 588-0806

E-mail: sales@issi.com

www.issi.com

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed (ns)

Order Part No.

Package

IS63LV1024-8T

TSOP (Type II)

IS63LV1024-8J

300-mil Plastic SOJ

IS63LV1024-8K

400-mil Plastic SOJ

IS63LV1024-10T

TSOP (Type II)

IS63LV1024-10J

300-mil Plastic SOJ

IS63LV1024-10K

400-mil Plastic SOJ

IS63LV1024-12T

TSOP (Type II)

IS63LV1024-12J

300-mil Plastic SOJ

IS63LV1024-12K

400-mil Plastic SOJ

IS63LV1024-15T

TSOP (Type II)

IS63LV1024-15J

300-mil Plastic SOJ

IS63LV1024-15K

400-mil Plastic SOJ

Industrial Range: 40°C to +85°C

Speed (ns)

Order Part No.

Package

IS63LV1024-8TI

TSOP (Type II)

IS63LV1024-8JI

300-mil Plastic SOJ

IS63LV1024-8KI

400-mil Plastic SOJ

IS63LV1024-10TI

TSOP (Type II)

IS63LV1024-10JI

300-mil Plastic SOJ

IS63LV1024-10KI

400-mil Plastic SOJ

IS63LV1024-12TI

TSOP (Type II)

IS63LV1024-12JI

300-mil Plastic SOJ

IS63LV1024-12KI

400-mil Plastic SOJ

IS63LV1024-15TI

TSOP (Type II)

IS63LV1024-15JI

300-mil Plastic SOJ

IS63LV1024-15KI

400-mil Plastic SOJ

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IS63LV1024-15I

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IS63LV1024-15I